1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -instcombine < %s | FileCheck %s 3 4define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) { 5; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe( 6; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 7; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 8; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 9; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 10; CHECK-NEXT: ret i64 [[TMP4]] 11; 12 %1 = and i32 %x, 15 13 %2 = shl nuw nsw i32 %1, 2 14 %3 = zext i32 %2 to i64 15 %4 = icmp eq i32 %1, 0 16 %5 = ashr i64 %y, %3 17 %6 = select i1 %4, i64 %y, i64 %5 18 ret i64 %6 19} 20 21define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) { 22; CHECK-LABEL: @test_shl_nuw__all_are_safe( 23; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 24; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 25; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 26; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 27; CHECK-NEXT: ret i64 [[TMP4]] 28; 29 %1 = and i32 %x, 15 30 %2 = shl nuw i32 %1, 2 31 %3 = zext i32 %2 to i64 32 %4 = icmp eq i32 %1, 0 33 %5 = ashr i64 %y, %3 34 %6 = select i1 %4, i64 %y, i64 %5 35 ret i64 %6 36} 37 38define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) { 39; CHECK-LABEL: @test_shl_nsw__all_are_safe( 40; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 41; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 42; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 43; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 44; CHECK-NEXT: ret i64 [[TMP4]] 45; 46 %1 = and i32 %x, 15 47 %2 = shl nsw i32 %1, 2 48 %3 = zext i32 %2 to i64 49 %4 = icmp eq i32 %1, 0 50 %5 = ashr i64 %y, %3 51 %6 = select i1 %4, i64 %y, i64 %5 52 ret i64 %6 53} 54 55define i64 @test_shl__all_are_safe(i32 %x, i64 %y) { 56; CHECK-LABEL: @test_shl__all_are_safe( 57; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 58; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 59; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 60; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 61; CHECK-NEXT: ret i64 [[TMP4]] 62; 63 %1 = and i32 %x, 15 64 %2 = shl i32 %1, 2 65 %3 = zext i32 %2 to i64 66 %4 = icmp eq i32 %1, 0 67 %5 = ashr i64 %y, %3 68 %6 = select i1 %4, i64 %y, i64 %5 69 ret i64 %6 70} 71 72define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) { 73; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe( 74; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 75; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 76; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 77; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 78; CHECK-NEXT: ret i64 [[TMP4]] 79; 80 %1 = and i32 %x, 1073741822 81 %2 = shl nuw nsw i32 %1, 2 82 %3 = zext i32 %2 to i64 83 %4 = icmp eq i32 %1, 0 84 %5 = ashr i64 %y, %3 85 %6 = select i1 %4, i64 %y, i64 %5 86 ret i64 %6 87} 88 89define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) { 90; CHECK-LABEL: @test_shl_nuw__nuw_is_safe( 91; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 92; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 93; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 94; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 95; CHECK-NEXT: ret i64 [[TMP4]] 96; 97 %1 = and i32 %x, 1073741822 98 %2 = shl nuw i32 %1, 2 99 %3 = zext i32 %2 to i64 100 %4 = icmp eq i32 %1, 0 101 %5 = ashr i64 %y, %3 102 %6 = select i1 %4, i64 %y, i64 %5 103 ret i64 %6 104} 105 106define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) { 107; CHECK-LABEL: @test_shl_nsw__nuw_is_safe( 108; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 109; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 110; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 111; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 112; CHECK-NEXT: ret i64 [[TMP4]] 113; 114 %1 = and i32 %x, 1073741822 115 %2 = shl nsw i32 %1, 2 116 %3 = zext i32 %2 to i64 117 %4 = icmp eq i32 %1, 0 118 %5 = ashr i64 %y, %3 119 %6 = select i1 %4, i64 %y, i64 %5 120 ret i64 %6 121} 122 123define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) { 124; CHECK-LABEL: @test_shl__nuw_is_safe( 125; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 126; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 127; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 128; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 129; CHECK-NEXT: ret i64 [[TMP4]] 130; 131 %1 = and i32 %x, 1073741822 132 %2 = shl i32 %1, 2 133 %3 = zext i32 %2 to i64 134 %4 = icmp eq i32 %1, 0 135 %5 = ashr i64 %y, %3 136 %6 = select i1 %4, i64 %y, i64 %5 137 ret i64 %6 138} 139 140define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) { 141; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe( 142; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 143; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 144; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 145; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 146; CHECK-NEXT: ret i32 [[TMP4]] 147; 148 %1 = or i32 %x, -83886080 149 %2 = icmp eq i32 %1, -83886079 150 %3 = shl nuw nsw i32 %1, 2 151 %4 = select i1 %2, i32 -335544316, i32 %3 152 %5 = mul i32 %4, %1 153 %6 = mul i32 %5, %3 154 ret i32 %6 155} 156 157define i32 @test_shl_nuw__nsw_is_safe(i32 %x) { 158; CHECK-LABEL: @test_shl_nuw__nsw_is_safe( 159; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 160; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 161; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 162; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 163; CHECK-NEXT: ret i32 [[TMP4]] 164; 165 %1 = or i32 %x, -83886080 166 %2 = icmp eq i32 %1, -83886079 167 %3 = shl nuw i32 %1, 2 168 %4 = select i1 %2, i32 -335544316, i32 %3 169 %5 = mul i32 %4, %1 170 %6 = mul i32 %5, %3 171 ret i32 %6 172} 173 174define i32 @test_shl_nsw__nsw_is_safe(i32 %x) { 175; CHECK-LABEL: @test_shl_nsw__nsw_is_safe( 176; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 177; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 178; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 179; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 180; CHECK-NEXT: ret i32 [[TMP4]] 181; 182 %1 = or i32 %x, -83886080 183 %2 = icmp eq i32 %1, -83886079 184 %3 = shl nsw i32 %1, 2 185 %4 = select i1 %2, i32 -335544316, i32 %3 186 %5 = mul i32 %4, %1 187 %6 = mul i32 %5, %3 188 ret i32 %6 189} 190 191define i32 @test_shl__nsw_is_safe(i32 %x) { 192; CHECK-LABEL: @test_shl__nsw_is_safe( 193; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 194; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 195; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 196; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 197; CHECK-NEXT: ret i32 [[TMP4]] 198; 199 %1 = or i32 %x, -83886080 200 %2 = icmp eq i32 %1, -83886079 201 %3 = shl i32 %1, 2 202 %4 = select i1 %2, i32 -335544316, i32 %3 203 %5 = mul i32 %4, %1 204 %6 = mul i32 %5, %3 205 ret i32 %6 206} 207 208 209define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) { 210; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe( 211; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 212; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 213; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 214; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 215; CHECK-NEXT: ret i64 [[TMP4]] 216; 217 %1 = and i32 %x, 4294967294 218 %2 = shl nuw nsw i32 %1, 2 219 %3 = zext i32 %2 to i64 220 %4 = icmp eq i32 %1, 0 221 %5 = ashr i64 %y, %3 222 %6 = select i1 %4, i64 %y, i64 %5 223 ret i64 %6 224} 225 226define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) { 227; CHECK-LABEL: @test_shl_nuw__none_are_safe( 228; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 229; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 230; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 231; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 232; CHECK-NEXT: ret i64 [[TMP4]] 233; 234 %1 = and i32 %x, 4294967294 235 %2 = shl nuw i32 %1, 2 236 %3 = zext i32 %2 to i64 237 %4 = icmp eq i32 %1, 0 238 %5 = ashr i64 %y, %3 239 %6 = select i1 %4, i64 %y, i64 %5 240 ret i64 %6 241} 242 243define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) { 244; CHECK-LABEL: @test_shl_nsw__none_are_safe( 245; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 246; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 247; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 248; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 249; CHECK-NEXT: ret i64 [[TMP4]] 250; 251 %1 = and i32 %x, 4294967294 252 %2 = shl nsw i32 %1, 2 253 %3 = zext i32 %2 to i64 254 %4 = icmp eq i32 %1, 0 255 %5 = ashr i64 %y, %3 256 %6 = select i1 %4, i64 %y, i64 %5 257 ret i64 %6 258} 259 260define i64 @test_shl__none_are_safe(i32 %x, i64 %y) { 261; CHECK-LABEL: @test_shl__none_are_safe( 262; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 263; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 264; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 265; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 266; CHECK-NEXT: ret i64 [[TMP4]] 267; 268 %1 = and i32 %x, 4294967294 269 %2 = shl i32 %1, 2 270 %3 = zext i32 %2 to i64 271 %4 = icmp eq i32 %1, 0 272 %5 = ashr i64 %y, %3 273 %6 = select i1 %4, i64 %y, i64 %5 274 ret i64 %6 275} 276 277define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) { 278; CHECK-LABEL: @test_lshr_exact__exact_is_safe( 279; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 280; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 281; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 282; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 283; CHECK-NEXT: ret i64 [[TMP4]] 284; 285 %1 = and i32 %x, 60 286 %2 = lshr exact i32 %1, 2 287 %3 = zext i32 %2 to i64 288 %4 = icmp eq i32 %1, 0 289 %5 = ashr i64 %y, %3 290 %6 = select i1 %4, i64 %y, i64 %5 291 ret i64 %6 292} 293 294define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) { 295; CHECK-LABEL: @test_lshr__exact_is_safe( 296; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 297; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 298; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 299; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 300; CHECK-NEXT: ret i64 [[TMP4]] 301; 302 %1 = and i32 %x, 60 303 %2 = lshr i32 %1, 2 304 %3 = zext i32 %2 to i64 305 %4 = icmp eq i32 %1, 0 306 %5 = ashr i64 %y, %3 307 %6 = select i1 %4, i64 %y, i64 %5 308 ret i64 %6 309} 310 311define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) { 312; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe( 313; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 314; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 315; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 316; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 317; CHECK-NEXT: ret i64 [[TMP4]] 318; 319 %1 = and i32 %x, 63 320 %2 = lshr exact i32 %1, 2 321 %3 = zext i32 %2 to i64 322 %4 = icmp eq i32 %1, 0 323 %5 = ashr i64 %y, %3 324 %6 = select i1 %4, i64 %y, i64 %5 325 ret i64 %6 326} 327 328define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) { 329; CHECK-LABEL: @test_lshr__exact_is_unsafe( 330; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 331; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 332; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 333; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 334; CHECK-NEXT: ret i64 [[TMP4]] 335; 336 %1 = and i32 %x, 63 337 %2 = lshr i32 %1, 2 338 %3 = zext i32 %2 to i64 339 %4 = icmp eq i32 %1, 0 340 %5 = ashr i64 %y, %3 341 %6 = select i1 %4, i64 %y, i64 %5 342 ret i64 %6 343} 344 345define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) { 346; CHECK-LABEL: @test_ashr_exact__exact_is_safe( 347; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 348; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 349; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 350; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 351; CHECK-NEXT: ret i64 [[TMP4]] 352; 353 %1 = and i32 %x, -2147483588 354 %2 = ashr exact i32 %1, 2 355 %3 = zext i32 %2 to i64 356 %4 = icmp eq i32 %1, 0 357 %5 = ashr i64 %y, %3 358 %6 = select i1 %4, i64 %y, i64 %5 359 ret i64 %6 360} 361 362define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) { 363; CHECK-LABEL: @test_ashr__exact_is_safe( 364; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 365; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 366; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 367; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 368; CHECK-NEXT: ret i64 [[TMP4]] 369; 370 %1 = and i32 %x, -2147483588 371 %2 = ashr i32 %1, 2 372 %3 = zext i32 %2 to i64 373 %4 = icmp eq i32 %1, 0 374 %5 = ashr i64 %y, %3 375 %6 = select i1 %4, i64 %y, i64 %5 376 ret i64 %6 377} 378 379define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) { 380; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe( 381; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 382; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 383; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 384; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 385; CHECK-NEXT: ret i64 [[TMP4]] 386; 387 %1 = and i32 %x, -2147483585 388 %2 = ashr exact i32 %1, 2 389 %3 = zext i32 %2 to i64 390 %4 = icmp eq i32 %1, 0 391 %5 = ashr i64 %y, %3 392 %6 = select i1 %4, i64 %y, i64 %5 393 ret i64 %6 394} 395 396define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) { 397; CHECK-LABEL: @test_ashr__exact_is_unsafe( 398; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 399; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 400; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 401; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 402; CHECK-NEXT: ret i64 [[TMP4]] 403; 404 %1 = and i32 %x, -2147483585 405 %2 = ashr i32 %1, 2 406 %3 = zext i32 %2 to i64 407 %4 = icmp eq i32 %1, 0 408 %5 = ashr i64 %y, %3 409 %6 = select i1 %4, i64 %y, i64 %5 410 ret i64 %6 411} 412 413define i32 @test_add_nuw_nsw__all_are_safe(i32 %x) { 414; CHECK-LABEL: @test_add_nuw_nsw__all_are_safe( 415; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 416; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 417; CHECK-NEXT: ret i32 [[ADD]] 418; 419 %and = and i32 %x, 1073741823 420 %cmp = icmp eq i32 %and, 3 421 %add = add nuw nsw i32 %and, 1 422 %sel = select i1 %cmp, i32 4, i32 %add 423 ret i32 %sel 424} 425 426define i32 @test_add_nuw__all_are_safe(i32 %x) { 427; CHECK-LABEL: @test_add_nuw__all_are_safe( 428; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 429; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 430; CHECK-NEXT: ret i32 [[ADD]] 431; 432 %and = and i32 %x, 1073741823 433 %cmp = icmp eq i32 %and, 3 434 %add = add nuw i32 %and, 1 435 %sel = select i1 %cmp, i32 4, i32 %add 436 ret i32 %sel 437} 438 439define i32 @test_add_nsw__all_are_safe(i32 %x) { 440; CHECK-LABEL: @test_add_nsw__all_are_safe( 441; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 442; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 443; CHECK-NEXT: ret i32 [[ADD]] 444; 445 %and = and i32 %x, 1073741823 446 %cmp = icmp eq i32 %and, 3 447 %add = add nsw i32 %and, 1 448 %sel = select i1 %cmp, i32 4, i32 %add 449 ret i32 %sel 450} 451 452define i32 @test_add__all_are_safe(i32 %x) { 453; CHECK-LABEL: @test_add__all_are_safe( 454; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 455; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 456; CHECK-NEXT: ret i32 [[ADD]] 457; 458 %and = and i32 %x, 1073741823 459 %cmp = icmp eq i32 %and, 3 460 %add = add i32 %and, 1 461 %sel = select i1 %cmp, i32 4, i32 %add 462 ret i32 %sel 463} 464 465define i32 @test_add_nuw_nsw__nuw_is_safe(i32 %x) { 466; CHECK-LABEL: @test_add_nuw_nsw__nuw_is_safe( 467; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 468; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 469; CHECK-NEXT: ret i32 [[ADD]] 470; 471 %and = and i32 %x, 2147483647 472 %cmp = icmp eq i32 %and, 2147483647 473 %add = add nuw nsw i32 %and, 1 474 %sel = select i1 %cmp, i32 -2147483648, i32 %add 475 ret i32 %sel 476} 477 478define i32 @test_add_nuw__nuw_is_safe(i32 %x) { 479; CHECK-LABEL: @test_add_nuw__nuw_is_safe( 480; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 481; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 482; CHECK-NEXT: ret i32 [[ADD]] 483; 484 %and = and i32 %x, 2147483647 485 %cmp = icmp eq i32 %and, 2147483647 486 %add = add nuw i32 %and, 1 487 %sel = select i1 %cmp, i32 -2147483648, i32 %add 488 ret i32 %sel 489} 490 491define i32 @test_add_nsw__nuw_is_safe(i32 %x) { 492; CHECK-LABEL: @test_add_nsw__nuw_is_safe( 493; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 494; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 495; CHECK-NEXT: ret i32 [[ADD]] 496; 497 %and = and i32 %x, 2147483647 498 %cmp = icmp eq i32 %and, 2147483647 499 %add = add nsw i32 %and, 1 500 %sel = select i1 %cmp, i32 -2147483648, i32 %add 501 ret i32 %sel 502} 503 504define i32 @test_add__nuw_is_safe(i32 %x) { 505; CHECK-LABEL: @test_add__nuw_is_safe( 506; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 507; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 508; CHECK-NEXT: ret i32 [[ADD]] 509; 510 %and = and i32 %x, 2147483647 511 %cmp = icmp eq i32 %and, 2147483647 512 %add = add i32 %and, 1 513 %sel = select i1 %cmp, i32 -2147483648, i32 %add 514 ret i32 %sel 515} 516 517define i32 @test_add_nuw_nsw__nsw_is_safe(i32 %x) { 518; CHECK-LABEL: @test_add_nuw_nsw__nsw_is_safe( 519; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 520; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 521; CHECK-NEXT: ret i32 [[ADD]] 522; 523 %or = or i32 %x, -2147483648 524 %cmp = icmp eq i32 %or, -1 525 %add = add nuw nsw i32 %or, 1 526 %sel = select i1 %cmp, i32 0, i32 %add 527 ret i32 %sel 528} 529 530define i32 @test_add_nuw__nsw_is_safe(i32 %x) { 531; CHECK-LABEL: @test_add_nuw__nsw_is_safe( 532; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 533; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 534; CHECK-NEXT: ret i32 [[ADD]] 535; 536 %or = or i32 %x, -2147483648 537 %cmp = icmp eq i32 %or, -1 538 %add = add nuw i32 %or, 1 539 %sel = select i1 %cmp, i32 0, i32 %add 540 ret i32 %sel 541} 542 543define i32 @test_add_nsw__nsw_is_safe(i32 %x) { 544; CHECK-LABEL: @test_add_nsw__nsw_is_safe( 545; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 546; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 547; CHECK-NEXT: ret i32 [[ADD]] 548; 549 %or = or i32 %x, -2147483648 550 %cmp = icmp eq i32 %or, -1 551 %add = add nsw i32 %or, 1 552 %sel = select i1 %cmp, i32 0, i32 %add 553 ret i32 %sel 554} 555 556define i32 @test_add__nsw_is_safe(i32 %x) { 557; CHECK-LABEL: @test_add__nsw_is_safe( 558; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 559; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 560; CHECK-NEXT: ret i32 [[ADD]] 561; 562 %or = or i32 %x, -2147483648 563 %cmp = icmp eq i32 %or, -1 564 %add = add i32 %or, 1 565 %sel = select i1 %cmp, i32 0, i32 %add 566 ret i32 %sel 567} 568 569define i32 @test_add_nuw_nsw__none_are_safe(i32 %x) { 570; CHECK-LABEL: @test_add_nuw_nsw__none_are_safe( 571; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 572; CHECK-NEXT: ret i32 [[ADD]] 573; 574 %cmp = icmp eq i32 %x, 3 575 %add = add nuw nsw i32 %x, 1 576 %sel = select i1 %cmp, i32 4, i32 %add 577 ret i32 %sel 578} 579 580define i32 @test_add_nuw__none_are_safe(i32 %x) { 581; CHECK-LABEL: @test_add_nuw__none_are_safe( 582; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 583; CHECK-NEXT: ret i32 [[ADD]] 584; 585 %cmp = icmp eq i32 %x, 3 586 %add = add nuw i32 %x, 1 587 %sel = select i1 %cmp, i32 4, i32 %add 588 ret i32 %sel 589} 590 591define i32 @test_add_nsw__none_are_safe(i32 %x) { 592; CHECK-LABEL: @test_add_nsw__none_are_safe( 593; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 594; CHECK-NEXT: ret i32 [[ADD]] 595; 596 %cmp = icmp eq i32 %x, 3 597 %add = add nsw i32 %x, 1 598 %sel = select i1 %cmp, i32 4, i32 %add 599 ret i32 %sel 600} 601 602define i32 @test_add__none_are_safe(i32 %x) { 603; CHECK-LABEL: @test_add__none_are_safe( 604; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 605; CHECK-NEXT: ret i32 [[ADD]] 606; 607 %cmp = icmp eq i32 %x, 3 608 %add = add i32 %x, 1 609 %sel = select i1 %cmp, i32 4, i32 %add 610 ret i32 %sel 611} 612 613define i32 @test_sub_nuw_nsw__all_are_safe(i32 %x) { 614; CHECK-LABEL: @test_sub_nuw_nsw__all_are_safe( 615; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 616; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 617; CHECK-NEXT: ret i32 [[SUB]] 618; 619 %and = and i32 %x, 255 620 %cmp = icmp eq i32 %and, 6 621 %sub = sub nuw nsw i32 -254, %and 622 %sel = select i1 %cmp, i32 -260, i32 %sub 623 ret i32 %sel 624} 625 626define i32 @test_sub_nuw__all_are_safe(i32 %x) { 627; CHECK-LABEL: @test_sub_nuw__all_are_safe( 628; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 629; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 630; CHECK-NEXT: ret i32 [[SUB]] 631; 632 %and = and i32 %x, 255 633 %cmp = icmp eq i32 %and, 6 634 %sub = sub nuw i32 -254, %and 635 %sel = select i1 %cmp, i32 -260, i32 %sub 636 ret i32 %sel 637} 638 639define i32 @test_sub_nsw__all_are_safe(i32 %x) { 640; CHECK-LABEL: @test_sub_nsw__all_are_safe( 641; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 642; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 643; CHECK-NEXT: ret i32 [[SUB]] 644; 645 %and = and i32 %x, 255 646 %cmp = icmp eq i32 %and, 6 647 %sub = sub nsw i32 -254, %and 648 %sel = select i1 %cmp, i32 -260, i32 %sub 649 ret i32 %sel 650} 651 652define i32 @test_sub__all_are_safe(i32 %x) { 653; CHECK-LABEL: @test_sub__all_are_safe( 654; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 655; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 656; CHECK-NEXT: ret i32 [[SUB]] 657; 658 %and = and i32 %x, 255 659 %cmp = icmp eq i32 %and, 6 660 %sub = sub i32 -254, %and 661 %sel = select i1 %cmp, i32 -260, i32 %sub 662 ret i32 %sel 663} 664 665define i32 @test_sub_nuw_nsw__nuw_is_safe(i32 %x) { 666; CHECK-LABEL: @test_sub_nuw_nsw__nuw_is_safe( 667; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 668; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 669; CHECK-NEXT: ret i32 [[SUB]] 670; 671 %and = and i32 %x, 2147483647 672 %cmp = icmp eq i32 %and, 1073741824 673 %sub = sub nuw nsw i32 -2147483648, %and 674 %sel = select i1 %cmp, i32 1073741824, i32 %sub 675 ret i32 %sel 676} 677 678define i32 @test_sub_nuw__nuw_is_safe(i32 %x) { 679; CHECK-LABEL: @test_sub_nuw__nuw_is_safe( 680; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 681; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 682; CHECK-NEXT: ret i32 [[SUB]] 683; 684 %and = and i32 %x, 2147483647 685 %cmp = icmp eq i32 %and, 1073741824 686 %sub = sub nuw i32 -2147483648, %and 687 %sel = select i1 %cmp, i32 1073741824, i32 %sub 688 ret i32 %sel 689} 690 691define i32 @test_sub_nsw__nuw_is_safe(i32 %x) { 692; CHECK-LABEL: @test_sub_nsw__nuw_is_safe( 693; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 694; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 695; CHECK-NEXT: ret i32 [[SUB]] 696; 697 %and = and i32 %x, 2147483647 698 %cmp = icmp eq i32 %and, 1073741824 699 %sub = sub nsw i32 -2147483648, %and 700 %sel = select i1 %cmp, i32 1073741824, i32 %sub 701 ret i32 %sel 702} 703 704define i32 @test_sub__nuw_is_safe(i32 %x) { 705; CHECK-LABEL: @test_sub__nuw_is_safe( 706; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 707; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 708; CHECK-NEXT: ret i32 [[SUB]] 709; 710 %and = and i32 %x, 2147483647 711 %cmp = icmp eq i32 %and, 1073741824 712 %sub = sub i32 -2147483648, %and 713 %sel = select i1 %cmp, i32 1073741824, i32 %sub 714 ret i32 %sel 715} 716 717define i32 @test_sub_nuw_nsw__nsw_is_safe(i32 %x) { 718; CHECK-LABEL: @test_sub_nuw_nsw__nsw_is_safe( 719; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 720; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 721; CHECK-NEXT: ret i32 [[SUB]] 722; 723 %or = or i32 %x, -2147483648 724 %cmp = icmp eq i32 %or, -2147483647 725 %sub = sub nuw nsw i32 -2147483648, %or 726 %sel = select i1 %cmp, i32 -1, i32 %sub 727 ret i32 %sel 728} 729 730define i32 @test_sub_nuw__nsw_is_safe(i32 %x) { 731; CHECK-LABEL: @test_sub_nuw__nsw_is_safe( 732; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 733; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 734; CHECK-NEXT: ret i32 [[SUB]] 735; 736 %or = or i32 %x, -2147483648 737 %cmp = icmp eq i32 %or, -2147483647 738 %sub = sub nuw i32 -2147483648, %or 739 %sel = select i1 %cmp, i32 -1, i32 %sub 740 ret i32 %sel 741} 742 743define i32 @test_sub_nsw__nsw_is_safe(i32 %x) { 744; CHECK-LABEL: @test_sub_nsw__nsw_is_safe( 745; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 746; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 747; CHECK-NEXT: ret i32 [[SUB]] 748; 749 %or = or i32 %x, -2147483648 750 %cmp = icmp eq i32 %or, -2147483647 751 %sub = sub nsw i32 -2147483648, %or 752 %sel = select i1 %cmp, i32 -1, i32 %sub 753 ret i32 %sel 754} 755 756define i32 @test_sub__nsw_is_safe(i32 %x) { 757; CHECK-LABEL: @test_sub__nsw_is_safe( 758; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 759; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 760; CHECK-NEXT: ret i32 [[SUB]] 761; 762 %or = or i32 %x, -2147483648 763 %cmp = icmp eq i32 %or, -2147483647 764 %sub = sub i32 -2147483648, %or 765 %sel = select i1 %cmp, i32 -1, i32 %sub 766 ret i32 %sel 767} 768 769define i32 @test_sub_nuw_nsw__none_are_safe(i32 %x) { 770; CHECK-LABEL: @test_sub_nuw_nsw__none_are_safe( 771; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 772; CHECK-NEXT: ret i32 [[SUB]] 773; 774 %cmp = icmp eq i32 %x, 1 775 %sub = sub nuw nsw i32 -2147483648, %x 776 %sel = select i1 %cmp, i32 2147483647, i32 %sub 777 ret i32 %sel 778} 779 780define i32 @test_sub_nuw__none_are_safe(i32 %x) { 781; CHECK-LABEL: @test_sub_nuw__none_are_safe( 782; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 783; CHECK-NEXT: ret i32 [[SUB]] 784; 785 %cmp = icmp eq i32 %x, 1 786 %sub = sub nuw i32 -2147483648, %x 787 %sel = select i1 %cmp, i32 2147483647, i32 %sub 788 ret i32 %sel 789} 790 791define i32 @test_sub_nsw__none_are_safe(i32 %x) { 792; CHECK-LABEL: @test_sub_nsw__none_are_safe( 793; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 794; CHECK-NEXT: ret i32 [[SUB]] 795; 796 %cmp = icmp eq i32 %x, 1 797 %sub = sub nsw i32 -2147483648, %x 798 %sel = select i1 %cmp, i32 2147483647, i32 %sub 799 ret i32 %sel 800} 801 802define i32 @test_sub__none_are_safe(i32 %x) { 803; CHECK-LABEL: @test_sub__none_are_safe( 804; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 805; CHECK-NEXT: ret i32 [[SUB]] 806; 807 %cmp = icmp eq i32 %x, 1 808 %sub = sub i32 -2147483648, %x 809 %sel = select i1 %cmp, i32 2147483647, i32 %sub 810 ret i32 %sel 811} 812 813define i32 @test_mul_nuw_nsw__all_are_safe(i32 %x) { 814; CHECK-LABEL: @test_mul_nuw_nsw__all_are_safe( 815; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 816; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 817; CHECK-NEXT: ret i32 [[MUL]] 818; 819 %and = and i32 %x, 255 820 %cmp = icmp eq i32 %and, 17 821 %mul = mul nuw nsw i32 %and, 9 822 %sel = select i1 %cmp, i32 153, i32 %mul 823 ret i32 %sel 824} 825 826define i32 @test_mul_nuw__all_are_safe(i32 %x) { 827; CHECK-LABEL: @test_mul_nuw__all_are_safe( 828; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 829; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 830; CHECK-NEXT: ret i32 [[MUL]] 831; 832 %and = and i32 %x, 255 833 %cmp = icmp eq i32 %and, 17 834 %mul = mul nuw i32 %and, 9 835 %sel = select i1 %cmp, i32 153, i32 %mul 836 ret i32 %sel 837} 838 839define i32 @test_mul_nsw__all_are_safe(i32 %x) { 840; CHECK-LABEL: @test_mul_nsw__all_are_safe( 841; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 842; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 843; CHECK-NEXT: ret i32 [[MUL]] 844; 845 %and = and i32 %x, 255 846 %cmp = icmp eq i32 %and, 17 847 %mul = mul nsw i32 %and, 9 848 %sel = select i1 %cmp, i32 153, i32 %mul 849 ret i32 %sel 850} 851 852define i32 @test_mul__all_are_safe(i32 %x) { 853; CHECK-LABEL: @test_mul__all_are_safe( 854; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 855; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 856; CHECK-NEXT: ret i32 [[MUL]] 857; 858 %and = and i32 %x, 255 859 %cmp = icmp eq i32 %and, 17 860 %mul = mul i32 %and, 9 861 %sel = select i1 %cmp, i32 153, i32 %mul 862 ret i32 %sel 863} 864 865define i32 @test_mul_nuw_nsw__nuw_is_safe(i32 %x) { 866; CHECK-LABEL: @test_mul_nuw_nsw__nuw_is_safe( 867; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 868; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 869; CHECK-NEXT: ret i32 [[MUL]] 870; 871 %and = and i32 %x, 268435457 872 %cmp = icmp eq i32 %and, 268435456 873 %mul = mul nuw nsw i32 %and, 9 874 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 875 ret i32 %sel 876} 877 878define i32 @test_mul_nuw__nuw_is_safe(i32 %x) { 879; CHECK-LABEL: @test_mul_nuw__nuw_is_safe( 880; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 881; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 882; CHECK-NEXT: ret i32 [[MUL]] 883; 884 %and = and i32 %x, 268435457 885 %cmp = icmp eq i32 %and, 268435456 886 %mul = mul nuw i32 %and, 9 887 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 888 ret i32 %sel 889} 890 891define i32 @test_mul_nsw__nuw_is_safe(i32 %x) { 892; CHECK-LABEL: @test_mul_nsw__nuw_is_safe( 893; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 894; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 895; CHECK-NEXT: ret i32 [[MUL]] 896; 897 %and = and i32 %x, 268435457 898 %cmp = icmp eq i32 %and, 268435456 899 %mul = mul nsw i32 %and, 9 900 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 901 ret i32 %sel 902} 903 904define i32 @test_mul__nuw_is_safe(i32 %x) { 905; CHECK-LABEL: @test_mul__nuw_is_safe( 906; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 907; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 908; CHECK-NEXT: ret i32 [[MUL]] 909; 910 %and = and i32 %x, 268435457 911 %cmp = icmp eq i32 %and, 268435456 912 %mul = mul i32 %and, 9 913 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 914 ret i32 %sel 915} 916 917define i32 @test_mul_nuw_nsw__nsw_is_safe(i32 %x) { 918; CHECK-LABEL: @test_mul_nuw_nsw__nsw_is_safe( 919; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 920; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 921; CHECK-NEXT: ret i32 [[MUL]] 922; 923 %and = or i32 %x, -83886080 924 %cmp = icmp eq i32 %and, -83886079 925 %mul = mul nuw nsw i32 %and, 9 926 %sel = select i1 %cmp, i32 -754974711, i32 %mul 927 ret i32 %sel 928} 929 930define i32 @test_mul_nuw__nsw_is_safe(i32 %x) { 931; CHECK-LABEL: @test_mul_nuw__nsw_is_safe( 932; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 933; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 934; CHECK-NEXT: ret i32 [[MUL]] 935; 936 %and = or i32 %x, -83886080 937 %cmp = icmp eq i32 %and, -83886079 938 %mul = mul nuw i32 %and, 9 939 %sel = select i1 %cmp, i32 -754974711, i32 %mul 940 ret i32 %sel 941} 942 943define i32 @test_mul_nsw__nsw_is_safe(i32 %x) { 944; CHECK-LABEL: @test_mul_nsw__nsw_is_safe( 945; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 946; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 947; CHECK-NEXT: ret i32 [[MUL]] 948; 949 %and = or i32 %x, -83886080 950 %cmp = icmp eq i32 %and, -83886079 951 %mul = mul nsw i32 %and, 9 952 %sel = select i1 %cmp, i32 -754974711, i32 %mul 953 ret i32 %sel 954} 955 956define i32 @test_mul__nsw_is_safe(i32 %x) { 957; CHECK-LABEL: @test_mul__nsw_is_safe( 958; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 959; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 960; CHECK-NEXT: ret i32 [[MUL]] 961; 962 %and = or i32 %x, -83886080 963 %cmp = icmp eq i32 %and, -83886079 964 %mul = mul i32 %and, 9 965 %sel = select i1 %cmp, i32 -754974711, i32 %mul 966 ret i32 %sel 967} 968 969define i32 @test_mul_nuw_nsw__none_are_safe(i32 %x) { 970; CHECK-LABEL: @test_mul_nuw_nsw__none_are_safe( 971; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 972; CHECK-NEXT: ret i32 [[MUL]] 973; 974 %cmp = icmp eq i32 %x, 805306368 975 %mul = mul nuw nsw i32 %x, 9 976 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 977 ret i32 %sel 978} 979 980define i32 @test_mul_nuw__none_are_safe(i32 %x) { 981; CHECK-LABEL: @test_mul_nuw__none_are_safe( 982; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 983; CHECK-NEXT: ret i32 [[MUL]] 984; 985 %cmp = icmp eq i32 %x, 805306368 986 %mul = mul nuw i32 %x, 9 987 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 988 ret i32 %sel 989} 990 991define i32 @test_mul_nsw__none_are_safe(i32 %x) { 992; CHECK-LABEL: @test_mul_nsw__none_are_safe( 993; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 994; CHECK-NEXT: ret i32 [[MUL]] 995; 996 %cmp = icmp eq i32 %x, 805306368 997 %mul = mul nsw i32 %x, 9 998 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 999 ret i32 %sel 1000} 1001 1002define i32 @test_mul__none_are_safe(i32 %x) { 1003; CHECK-LABEL: @test_mul__none_are_safe( 1004; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 1005; CHECK-NEXT: ret i32 [[MUL]] 1006; 1007 %cmp = icmp eq i32 %x, 805306368 1008 %mul = mul i32 %x, 9 1009 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 1010 ret i32 %sel 1011} 1012