1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4; For pattern (X & (signbit << Y)) ==/!= 0 5; it may be optimal to fold into (X l>> Y) >=/< 0 6 7; Scalar tests 8 9define i1 @scalar_i8_signbit_shl_and_eq(i8 %x, i8 %y) { 10; CHECK-LABEL: @scalar_i8_signbit_shl_and_eq( 11; CHECK-NEXT: [[SHL:%.*]] = shl i8 -128, [[Y:%.*]] 12; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHL]], [[X:%.*]] 13; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0 14; CHECK-NEXT: ret i1 [[R]] 15; 16 %shl = shl i8 128, %y 17 %and = and i8 %shl, %x 18 %r = icmp eq i8 %and, 0 19 ret i1 %r 20} 21 22define i1 @scalar_i16_signbit_shl_and_eq(i16 %x, i16 %y) { 23; CHECK-LABEL: @scalar_i16_signbit_shl_and_eq( 24; CHECK-NEXT: [[SHL:%.*]] = shl i16 -32768, [[Y:%.*]] 25; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], [[X:%.*]] 26; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], 0 27; CHECK-NEXT: ret i1 [[R]] 28; 29 %shl = shl i16 32768, %y 30 %and = and i16 %shl, %x 31 %r = icmp eq i16 %and, 0 32 ret i1 %r 33} 34 35define i1 @scalar_i32_signbit_shl_and_eq(i32 %x, i32 %y) { 36; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq( 37; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 38; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 39; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 40; CHECK-NEXT: ret i1 [[R]] 41; 42 %shl = shl i32 2147483648, %y 43 %and = and i32 %shl, %x 44 %r = icmp eq i32 %and, 0 45 ret i1 %r 46} 47 48define i1 @scalar_i64_signbit_shl_and_eq(i64 %x, i64 %y) { 49; CHECK-LABEL: @scalar_i64_signbit_shl_and_eq( 50; CHECK-NEXT: [[SHL:%.*]] = shl i64 -9223372036854775808, [[Y:%.*]] 51; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHL]], [[X:%.*]] 52; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[AND]], 0 53; CHECK-NEXT: ret i1 [[R]] 54; 55 %shl = shl i64 9223372036854775808, %y 56 %and = and i64 %shl, %x 57 %r = icmp eq i64 %and, 0 58 ret i1 %r 59} 60 61define i1 @scalar_i32_signbit_shl_and_ne(i32 %x, i32 %y) { 62; CHECK-LABEL: @scalar_i32_signbit_shl_and_ne( 63; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 64; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 65; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[AND]], 0 66; CHECK-NEXT: ret i1 [[R]] 67; 68 %shl = shl i32 2147483648, %y 69 %and = and i32 %shl, %x 70 %r = icmp ne i32 %and, 0 ; check 'ne' predicate 71 ret i1 %r 72} 73 74; Vector tests 75 76define <4 x i1> @vec_4xi32_signbit_shl_and_eq(<4 x i32> %x, <4 x i32> %y) { 77; CHECK-LABEL: @vec_4xi32_signbit_shl_and_eq( 78; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, [[Y:%.*]] 79; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], [[X:%.*]] 80; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer 81; CHECK-NEXT: ret <4 x i1> [[R]] 82; 83 %shl = shl <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, %y 84 %and = and <4 x i32> %shl, %x 85 %r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 0> 86 ret <4 x i1> %r 87} 88 89define <4 x i1> @vec_4xi32_signbit_shl_and_eq_undef1(<4 x i32> %x, <4 x i32> %y) { 90; CHECK-LABEL: @vec_4xi32_signbit_shl_and_eq_undef1( 91; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> <i32 -2147483648, i32 undef, i32 -2147483648, i32 2147473648>, [[Y:%.*]] 92; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], [[X:%.*]] 93; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer 94; CHECK-NEXT: ret <4 x i1> [[R]] 95; 96 %shl = shl <4 x i32> <i32 2147483648, i32 undef, i32 2147483648, i32 2147473648>, %y 97 %and = and <4 x i32> %shl, %x 98 %r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 0> 99 ret <4 x i1> %r 100} 101 102define <4 x i1> @vec_4xi32_signbit_shl_and_eq_undef2(<4 x i32> %x, <4 x i32> %y) { 103; CHECK-LABEL: @vec_4xi32_signbit_shl_and_eq_undef2( 104; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 2147473648>, [[Y:%.*]] 105; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], [[X:%.*]] 106; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef> 107; CHECK-NEXT: ret <4 x i1> [[R]] 108; 109 %shl = shl <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147473648>, %y 110 %and = and <4 x i32> %shl, %x 111 %r = icmp eq <4 x i32> %and, <i32 0, i32 0, i32 0, i32 undef> 112 ret <4 x i1> %r 113} 114 115define <4 x i1> @vec_4xi32_signbit_shl_and_eq_undef3(<4 x i32> %x, <4 x i32> %y) { 116; CHECK-LABEL: @vec_4xi32_signbit_shl_and_eq_undef3( 117; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> <i32 -2147483648, i32 undef, i32 -2147483648, i32 2147473648>, [[Y:%.*]] 118; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], [[X:%.*]] 119; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 undef, i32 0, i32 0, i32 0> 120; CHECK-NEXT: ret <4 x i1> [[R]] 121; 122 %shl = shl <4 x i32> <i32 2147483648, i32 undef, i32 2147483648, i32 2147473648>, %y 123 %and = and <4 x i32> %shl, %x 124 %r = icmp eq <4 x i32> %and, <i32 undef, i32 0, i32 0, i32 0> 125 ret <4 x i1> %r 126} 127 128; Extra use 129 130; Fold happened 131define i1 @scalar_i32_signbit_shl_and_eq_extra_use_shl(i32 %x, i32 %y, i32 %z, i32* %p) { 132; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_extra_use_shl( 133; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 134; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]] 135; CHECK-NEXT: store i32 [[XOR]], i32* [[P:%.*]], align 4 136; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 137; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 138; CHECK-NEXT: ret i1 [[R]] 139; 140 %shl = shl i32 2147483648, %y 141 %xor = xor i32 %shl, %z ; extra use of shl 142 store i32 %xor, i32* %p 143 %and = and i32 %shl, %x 144 %r = icmp eq i32 %and, 0 145 ret i1 %r 146} 147 148; Not fold 149define i1 @scalar_i32_signbit_shl_and_eq_extra_use_and(i32 %x, i32 %y, i32 %z, i32* %p) { 150; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_extra_use_and( 151; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 152; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 153; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AND]], [[Z:%.*]] 154; CHECK-NEXT: store i32 [[MUL]], i32* [[P:%.*]], align 4 155; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 156; CHECK-NEXT: ret i1 [[R]] 157; 158 %shl = shl i32 2147483648, %y 159 %and = and i32 %shl, %x 160 %mul = mul i32 %and, %z ; extra use of and 161 store i32 %mul, i32* %p 162 %r = icmp eq i32 %and, 0 163 ret i1 %r 164} 165 166; Not fold 167define i1 @scalar_i32_signbit_shl_and_eq_extra_use_shl_and(i32 %x, i32 %y, i32 %z, i32* %p, i32* %q) { 168; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_extra_use_shl_and( 169; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 170; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 171; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4 172; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[Z:%.*]] 173; CHECK-NEXT: store i32 [[ADD]], i32* [[Q:%.*]], align 4 174; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 175; CHECK-NEXT: ret i1 [[R]] 176; 177 %shl = shl i32 2147483648, %y 178 %and = and i32 %shl, %x 179 store i32 %and, i32* %p ; extra use of and 180 %add = add i32 %shl, %z ; extra use of shl 181 store i32 %add, i32* %q 182 %r = icmp eq i32 %and, 0 183 ret i1 %r 184} 185 186; X is constant 187 188define i1 @scalar_i32_signbit_shl_and_eq_X_is_constant1(i32 %y) { 189; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_X_is_constant1( 190; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 191; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], 12345 192; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 193; CHECK-NEXT: ret i1 [[R]] 194; 195 %shl = shl i32 2147483648, %y 196 %and = and i32 %shl, 12345 197 %r = icmp eq i32 %and, 0 198 ret i1 %r 199} 200 201define i1 @scalar_i32_signbit_shl_and_eq_X_is_constant2(i32 %y) { 202; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_X_is_constant2( 203; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 204; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], 1 205; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 206; CHECK-NEXT: ret i1 [[R]] 207; 208 %shl = shl i32 2147483648, %y 209 %and = and i32 %shl, 1 210 %r = icmp eq i32 %and, 0 211 ret i1 %r 212} 213 214; Negative tests 215 216; Check 'slt' predicate 217 218define i1 @scalar_i32_signbit_shl_and_slt(i32 %x, i32 %y) { 219; CHECK-LABEL: @scalar_i32_signbit_shl_and_slt( 220; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 221; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 222; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[AND]], 0 223; CHECK-NEXT: ret i1 [[R]] 224; 225 %shl = shl i32 2147483648, %y 226 %and = and i32 %shl, %x 227 %r = icmp slt i32 %and, 0 228 ret i1 %r 229} 230 231; Compare with nonzero 232 233define i1 @scalar_i32_signbit_shl_and_eq_nonzero(i32 %x, i32 %y) { 234; CHECK-LABEL: @scalar_i32_signbit_shl_and_eq_nonzero( 235; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] 236; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] 237; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 1 238; CHECK-NEXT: ret i1 [[R]] 239; 240 %shl = shl i32 2147483648, %y 241 %and = and i32 %shl, %x 242 %r = icmp eq i32 %and, 1 ; should be comparing with 0 243 ret i1 %r 244} 245