1; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=x86_64-unknown-linux -S 2>&1 | FileCheck %s 2; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=x86_64-unknown-linux -mattr=+avx512f -S 2>&1 | FileCheck %s --check-prefix=AVX512F 3; REQUIRES: asserts 4 5@a = global [1024 x i8] zeroinitializer, align 16 6@b = global [1024 x i8] zeroinitializer, align 16 7 8define i32 @foo() { 9; This function has a loop of SAD pattern. Here we check when VF = 16 the 10; register usage doesn't exceed 16. 11; 12; CHECK-LABEL: foo 13; CHECK: LV(REG): VF = 8 14; CHECK-NEXT: LV(REG): Found max usage: 2 item 15; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers 16; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 7 registers 17; CHECK-NEXT: LV(REG): Found invariant usage: 0 item 18; CHECK: LV(REG): VF = 16 19; CHECK-NEXT: LV(REG): Found max usage: 2 item 20; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers 21; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 13 registers 22; CHECK-NEXT: LV(REG): Found invariant usage: 0 item 23 24entry: 25 br label %for.body 26 27for.cond.cleanup: 28 %add.lcssa = phi i32 [ %add, %for.body ] 29 ret i32 %add.lcssa 30 31for.body: 32 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 33 %s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ] 34 %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @a, i64 0, i64 %indvars.iv 35 %0 = load i8, i8* %arrayidx, align 1 36 %conv = zext i8 %0 to i32 37 %arrayidx2 = getelementptr inbounds [1024 x i8], [1024 x i8]* @b, i64 0, i64 %indvars.iv 38 %1 = load i8, i8* %arrayidx2, align 1 39 %conv3 = zext i8 %1 to i32 40 %sub = sub nsw i32 %conv, %conv3 41 %ispos = icmp sgt i32 %sub, -1 42 %neg = sub nsw i32 0, %sub 43 %2 = select i1 %ispos, i32 %sub, i32 %neg 44 %add = add nsw i32 %2, %s.015 45 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 46 %exitcond = icmp eq i64 %indvars.iv.next, 1024 47 br i1 %exitcond, label %for.cond.cleanup, label %for.body 48} 49 50define i32 @goo() { 51; For indvars.iv used in a computating chain only feeding into getelementptr or cmp, 52; it will not have vector version and the vector register usage will not exceed the 53; available vector register number. 54; CHECK-LABEL: goo 55; CHECK: LV(REG): VF = 8 56; CHECK-NEXT: LV(REG): Found max usage: 2 item 57; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers 58; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 7 registers 59; CHECK-NEXT: LV(REG): Found invariant usage: 0 item 60; CHECK: LV(REG): VF = 16 61; CHECK-NEXT: LV(REG): Found max usage: 2 item 62; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers 63; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 13 registers 64; CHECK-NEXT: LV(REG): Found invariant usage: 0 item 65entry: 66 br label %for.body 67 68for.cond.cleanup: ; preds = %for.body 69 %add.lcssa = phi i32 [ %add, %for.body ] 70 ret i32 %add.lcssa 71 72for.body: ; preds = %for.body, %entry 73 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 74 %s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ] 75 %tmp1 = add nsw i64 %indvars.iv, 3 76 %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @a, i64 0, i64 %tmp1 77 %tmp = load i8, i8* %arrayidx, align 1 78 %conv = zext i8 %tmp to i32 79 %tmp2 = add nsw i64 %indvars.iv, 2 80 %arrayidx2 = getelementptr inbounds [1024 x i8], [1024 x i8]* @b, i64 0, i64 %tmp2 81 %tmp3 = load i8, i8* %arrayidx2, align 1 82 %conv3 = zext i8 %tmp3 to i32 83 %sub = sub nsw i32 %conv, %conv3 84 %ispos = icmp sgt i32 %sub, -1 85 %neg = sub nsw i32 0, %sub 86 %tmp4 = select i1 %ispos, i32 %sub, i32 %neg 87 %add = add nsw i32 %tmp4, %s.015 88 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 89 %exitcond = icmp eq i64 %indvars.iv.next, 1024 90 br i1 %exitcond, label %for.cond.cleanup, label %for.body 91} 92 93define i64 @bar(i64* nocapture %a) { 94; CHECK-LABEL: bar 95; CHECK: LV(REG): VF = 2 96; CHECK-NEXT: LV(REG): Found max usage: 2 item 97; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 3 registers 98; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers 99; CHECK-NEXT: LV(REG): Found invariant usage: 0 item 100 101entry: 102 br label %for.body 103 104for.cond.cleanup: 105 %add2.lcssa = phi i64 [ %add2, %for.body ] 106 ret i64 %add2.lcssa 107 108for.body: 109 %i.012 = phi i64 [ 0, %entry ], [ %inc, %for.body ] 110 %s.011 = phi i64 [ 0, %entry ], [ %add2, %for.body ] 111 %arrayidx = getelementptr inbounds i64, i64* %a, i64 %i.012 112 %0 = load i64, i64* %arrayidx, align 8 113 %add = add nsw i64 %0, %i.012 114 store i64 %add, i64* %arrayidx, align 8 115 %add2 = add nsw i64 %add, %s.011 116 %inc = add nuw nsw i64 %i.012, 1 117 %exitcond = icmp eq i64 %inc, 1024 118 br i1 %exitcond, label %for.cond.cleanup, label %for.body 119} 120 121@d = external global [0 x i64], align 8 122@e = external global [0 x i32], align 4 123@c = external global [0 x i32], align 4 124 125define void @hoo(i32 %n) { 126; For c[i] = e[d[i]] in the loop, e[d[i]] is not consecutive but its index %tmp can 127; be gathered into a vector. For VF == 16, the vector version of %tmp will be <16 x i64> 128; so the max usage of AVX512 vector register will be 2. 129; AVX512F-LABEL: bar 130; AVX512F: LV(REG): VF = 16 131; AVX512F-CHECK: LV(REG): Found max usage: 2 item 132; AVX512F-CHECK: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers 133; AVX512F-CHECK: LV(REG): RegisterClass: Generic::VectorRC, 2 registers 134; AVX512F-CHECK: LV(REG): Found invariant usage: 0 item 135 136entry: 137 br label %for.body 138 139for.body: ; preds = %for.body, %entry 140 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 141 %arrayidx = getelementptr inbounds [0 x i64], [0 x i64]* @d, i64 0, i64 %indvars.iv 142 %tmp = load i64, i64* %arrayidx, align 8 143 %arrayidx1 = getelementptr inbounds [0 x i32], [0 x i32]* @e, i64 0, i64 %tmp 144 %tmp1 = load i32, i32* %arrayidx1, align 4 145 %arrayidx3 = getelementptr inbounds [0 x i32], [0 x i32]* @c, i64 0, i64 %indvars.iv 146 store i32 %tmp1, i32* %arrayidx3, align 4 147 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 148 %exitcond = icmp eq i64 %indvars.iv.next, 10000 149 br i1 %exitcond, label %for.end, label %for.body 150 151for.end: ; preds = %for.body 152 ret void 153} 154