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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -O3                   -S < %s  | FileCheck %s
3; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
4
5target triple = "x86_64--"
6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
7
8; PR42174 - https://bugs.llvm.org/show_bug.cgi?id=42174
9; This test should match the IR produced by clang after running -mem2reg.
10; All math before the final 'add' should be scalarized.
11
12define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 %h, i32 %k, i32 %w, i32 %p, i32 %j, i32 %u) {
13; CHECK-LABEL: @square(
14; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[K:%.*]], 2
15; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[P:%.*]], 6234
16; CHECK-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[H:%.*]], 75
17; CHECK-NEXT:    [[DIV9:%.*]] = sdiv i32 [[J:%.*]], 3452
18; CHECK-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[W:%.*]], 53
19; CHECK-NEXT:    [[DIV17:%.*]] = sdiv i32 [[X:%.*]], 820
20; CHECK-NEXT:    [[MUL21:%.*]] = shl nsw i32 [[U:%.*]], 2
21; CHECK-NEXT:    [[DOTSCALAR:%.*]] = add i32 [[Y:%.*]], 1
22; CHECK-NEXT:    [[DOTSCALAR1:%.*]] = add i32 [[DOTSCALAR]], [[DIV17]]
23; CHECK-NEXT:    [[DOTSCALAR2:%.*]] = add i32 [[DOTSCALAR1]], [[MUL5]]
24; CHECK-NEXT:    [[DOTSCALAR3:%.*]] = add i32 [[DOTSCALAR2]], [[DIV]]
25; CHECK-NEXT:    [[DOTSCALAR4:%.*]] = add i32 [[DOTSCALAR3]], [[MUL13]]
26; CHECK-NEXT:    [[DOTSCALAR5:%.*]] = add i32 [[DOTSCALAR4]], [[MUL]]
27; CHECK-NEXT:    [[DOTSCALAR6:%.*]] = add i32 [[DOTSCALAR5]], [[DIV9]]
28; CHECK-NEXT:    [[DOTSCALAR7:%.*]] = add i32 [[DOTSCALAR6]], [[MUL21]]
29; CHECK-NEXT:    [[DOTSCALAR8:%.*]] = add i32 [[DOTSCALAR7]], 317425
30; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> undef, i32 [[DOTSCALAR8]], i64 0
31; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
32; CHECK-NEXT:    [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]
33; CHECK-NEXT:    ret <4 x i32> [[ADD29]]
34;
35  %add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1>
36  %div = sdiv i32 %k, 2
37  %splatinsert = insertelement <4 x i32> undef, i32 %div, i32 0
38  %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
39  %add1 = add <4 x i32> %add, %splat
40  %mul = mul nsw i32 %p, 6234
41  %splatinsert2 = insertelement <4 x i32> undef, i32 %mul, i32 0
42  %splat3 = shufflevector <4 x i32> %splatinsert2, <4 x i32> undef, <4 x i32> zeroinitializer
43  %add4 = add <4 x i32> %add1, %splat3
44  %mul5 = mul nsw i32 75, %h
45  %splatinsert6 = insertelement <4 x i32> undef, i32 %mul5, i32 0
46  %splat7 = shufflevector <4 x i32> %splatinsert6, <4 x i32> undef, <4 x i32> zeroinitializer
47  %add8 = add <4 x i32> %add4, %splat7
48  %div9 = sdiv i32 %j, 3452
49  %splatinsert10 = insertelement <4 x i32> undef, i32 %div9, i32 0
50  %splat11 = shufflevector <4 x i32> %splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer
51  %add12 = add <4 x i32> %add8, %splat11
52  %mul13 = mul nsw i32 53, %w
53  %splatinsert14 = insertelement <4 x i32> undef, i32 %mul13, i32 0
54  %splat15 = shufflevector <4 x i32> %splatinsert14, <4 x i32> undef, <4 x i32> zeroinitializer
55  %add16 = add <4 x i32> %add12, %splat15
56  %div17 = sdiv i32 %x, 820
57  %splatinsert18 = insertelement <4 x i32> undef, i32 %div17, i32 0
58  %splat19 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer
59  %add20 = add <4 x i32> %add16, %splat19
60  %mul21 = mul nsw i32 4, %u
61  %splatinsert22 = insertelement <4 x i32> undef, i32 %mul21, i32 0
62  %splat23 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer
63  %add24 = add <4 x i32> %add20, %splat23
64  %splatinsert25 = insertelement <4 x i32> undef, i32 %y, i32 0
65  %splat26 = shufflevector <4 x i32> %splatinsert25, <4 x i32> undef, <4 x i32> zeroinitializer
66  %add27 = add <4 x i32> %add24, %splat26
67  %add28 = add <4 x i32> %add27, <i32 25, i32 25, i32 25, i32 25>
68  %add29 = add <4 x i32> %add28, <i32 317400, i32 317400, i32 317400, i32 317400>
69  ret <4 x i32> %add29
70}
71
72