1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s 3 4define <4 x i32> @sign_extend_v_v(<4 x i16> %lhs) { 5; CHECK-LABEL: @sign_extend_v_v( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[TMP0:%.*]] = sext <4 x i16> [[LHS:%.*]] to <4 x i32> 8; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 9; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> undef, i32 [[TMP1]], i32 0 10; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 11; CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[TMP2]], i32 1 12; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 13; CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <4 x i32> [[VECINIT3]], i32 [[TMP3]], i32 2 14; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 15; CHECK-NEXT: [[VECINIT9:%.*]] = insertelement <4 x i32> [[VECINIT6]], i32 [[TMP4]], i32 3 16; CHECK-NEXT: ret <4 x i32> [[VECINIT9]] 17; 18entry: 19 %vecext = extractelement <4 x i16> %lhs, i32 0 20 %conv = sext i16 %vecext to i32 21 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 22 %vecext1 = extractelement <4 x i16> %lhs, i32 1 23 %conv2 = sext i16 %vecext1 to i32 24 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 25 %vecext4 = extractelement <4 x i16> %lhs, i32 2 26 %conv5 = sext i16 %vecext4 to i32 27 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 28 %vecext7 = extractelement <4 x i16> %lhs, i32 3 29 %conv8 = sext i16 %vecext7 to i32 30 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 31 ret <4 x i32> %vecinit9 32} 33 34define <4 x i16> @truncate_v_v(<4 x i32> %lhs) { 35; CHECK-LABEL: @truncate_v_v( 36; CHECK-NEXT: entry: 37; CHECK-NEXT: [[TMP0:%.*]] = trunc <4 x i32> [[LHS:%.*]] to <4 x i16> 38; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[TMP0]], i32 0 39; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i16> undef, i16 [[TMP1]], i32 0 40; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[TMP0]], i32 1 41; CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x i16> [[VECINIT]], i16 [[TMP2]], i32 1 42; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i16> [[TMP0]], i32 2 43; CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <4 x i16> [[VECINIT3]], i16 [[TMP3]], i32 2 44; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP0]], i32 3 45; CHECK-NEXT: [[VECINIT9:%.*]] = insertelement <4 x i16> [[VECINIT6]], i16 [[TMP4]], i32 3 46; CHECK-NEXT: ret <4 x i16> [[VECINIT9]] 47; 48entry: 49 %vecext = extractelement <4 x i32> %lhs, i32 0 50 %conv = trunc i32 %vecext to i16 51 %vecinit = insertelement <4 x i16> undef, i16 %conv, i32 0 52 %vecext1 = extractelement <4 x i32> %lhs, i32 1 53 %conv2 = trunc i32 %vecext1 to i16 54 %vecinit3 = insertelement <4 x i16> %vecinit, i16 %conv2, i32 1 55 %vecext4 = extractelement <4 x i32> %lhs, i32 2 56 %conv5 = trunc i32 %vecext4 to i16 57 %vecinit6 = insertelement <4 x i16> %vecinit3, i16 %conv5, i32 2 58 %vecext7 = extractelement <4 x i32> %lhs, i32 3 59 %conv8 = trunc i32 %vecext7 to i16 60 %vecinit9 = insertelement <4 x i16> %vecinit6, i16 %conv8, i32 3 61 ret <4 x i16> %vecinit9 62} 63