1; RUN: opt -lowerswitch -S < %s | FileCheck %s 2 3; Test that we don't crash and have a different basic block for each incoming edge. 4define void @test0(i32 %mode) { 5; CHECK-LABEL: @test0 6; 7; CHECK: icmp eq i32 %mode, 4 8; CHECK-NEXT: label %BB3, label %NewDefault 9; 10; CHECK: icmp eq i32 %mode, 2 11; CHECK-NEXT: label %BB3, label %NewDefault 12; 13; CHECK: icmp eq i32 %mode, 0 14; CHECK-NEXT: label %BB3, label %NewDefault 15; 16; CHECK: %merge = phi i64 [ 1, %BB3 ], [ 0, %NewDefault ] 17BB1: 18 switch i32 %mode, label %BB2 [ 19 i32 3, label %BB2 20 i32 5, label %BB2 21 i32 0, label %BB3 22 i32 2, label %BB3 23 i32 4, label %BB3 24 ] 25 26BB2: 27 %merge = phi i64 [ 1, %BB3 ], [ 0, %BB1 ], [ 0, %BB1 ], [ 0, %BB1 ] 28 ret void 29 30BB3: 31 br label %BB2 32} 33 34; Test switch cases that are merged into a single case during lowerswitch 35; (take 84 and 85 below) - check that the number of incoming phi values match 36; the number of branches. 37define void @test1(i32 %mode) { 38; CHECK-LABEL: @test1 39entry: 40 br label %bb1 41 42bb1: 43 switch i32 %mode, label %bb1 [ 44 i32 84, label %bb3 45 i32 85, label %bb3 46 i32 86, label %bb2 47 i32 78, label %exit 48 i32 99, label %bb3 49 ] 50 51bb2: 52 br label %bb3 53 54bb3: 55; CHECK-LABEL: bb3 56; CHECK: %tmp = phi i32 [ 1, %NodeBlock ], [ 0, %bb2 ], [ 1, %LeafBlock3 ] 57 %tmp = phi i32 [ 1, %bb1 ], [ 0, %bb2 ], [ 1, %bb1 ], [ 1, %bb1 ] 58; CHECK-NEXT: %tmp2 = phi i32 [ 2, %NodeBlock ], [ 5, %bb2 ], [ 2, %LeafBlock3 ] 59 %tmp2 = phi i32 [ 2, %bb1 ], [ 2, %bb1 ], [ 5, %bb2 ], [ 2, %bb1 ] 60 br label %exit 61 62exit: 63 ret void 64} 65 66; Test that we don't crash. 67define void @test2(i32 %mode) { 68; CHECK-LABEL: @test2 69 br i1 undef, label %1, label %._crit_edge 70 71; <label>:1 ; preds = %0 72 switch i32 %mode, label %33 [ 73 i32 2, label %2 74 i32 3, label %3 75 i32 4, label %4 76 i32 5, label %5 77 i32 6, label %6 78 i32 7, label %7 79 i32 8, label %8 80 i32 9, label %9 81 i32 10, label %10 82 i32 11, label %14 83 i32 12, label %18 84 i32 13, label %22 85 i32 14, label %26 86 i32 15, label %27 87 i32 16, label %34 88 i32 17, label %34 89 i32 18, label %34 90 i32 19, label %34 91 i32 22, label %34 92 i32 20, label %31 93 i32 21, label %32 94 ] 95 96; <label>:2 ; preds = %1 97 br label %34 98 99; <label>:3 ; preds = %1 100 br label %34 101 102; <label>:4 ; preds = %1 103 br label %34 104 105; <label>:5 ; preds = %1 106 br label %34 107 108; <label>:6 ; preds = %1 109 br label %34 110 111; <label>:7 ; preds = %1 112 br label %34 113 114; <label>:8 ; preds = %1 115 br label %34 116 117; <label>:9 ; preds = %1 118 br label %34 119 120; <label>:10 ; preds = %1 121 br i1 undef, label %11, label %12 122 123; <label>:11 ; preds = %10 124 br label %13 125 126; <label>:12 ; preds = %10 127 br label %13 128 129; <label>:13 ; preds = %12, %11 130 br label %34 131 132; <label>:14 ; preds = %1 133 br i1 undef, label %15, label %16 134 135; <label>:15 ; preds = %14 136 br label %17 137 138; <label>:16 ; preds = %14 139 br label %17 140 141; <label>:17 ; preds = %16, %15 142 br label %34 143 144; <label>:18 ; preds = %1 145 br i1 undef, label %19, label %20 146 147; <label>:19 ; preds = %18 148 br label %21 149 150; <label>:20 ; preds = %18 151 br label %21 152 153; <label>:21 ; preds = %20, %19 154 br label %34 155 156; <label>:22 ; preds = %1 157 br i1 undef, label %23, label %24 158 159; <label>:23 ; preds = %22 160 br label %25 161 162; <label>:24 ; preds = %22 163 br label %25 164 165; <label>:25 ; preds = %24, %23 166 br label %34 167 168; <label>:26 ; preds = %1 169 br label %34 170 171; <label>:27 ; preds = %1 172 br i1 undef, label %28, label %29 173 174; <label>:28 ; preds = %27 175 br label %30 176 177; <label>:29 ; preds = %27 178 br label %30 179 180; <label>:30 ; preds = %29, %28 181 br label %34 182 183; <label>:31 ; preds = %1 184 br label %34 185 186; <label>:32 ; preds = %1 187 br label %34 188 189; <label>:33 ; preds = %1 190 br label %34 191 192; <label>:34 ; preds = %33, %32, %31, %30, %26, %25, %21, %17, %13, %9, %8, %7, %6, %5, %4, %3, %2, %1, %1, %1, %1, %1 193 %o.0 = phi float [ undef, %33 ], [ undef, %32 ], [ undef, %31 ], [ undef, %30 ], [ undef, %26 ], [ undef, %25 ], [ undef, %21 ], [ undef, %17 ], [ undef, %13 ], [ undef, %9 ], [ undef, %8 ], [ undef, %7 ], [ undef, %6 ], [ undef, %5 ], [ undef, %4 ], [ undef, %3 ], [ undef, %2 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ], [ undef, %1 ] 194 br label %._crit_edge 195 196._crit_edge: ; preds = %34, %0 197 ret void 198} 199 200; Test that the PHI node in for.cond should have one entry for each predecessor 201; of its parent basic block after lowerswitch merged several cases into a new 202; default block. 203define void @test3(i32 %mode) { 204; CHECK-LABEL: @test3 205entry: 206 br label %lbl1 207 208lbl1: ; preds = %cleanup, %entry 209 br label %lbl2 210 211lbl2: ; preds = %cleanup, %lbl1 212 br label %for.cond 213 214for.cond: ; preds = %cleanup, %cleanup, %lbl2 215; CHECK: for.cond: 216; CHECK: phi i16 [ undef, %lbl2 ], [ %b.3, %NewDefault ]{{$}} 217; CHECK: for.cond1: 218 %b.2 = phi i16 [ undef, %lbl2 ], [ %b.3, %cleanup ], [ %b.3, %cleanup ] 219 br label %for.cond1 220 221for.cond1: ; preds = %for.inc, %for.cond 222 %b.3 = phi i16 [ %b.2, %for.cond ], [ undef, %for.inc ] 223 %tobool = icmp ne i16 %b.3, 0 224 br i1 %tobool, label %for.body, label %for.end 225 226for.body: ; preds = %for.cond1 227 br i1 undef, label %if.then, label %for.inc 228 229if.then: ; preds = %for.body 230 br label %cleanup 231 232for.inc: ; preds = %for.body 233 br label %for.cond1 234 235for.end: ; preds = %for.cond1 236 br i1 undef, label %if.then4, label %for.body7 237 238if.then4: ; preds = %for.end 239 br label %cleanup 240 241for.body7: ; preds = %for.end 242 br label %cleanup 243 244cleanup: ; preds = %for.body7, %if.then4, %if.then 245 switch i32 %mode, label %unreachable [ 246 i32 0, label %for.cond 247 i32 2, label %lbl1 248 i32 5, label %for.cond 249 i32 3, label %lbl2 250 ] 251 252unreachable: ; preds = %cleanup 253 unreachable 254} 255 256; Test that the PHI node in cleanup17 is removed as the switch default block is 257; not reachable. 258define void @test4(i32 %mode) { 259; CHECK-LABEL: @test4 260entry: 261 switch i32 %mode, label %cleanup17 [ 262 i32 0, label %return 263 i32 9, label %return 264 ] 265 266cleanup17: 267; CHECK: cleanup17: 268; CHECK-NOT: phi i16 [ undef, %entry ] 269; CHECK: return: 270 271 %retval.4 = phi i16 [ undef, %entry ] 272 unreachable 273 274return: 275 ret void 276} 277 278; Test that the PHI node in for.inc is updated correctly as the switch is 279; replaced with a single branch to for.inc 280define void @test5(i32 %mode) { 281; CHECK-LABEL: @test5 282entry: 283 br i1 undef, label %cleanup10, label %cleanup10.thread 284 285cleanup10.thread: 286 br label %for.inc 287 288cleanup10: 289 switch i32 %mode, label %unreachable [ 290 i32 0, label %for.inc 291 i32 4, label %for.inc 292 ] 293 294for.inc: 295; CHECK: for.inc: 296; CHECK-NEXT: phi i16 [ 0, %cleanup10.thread ], [ undef, %cleanup10 ] 297%0 = phi i16 [ undef, %cleanup10 ], [ 0, %cleanup10.thread ], [ undef, %cleanup10 ] 298 unreachable 299 300unreachable: 301 unreachable 302} 303