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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
3
4prefetch    (%rax)
5prefetchw   (%rax)
6
7# CHECK:      Instruction Info:
8# CHECK-NEXT: [1]: #uOps
9# CHECK-NEXT: [2]: Latency
10# CHECK-NEXT: [3]: RThroughput
11# CHECK-NEXT: [4]: MayLoad
12# CHECK-NEXT: [5]: MayStore
13# CHECK-NEXT: [6]: HasSideEffects (U)
14
15# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
16# CHECK-NEXT:  1      5     0.50    *      *            prefetch	(%rax)
17# CHECK-NEXT:  1      5     0.50    *      *            prefetchw	(%rax)
18
19# CHECK:      Resources:
20# CHECK-NEXT: [0]   - SBDivider
21# CHECK-NEXT: [1]   - SBFPDivider
22# CHECK-NEXT: [2]   - SBPort0
23# CHECK-NEXT: [3]   - SBPort1
24# CHECK-NEXT: [4]   - SBPort4
25# CHECK-NEXT: [5]   - SBPort5
26# CHECK-NEXT: [6.0] - SBPort23
27# CHECK-NEXT: [6.1] - SBPort23
28
29# CHECK:      Resource pressure per iteration:
30# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
31# CHECK-NEXT:  -      -      -      -      -      -     1.00   1.00
32
33# CHECK:      Resource pressure by instruction:
34# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
35# CHECK-NEXT:  -      -      -      -      -      -     0.50   0.50   prefetch	(%rax)
36# CHECK-NEXT:  -      -      -      -      -      -     0.50   0.50   prefetchw	(%rax)
37