1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -instruction-tables < %s | FileCheck %s 3 4lzcntw %cx, %cx 5lzcntw (%rax), %cx 6 7lzcntl %eax, %ecx 8lzcntl (%rax), %ecx 9 10lzcntq %rax, %rcx 11lzcntq (%rax), %rcx 12 13# CHECK: Instruction Info: 14# CHECK-NEXT: [1]: #uOps 15# CHECK-NEXT: [2]: Latency 16# CHECK-NEXT: [3]: RThroughput 17# CHECK-NEXT: [4]: MayLoad 18# CHECK-NEXT: [5]: MayStore 19# CHECK-NEXT: [6]: HasSideEffects (U) 20 21# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 22# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx 23# CHECK-NEXT: 2 8 1.00 * lzcntw (%rax), %cx 24# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx 25# CHECK-NEXT: 2 8 1.00 * lzcntl (%rax), %ecx 26# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx 27# CHECK-NEXT: 2 8 1.00 * lzcntq (%rax), %rcx 28 29# CHECK: Resources: 30# CHECK-NEXT: [0] - HWDivider 31# CHECK-NEXT: [1] - HWFPDivider 32# CHECK-NEXT: [2] - HWPort0 33# CHECK-NEXT: [3] - HWPort1 34# CHECK-NEXT: [4] - HWPort2 35# CHECK-NEXT: [5] - HWPort3 36# CHECK-NEXT: [6] - HWPort4 37# CHECK-NEXT: [7] - HWPort5 38# CHECK-NEXT: [8] - HWPort6 39# CHECK-NEXT: [9] - HWPort7 40 41# CHECK: Resource pressure per iteration: 42# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 43# CHECK-NEXT: - - - 6.00 1.50 1.50 - - - - 44 45# CHECK: Resource pressure by instruction: 46# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: 47# CHECK-NEXT: - - - 1.00 - - - - - - lzcntw %cx, %cx 48# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - lzcntw (%rax), %cx 49# CHECK-NEXT: - - - 1.00 - - - - - - lzcntl %eax, %ecx 50# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - lzcntl (%rax), %ecx 51# CHECK-NEXT: - - - 1.00 - - - - - - lzcntq %rax, %rcx 52# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - lzcntq (%rax), %rcx 53