1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULLREPORT 3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=true < %s | FileCheck %s -check-prefixes=ALL,FULLREPORT 4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats=false < %s | FileCheck %s -check-prefix=ALL 5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s -check-prefix=ALL 6 7add %eax, %eax 8 9# ALL: Iterations: 100 10# ALL-NEXT: Instructions: 100 11# ALL-NEXT: Total Cycles: 103 12# ALL-NEXT: Total uOps: 100 13 14# ALL: Dispatch Width: 2 15# ALL-NEXT: uOps Per Cycle: 0.97 16# ALL-NEXT: IPC: 0.97 17# ALL-NEXT: Block RThroughput: 0.5 18 19# ALL: Instruction Info: 20# ALL-NEXT: [1]: #uOps 21# ALL-NEXT: [2]: Latency 22# ALL-NEXT: [3]: RThroughput 23# ALL-NEXT: [4]: MayLoad 24# ALL-NEXT: [5]: MayStore 25# ALL-NEXT: [6]: HasSideEffects (U) 26 27# ALL: [1] [2] [3] [4] [5] [6] Instructions: 28# ALL-NEXT: 1 1 0.50 addl %eax, %eax 29 30# FULLREPORT: Dynamic Dispatch Stall Cycles: 31# FULLREPORT-NEXT: RAT - Register unavailable: 0 32# FULLREPORT-NEXT: RCU - Retire tokens unavailable: 0 33# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) 34# FULLREPORT-NEXT: LQ - Load queue full: 0 35# FULLREPORT-NEXT: SQ - Store queue full: 0 36# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0 37 38# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 39# FULLREPORT-NEXT: [# dispatched], [# cycles] 40# FULLREPORT-NEXT: 0, 22 (21.4%) 41# FULLREPORT-NEXT: 1, 62 (60.2%) 42# FULLREPORT-NEXT: 2, 19 (18.4%) 43 44# FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued: 45# FULLREPORT-NEXT: [# issued], [# cycles] 46# FULLREPORT-NEXT: 0, 3 (2.9%) 47# FULLREPORT-NEXT: 1, 100 (97.1%) 48 49# FULLREPORT: Scheduler's queue usage: 50# FULLREPORT-NEXT: [1] Resource name. 51# FULLREPORT-NEXT: [2] Average number of used buffer entries. 52# FULLREPORT-NEXT: [3] Maximum number of used buffer entries. 53# FULLREPORT-NEXT: [4] Total number of buffer entries. 54 55# FULLREPORT: [1] [2] [3] [4] 56# FULLREPORT-NEXT: JALU01 15 20 20 57# FULLREPORT-NEXT: JFPU01 0 0 18 58# FULLREPORT-NEXT: JLSAGU 0 0 12 59 60# FULLREPORT: Retire Control Unit - number of cycles where we saw N instructions retired: 61# FULLREPORT-NEXT: [# retired], [# cycles] 62# FULLREPORT-NEXT: 0, 3 (2.9%) 63# FULLREPORT-NEXT: 1, 100 (97.1%) 64 65# FULLREPORT: Total ROB Entries: 64 66# FULLREPORT-NEXT: Max Used ROB Entries: 22 ( 34.4% ) 67# FULLREPORT-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% ) 68 69# FULLREPORT: Register File statistics: 70# FULLREPORT-NEXT: Total number of mappings created: 200 71# FULLREPORT-NEXT: Max number of mappings used: 44 72 73# FULLREPORT: * Register File #1 -- JFpuPRF: 74# FULLREPORT-NEXT: Number of physical registers: 72 75# FULLREPORT-NEXT: Total number of mappings created: 0 76# FULLREPORT-NEXT: Max number of mappings used: 0 77 78# FULLREPORT: * Register File #2 -- JIntegerPRF: 79# FULLREPORT-NEXT: Number of physical registers: 64 80# FULLREPORT-NEXT: Total number of mappings created: 200 81# FULLREPORT-NEXT: Max number of mappings used: 44 82 83# ALL: Resources: 84# ALL-NEXT: [0] - JALU0 85# ALL-NEXT: [1] - JALU1 86# ALL-NEXT: [2] - JDiv 87# ALL-NEXT: [3] - JFPA 88# ALL-NEXT: [4] - JFPM 89# ALL-NEXT: [5] - JFPU0 90# ALL-NEXT: [6] - JFPU1 91# ALL-NEXT: [7] - JLAGU 92# ALL-NEXT: [8] - JMul 93# ALL-NEXT: [9] - JSAGU 94# ALL-NEXT: [10] - JSTC 95# ALL-NEXT: [11] - JVALU0 96# ALL-NEXT: [12] - JVALU1 97# ALL-NEXT: [13] - JVIMUL 98 99# ALL: Resource pressure per iteration: 100# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] 101# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - 102 103# ALL: Resource pressure by instruction: 104# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: 105# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax 106