1// RUN: mlir-opt %s -test-conv-vectorization="tile-sizes=1,3" --cse | FileCheck %s 2 3// CHECK-DAG: #[[$map0:.*]] = affine_map<(d0)[s0] -> (1, -d0 + s0)> 4// CHECK-DAG: #[[$map1:.*]] = affine_map<(d0)[s0] -> (d0 + s0)> 5// CHECK-DAG: #[[$map2:.*]] = affine_map<(d0, d1) -> (d0 + d1)> 6// CHECK-DAG: #[[$map3:.*]] = affine_map<(d0, d1)[s0] -> (3, -d0 - d1 + s0)> 7// CHECK-DAG: #[[$map4:.*]] = affine_map<(d0)[s0] -> (3, -d0 + s0)> 8 9func @conv_1d(%arg0: memref<?xf32>, %arg1: memref<?xf32>, %arg2: memref<?xf32>) { 10 linalg.conv_1d ins(%arg0, %arg1 : memref<?xf32>, memref<?xf32>) 11 outs(%arg2 : memref<?xf32>) 12 return 13} 14 15// CHECK-LABEL: @conv_1d 16// CHECK-SAME: %[[arg0:[a-zA-Z0-9]+]]: memref<?xf32> 17// CHECK-SAME: %[[arg1:[a-zA-Z0-9]+]]: memref<?xf32> 18// CHECK-SAME: %[[arg2:[a-zA-Z0-9]+]]: memref<?xf32 19// CHECK-DAG: %[[c12:.*]] = constant 12 : index 20// CHECK-DAG: %[[c4:.*]] = constant 4 : index 21// CHECK-DAG: %[[cst:.*]] = constant 0.000000e+00 : f32 22// CHECK-DAG: %[[c3:.*]] = constant 3 : index 23// CHECK-DAG: %[[c0:.*]] = constant 0 : index 24// CHECK-DAG: %[[c1:.*]] = constant 1 : index 25// CHECK: %[[v0:.*]] = dim %[[arg1]], %[[c0]] : memref<?xf32> 26// CHECK: %[[v1:.*]] = dim %[[arg2]], %[[c0]] : memref<?xf32> 27// CHECK: %[[v2:.*]] = dim %[[arg0]], %[[c0]] : memref<?xf32> 28// CHECK: %[[v3:.*]] = alloc(%[[c12]]) : memref<?xi8> 29// CHECK: %[[v4:.*]] = alloc(%[[c12]]) : memref<?xi8> 30// CHECK: %[[v5:.*]] = alloc(%[[c4]]) : memref<?xi8> 31// CHECK: %[[v6:.*]] = std.view %[[v3]][%[[c0]]][] : memref<?xi8> to memref<3xf32> 32// CHECK: %[[v7:.*]] = std.view %[[v4]][%[[c0]]][] : memref<?xi8> to memref<3xf32> 33// CHECK: %[[v8:.*]] = std.view %[[v5]][%[[c0]]][] : memref<?xi8> to memref<1xf32> 34// CHECK: scf.for %[[arg3:.*]] = %[[c0]] to %[[v1]] step %[[c1]] { 35// CHECK: %[[v9:.*]] = affine.min #[[$map0]](%[[arg3]])[%[[v1]]] 36// CHECK: %[[v10:.*]] = subview %[[arg2]][%[[arg3]]] [%[[v9]]] [1] : memref<?xf32> to memref<?xf32, #[[$map1]]> 37// CHECK: %[[v11:.*]] = subview %[[v8]][0] [%[[v9]]] [1] : memref<1xf32> to memref<?xf32> 38// CHECK: scf.for %[[arg4:.*]] = %[[c0]] to %[[v0]] step %[[c3]] { 39// CHECK: %[[v12:.*]] = affine.apply #[[$map2]](%[[arg3]], %[[arg4]]) 40// CHECK: %[[v13:.*]] = affine.min #[[$map3]](%[[arg3]], %[[arg4]])[%[[v2]]] 41// CHECK: %[[v14:.*]] = subview %arg0[%12] [%13] [1] : memref<?xf32> to memref<?xf32, #[[$map1]]> 42// CHECK: %[[v15:.*]] = affine.min #[[$map4]](%arg4)[%0] 43// CHECK: %[[v16:.*]] = subview %[[arg1]][%[[arg4]]] [%[[v15]]] [1] : memref<?xf32> to memref<?xf32, #[[$map1]]> 44// CHECK: %[[v17:.*]] = subview %[[v6]][0] [%[[v13]]] [1] : memref<3xf32> to memref<?xf32> 45// CHECK: %[[v19:.*]] = vector.transfer_read %[[v6]][%[[c0]]], %[[cst]] {masked = [false]} : memref<3xf32>, vector<3xf32> 46// CHECK: %[[v20:.*]] = vector.transfer_read %[[v7]][%[[c0]]], %[[cst]] {masked = [false]} : memref<3xf32>, vector<3xf32> 47// CHECK: %[[v21:.*]] = mulf %[[v19]], %[[v20]] : vector<3xf32> 48// CHECK: %[[v22:.*]] = vector.reduction "add", %[[v21]], %[[cst]] : vector<3xf32> into f32 49// CHECK: store %[[v22]], %[[v8]][%[[c0]]] : memref<1xf32> 50// CHECK: scf.for %[[arg5:.*]] = %[[c0]] to %[[v9]] step %[[c1]] { 51// CHECK: %[[v23:.*]] = load %[[v11]][%[[arg5]]] : memref<?xf32> 52// CHECK: store %[[v23]], %[[v10]][%[[arg5]]] : memref<?xf32, #[[$map1]]> 53