1{ 2 "context" : "[arg] -> { : -9223372036854775808 <= arg <= 9223372036854775807 }", 3 "name" : "%loop1---%exit", 4 "statements" : [ 5 { 6 "accesses" : [ 7 { 8 "kind" : "write", 9 "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[1 + i0] }" 10 } 11 ], 12 "domain" : "[arg] -> { Stmt_loop1[i0] : 0 <= i0 <= -2 + arg }", 13 "name" : "Stmt_loop1", 14 "schedule" : "[arg] -> { Stmt_loop1[i0] -> [0, i0] }" 15 }, 16 { 17 "accesses" : [ 18 { 19 "kind" : "read", 20 "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_A[1 + i0] }" 21 }, 22 { 23 "kind" : "write", 24 "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_val[] }" 25 } 26 ], 27 "domain" : "[arg] -> { Stmt_loop2[i0] : 0 <= i0 <= -2 + arg }", 28 "name" : "Stmt_loop2", 29 "schedule" : "[arg] -> { Stmt_loop2[i0] -> [1, i0] }" 30 }, 31 { 32 "accesses" : [ 33 { 34 "kind" : "write", 35 "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[1 + i0] }" 36 }, 37 { 38 "kind" : "read", 39 "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }" 40 } 41 ], 42 "domain" : "[arg] -> { Stmt_loop3[i0] : 0 <= i0 <= -2 + arg }", 43 "name" : "Stmt_loop3", 44 "schedule" : "[arg] -> { Stmt_loop3[i0] -> [2, i0] }" 45 } 46 ] 47} 48