1; RUN: opt %loadPolly -polly-vectorizer=polly -polly-opt-isl -polly-codegen -S < %s | FileCheck %s 2; 3; Polly crashed during codegen with an assertion error while trying to generate 4; a pointer bitcast from a pointer having an address space to one without 5; 6; CHECK-LABEL: entry: 7; CHECK: load <4 x float>, <4 x float> addrspace(4)* 8; 9; ModuleID = '/tmp/lud.bc' 10source_filename = "lud.c" 11; This datalayout was for a 32-bit ARC processor with 512-bit vector extension 12target datalayout = "e-m:e-p:32:32-p1:32:32-p3:32:32-p5:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-v256:32-v512:32-n8:16:32" 13; Specify x86 because the ARC backend is still experimental and not built by default 14target triple = "x86_64-unknown-unknown" 15 16; Function Attrs: noinline nounwind 17define void @LU_decomp_kij_opt(i32 %n, i32 %lda, float addrspace(4)* %A, float addrspace(4)* %scratch) #0 { 18entry: 19 %cmp34 = icmp sgt i32 %n, 0 20 br i1 %cmp34, label %for.body.lr.ph, label %for.end34 21 22for.body.lr.ph: ; preds = %entry 23 %0 = add nsw i32 %n, -1 24 br label %for.body 25 26for.body: ; preds = %for.inc32, %for.body.lr.ph 27 %k.035 = phi i32 [ 0, %for.body.lr.ph ], [ %add2, %for.inc32 ] 28 %mul = mul nsw i32 %k.035, %lda 29 %add = add nsw i32 %mul, %k.035 30 %arrayidx = getelementptr inbounds float, float addrspace(4)* %A, i32 %add 31 %1 = load float, float addrspace(4)* %arrayidx, align 4 32 %conv1 = fdiv arcp float 1.000000e+00, %1 33 %add2 = add nuw nsw i32 %k.035, 1 34 %exitcond37 = icmp eq i32 %k.035, %0 35 br i1 %exitcond37, label %for.end34, label %for.body6.lr.ph 36 37for.body6.lr.ph: ; preds = %for.body 38 br label %for.body6 39 40for.body6: ; preds = %for.inc29, %for.body6.lr.ph 41 %i.033 = phi i32 [ %add2, %for.body6.lr.ph ], [ %inc30, %for.inc29 ] 42 %mul7 = mul nsw i32 %i.033, %lda 43 %add8 = add nsw i32 %mul7, %k.035 44 %arrayidx9 = getelementptr inbounds float, float addrspace(4)* %A, i32 %add8 45 %2 = load float, float addrspace(4)* %arrayidx9, align 4 46 %mul10 = fmul arcp contract float %conv1, %2 47 store float %mul10, float addrspace(4)* %arrayidx9, align 4 48 br label %for.body18 49 50for.body18: ; preds = %for.body18, %for.body6 51 %j.031 = phi i32 [ %add2, %for.body6 ], [ %inc, %for.body18 ] 52 %3 = load float, float addrspace(4)* %arrayidx9, align 4 53 %add23 = add nsw i32 %j.031, %mul 54 %arrayidx24 = getelementptr inbounds float, float addrspace(4)* %A, i32 %add23 55 %4 = load float, float addrspace(4)* %arrayidx24, align 4 56 %mul25 = fmul arcp contract float %3, %4 57 %add27 = add nsw i32 %j.031, %mul7 58 %arrayidx28 = getelementptr inbounds float, float addrspace(4)* %A, i32 %add27 59 %5 = load float, float addrspace(4)* %arrayidx28, align 4 60 %sub = fsub arcp contract float %5, %mul25 61 store float %sub, float addrspace(4)* %arrayidx28, align 4 62 %inc = add nuw nsw i32 %j.031, 1 63 %exitcond = icmp eq i32 %inc, %n 64 br i1 %exitcond, label %for.inc29, label %for.body18 65 66for.inc29: ; preds = %for.body18 67 %inc30 = add nuw nsw i32 %i.033, 1 68 %exitcond36 = icmp eq i32 %inc30, %n 69 br i1 %exitcond36, label %for.inc32, label %for.body6 70 71for.inc32: ; preds = %for.inc29 72 br label %for.body 73 74for.end34: ; preds = %for.body, %entry 75 ret void 76} 77 78attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" } 79 80!llvm.module.flags = !{!0, !1} 81!llvm.ident = !{!2} 82 83!0 = !{i32 1, !"ArcIntrinsicCheck", i32 18224056} 84!1 = !{i32 1, !"wchar_size", i32 2} 85!2 = !{!"clang version 10.0.1 "} 86