1//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// Define TII for use in SchedVariant Predicates. 11// const MachineInstr *MI and const TargetSchedModel *SchedModel 12// are defined by default. 13def : PredicateProlog<[{ 14 const AArch64InstrInfo *TII = 15 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo()); 16 (void)TII; 17}]>; 18 19// AArch64 Scheduler Definitions 20 21def WriteImm : SchedWrite; // MOVN, MOVZ 22// TODO: Provide variants for MOV32/64imm Pseudos that dynamically 23// select the correct sequence of WriteImms. 24 25def WriteI : SchedWrite; // ALU 26def WriteISReg : SchedWrite; // ALU of Shifted-Reg 27def WriteIEReg : SchedWrite; // ALU of Extended-Reg 28def ReadI : SchedRead; // ALU 29def ReadISReg : SchedRead; // ALU of Shifted-Reg 30def ReadIEReg : SchedRead; // ALU of Extended-Reg 31def WriteExtr : SchedWrite; // EXTR shifts a reg pair 32def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair 33def WriteIS : SchedWrite; // Shift/Scale 34def WriteID32 : SchedWrite; // 32-bit Divide 35def WriteID64 : SchedWrite; // 64-bit Divide 36def ReadID : SchedRead; // 32/64-bit Divide 37def WriteIM32 : SchedWrite; // 32-bit Multiply 38def WriteIM64 : SchedWrite; // 64-bit Multiply 39def ReadIM : SchedRead; // 32/64-bit Multiply 40def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate 41def WriteBr : SchedWrite; // Branch 42def WriteBrReg : SchedWrite; // Indirect Branch 43 44def WriteLD : SchedWrite; // Load from base addr plus immediate offset 45def WriteST : SchedWrite; // Store to base addr plus immediate offset 46def WriteSTP : SchedWrite; // Store a register pair. 47def WriteAdr : SchedWrite; // Address pre/post increment. 48 49def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). 50def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). 51def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. 52 53// Predicate for determining when a shiftable register is shifted. 54def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>; 55 56// Predicate for determining when a extendedable register is extended. 57def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>; 58 59// ScaledIdxPred is true if a WriteLDIdx operand will be 60// scaled. Subtargets can use this to dynamically select resources and 61// latency for WriteLDIdx and ReadAdrBase. 62def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(*MI)}]>; 63 64// Serialized two-level address load. 65// EXAMPLE: LOADGot 66def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; 67 68// Serialized two-level address lookup. 69// EXAMPLE: MOVaddr... 70def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>; 71 72// The second register of a load-pair. 73// LDP,LDPSW,LDNP,LDXP,LDAXP 74def WriteLDHi : SchedWrite; 75 76// Store-exclusive is a store followed by a dependent load. 77def WriteSTX : WriteSequence<[WriteST, WriteLD]>; 78 79def WriteSys : SchedWrite; // Long, variable latency system ops. 80def WriteBarrier : SchedWrite; // Memory barrier. 81def WriteHint : SchedWrite; // Hint instruction. 82 83def WriteF : SchedWrite; // General floating-point ops. 84def WriteFCmp : SchedWrite; // Floating-point compare. 85def WriteFCvt : SchedWrite; // Float conversion. 86def WriteFCopy : SchedWrite; // Float-int register copy. 87def WriteFImm : SchedWrite; // Floating-point immediate. 88def WriteFMul : SchedWrite; // Floating-point multiply. 89def WriteFDiv : SchedWrite; // Floating-point division. 90 91def WriteV : SchedWrite; // Vector ops. 92def WriteVLD : SchedWrite; // Vector loads. 93def WriteVST : SchedWrite; // Vector stores. 94 95def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP) 96 97// Read the unwritten lanes of the VLD's destination registers. 98def ReadVLD : SchedRead; 99 100// Sequential vector load and shuffle. 101def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>; 102def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>; 103 104// Store a shuffled vector. 105def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>; 106def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>; 107