1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <cstdlib>
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "ppc-subtarget"
31
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
35
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
38
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
41 cl::Hidden);
42
initializeSubtargetDependencies(StringRef CPU,StringRef FS)43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
44 StringRef FS) {
45 initializeEnvironment();
46 initSubtargetFeatures(CPU, FS);
47 return *this;
48 }
49
PPCSubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const PPCTargetMachine & TM)50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51 const std::string &FS, const PPCTargetMachine &TM)
52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54 TargetTriple.getArch() == Triple::ppc64le),
55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56 InstrInfo(*this), TLInfo(TM, *this) {}
57
initializeEnvironment()58 void PPCSubtarget::initializeEnvironment() {
59 StackAlignment = 16;
60 DarwinDirective = PPC::DIR_NONE;
61 HasMFOCRF = false;
62 Has64BitSupport = false;
63 Use64BitRegs = false;
64 UseCRBits = false;
65 UseSoftFloat = false;
66 HasAltivec = false;
67 HasSPE = false;
68 HasQPX = false;
69 HasVSX = false;
70 HasP8Vector = false;
71 HasP8Altivec = false;
72 HasP8Crypto = false;
73 HasP9Vector = false;
74 HasP9Altivec = false;
75 HasFCPSGN = false;
76 HasFSQRT = false;
77 HasFRE = false;
78 HasFRES = false;
79 HasFRSQRTE = false;
80 HasFRSQRTES = false;
81 HasRecipPrec = false;
82 HasSTFIWX = false;
83 HasLFIWAX = false;
84 HasFPRND = false;
85 HasFPCVT = false;
86 HasISEL = false;
87 HasBPERMD = false;
88 HasExtDiv = false;
89 HasCMPB = false;
90 HasLDBRX = false;
91 IsBookE = false;
92 HasOnlyMSYNC = false;
93 IsPPC4xx = false;
94 IsPPC6xx = false;
95 IsE500 = false;
96 FeatureMFTB = false;
97 DeprecatedDST = false;
98 HasLazyResolverStubs = false;
99 HasICBT = false;
100 HasInvariantFunctionDescriptors = false;
101 HasPartwordAtomics = false;
102 HasDirectMove = false;
103 IsQPXStackUnaligned = false;
104 HasHTM = false;
105 HasFusion = false;
106 HasFloat128 = false;
107 IsISA3_0 = false;
108
109 HasPOPCNTD = POPCNTD_Unavailable;
110 }
111
initSubtargetFeatures(StringRef CPU,StringRef FS)112 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
113 // Determine default and user specified characteristics
114 std::string CPUName = CPU;
115 if (CPUName.empty() || CPU == "generic") {
116 // If cross-compiling with -march=ppc64le without -mcpu
117 if (TargetTriple.getArch() == Triple::ppc64le)
118 CPUName = "ppc64le";
119 else
120 CPUName = "generic";
121 }
122
123 // Initialize scheduling itinerary for the specified CPU.
124 InstrItins = getInstrItineraryForCPU(CPUName);
125
126 // Parse features string.
127 ParseSubtargetFeatures(CPUName, FS);
128
129 // If the user requested use of 64-bit regs, but the cpu selected doesn't
130 // support it, ignore.
131 if (IsPPC64 && has64BitSupport())
132 Use64BitRegs = true;
133
134 // Set up darwin-specific properties.
135 if (isDarwin())
136 HasLazyResolverStubs = true;
137
138 // QPX requires a 32-byte aligned stack. Note that we need to do this if
139 // we're compiling for a BG/Q system regardless of whether or not QPX
140 // is enabled because external functions will assume this alignment.
141 IsQPXStackUnaligned = QPXStackUnaligned;
142 StackAlignment = getPlatformStackAlignment();
143
144 // Determine endianness.
145 // FIXME: Part of the TargetMachine.
146 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
147 }
148
149 /// Return true if accesses to the specified global have to go through a dyld
150 /// lazy resolution stub. This means that an extra load is required to get the
151 /// address of the global.
hasLazyResolverStub(const GlobalValue * GV) const152 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
153 if (!HasLazyResolverStubs)
154 return false;
155 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
156 return true;
157 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
158 // the section that is being relocated. This means we have to use o load even
159 // for GVs that are known to be local to the dso.
160 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
161 return true;
162 return false;
163 }
164
165 // Embedded cores need aggressive scheduling (and some others also benefit).
needsAggressiveScheduling(unsigned Directive)166 static bool needsAggressiveScheduling(unsigned Directive) {
167 switch (Directive) {
168 default: return false;
169 case PPC::DIR_440:
170 case PPC::DIR_A2:
171 case PPC::DIR_E500mc:
172 case PPC::DIR_E5500:
173 case PPC::DIR_PWR7:
174 case PPC::DIR_PWR8:
175 // FIXME: Same as P8 until POWER9 scheduling info is available
176 case PPC::DIR_PWR9:
177 return true;
178 }
179 }
180
enableMachineScheduler() const181 bool PPCSubtarget::enableMachineScheduler() const {
182 // Enable MI scheduling for the embedded cores.
183 // FIXME: Enable this for all cores (some additional modeling
184 // may be necessary).
185 return needsAggressiveScheduling(DarwinDirective);
186 }
187
188 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
enablePostRAScheduler() const189 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
190
getAntiDepBreakMode() const191 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
192 return TargetSubtargetInfo::ANTIDEP_ALL;
193 }
194
getCriticalPathRCs(RegClassVector & CriticalPathRCs) const195 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
196 CriticalPathRCs.clear();
197 CriticalPathRCs.push_back(isPPC64() ?
198 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
199 }
200
overrideSchedPolicy(MachineSchedPolicy & Policy,unsigned NumRegionInstrs) const201 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
202 unsigned NumRegionInstrs) const {
203 if (needsAggressiveScheduling(DarwinDirective)) {
204 Policy.OnlyTopDown = false;
205 Policy.OnlyBottomUp = false;
206 }
207
208 // Spilling is generally expensive on all PPC cores, so always enable
209 // register-pressure tracking.
210 Policy.ShouldTrackPressure = true;
211 }
212
useAA() const213 bool PPCSubtarget::useAA() const {
214 // Use AA during code generation for the embedded cores.
215 return needsAggressiveScheduling(DarwinDirective);
216 }
217
enableSubRegLiveness() const218 bool PPCSubtarget::enableSubRegLiveness() const {
219 return UseSubRegLiveness;
220 }
221
classifyGlobalReference(const GlobalValue * GV) const222 unsigned char PPCSubtarget::classifyGlobalReference(
223 const GlobalValue *GV) const {
224 // Note that currently we don't generate non-pic references.
225 // If a caller wants that, this will have to be updated.
226
227 // Large code model always uses the TOC even for local symbols.
228 if (TM.getCodeModel() == CodeModel::Large)
229 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
230
231 unsigned char flags = PPCII::MO_PIC_FLAG;
232
233 // Only if the relocation mode is PIC do we have to worry about
234 // interposition. In all other cases we can use a slightly looser standard to
235 // decide how to access the symbol.
236 if (TM.getRelocationModel() == Reloc::PIC_) {
237 // If it's local, or it's non-default, it can't be interposed.
238 if (!GV->hasLocalLinkage() &&
239 GV->hasDefaultVisibility()) {
240 flags |= PPCII::MO_NLP_FLAG;
241 }
242 return flags;
243 }
244
245 if (GV->isStrongDefinitionForLinker())
246 return flags;
247 return flags | PPCII::MO_NLP_FLAG;
248 }
249
isELFv2ABI() const250 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
isPPC64() const251 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
252