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1//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MPX instruction set, defining the
11// instructions, and properties of the instructions which are needed for code
12// generation, machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
17  def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
18              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
19              Requires<[HasMPX, Not64BitMode]>;
20  def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
21              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
22              Requires<[HasMPX, In64BitMode]>;
23}
24
25defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
26
27multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
28  def 32rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, i32mem:$src2),
29              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
30              Requires<[HasMPX, Not64BitMode]>;
31  def 64rm: RI<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, i64mem:$src2),
32              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
33              Requires<[HasMPX, In64BitMode]>;
34  def 32rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR32:$src2),
35              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
36              Requires<[HasMPX, Not64BitMode]>;
37  def 64rr: RI<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR64:$src2),
38              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
39              Requires<[HasMPX, In64BitMode]>;
40}
41defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS;
42defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD;
43defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD;
44
45def BNDMOVRMrr   : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
46                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
47                    Requires<[HasMPX]>;
48def BNDMOVRM32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
49                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
50                    Requires<[HasMPX, Not64BitMode]>;
51def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
52                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
53                    Requires<[HasMPX, In64BitMode]>;
54
55def BNDMOVMRrr   : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
56                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
57                    Requires<[HasMPX]>;
58def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
59                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
60                    Requires<[HasMPX, Not64BitMode]>;
61def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
62                    "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
63                    Requires<[HasMPX, In64BitMode]>;
64
65def BNDSTXmr:      I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
66                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
67                    Requires<[HasMPX]>;
68def BNDLDXrm:      I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
69                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
70                    Requires<[HasMPX]>;
71