1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s 2 3; Test invalid shift values. This will fall-back to SDAG. 4; AND 5define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) { 6; CHECK-LABEL: and_rs_i8 7; CHECK: and [[REG:w[0-9]+]], w0, w8 8; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff 9 %1 = shl i8 %b, 8 10 %2 = and i8 %a, %1 11 ret i8 %2 12} 13 14define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) { 15; CHECK-LABEL: and_rs_i16 16; CHECK: and [[REG:w[0-9]+]], w0, w8 17; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff 18 %1 = shl i16 %b, 16 19 %2 = and i16 %a, %1 20 ret i16 %2 21} 22 23define i32 @and_rs_i32(i32 %a, i32 %b) { 24; CHECK-LABEL: and_rs_i32 25; CHECK: and w0, w0, w8 26 %1 = shl i32 %b, 32 27 %2 = and i32 %a, %1 28 ret i32 %2 29} 30 31define i64 @and_rs_i64(i64 %a, i64 %b) { 32; CHECK-LABEL: and_rs_i64 33; CHECK: and x0, x0, x8 34 %1 = shl i64 %b, 64 35 %2 = and i64 %a, %1 36 ret i64 %2 37} 38 39; OR 40define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) { 41; CHECK-LABEL: or_rs_i8 42; CHECK: orr [[REG:w[0-9]+]], w0, w8 43; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff 44 %1 = shl i8 %b, 8 45 %2 = or i8 %a, %1 46 ret i8 %2 47} 48 49define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) { 50; CHECK-LABEL: or_rs_i16 51; CHECK: orr [[REG:w[0-9]+]], w0, w8 52; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff 53 %1 = shl i16 %b, 16 54 %2 = or i16 %a, %1 55 ret i16 %2 56} 57 58define i32 @or_rs_i32(i32 %a, i32 %b) { 59; CHECK-LABEL: or_rs_i32 60; CHECK: orr w0, w0, w8 61 %1 = shl i32 %b, 32 62 %2 = or i32 %a, %1 63 ret i32 %2 64} 65 66define i64 @or_rs_i64(i64 %a, i64 %b) { 67; CHECK-LABEL: or_rs_i64 68; CHECK: orr x0, x0, x8 69 %1 = shl i64 %b, 64 70 %2 = or i64 %a, %1 71 ret i64 %2 72} 73 74; XOR 75define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) { 76; CHECK-LABEL: xor_rs_i8 77; CHECK: eor [[REG:w[0-9]+]], w0, w8 78; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff 79 %1 = shl i8 %b, 8 80 %2 = xor i8 %a, %1 81 ret i8 %2 82} 83 84define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) { 85; CHECK-LABEL: xor_rs_i16 86; CHECK: eor [[REG:w[0-9]+]], w0, w8 87; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff 88 %1 = shl i16 %b, 16 89 %2 = xor i16 %a, %1 90 ret i16 %2 91} 92 93define i32 @xor_rs_i32(i32 %a, i32 %b) { 94; CHECK-LABEL: xor_rs_i32 95; CHECK: eor w0, w0, w8 96 %1 = shl i32 %b, 32 97 %2 = xor i32 %a, %1 98 ret i32 %2 99} 100 101define i64 @xor_rs_i64(i64 %a, i64 %b) { 102; CHECK-LABEL: xor_rs_i64 103; CHECK: eor x0, x0, x8 104 %1 = shl i64 %b, 64 105 %2 = xor i64 %a, %1 106 ret i64 %2 107} 108 109;ADD 110define i32 @add_rs_i32(i32 %a, i32 %b) { 111; CHECK-LABEL: add_rs_i32 112; CHECK: add w0, w0, w8 113 %1 = shl i32 %b, 32 114 %2 = add i32 %a, %1 115 ret i32 %2 116} 117 118define i64 @add_rs_i64(i64 %a, i64 %b) { 119; CHECK-LABEL: add_rs_i64 120; CHECK: add x0, x0, x8 121 %1 = shl i64 %b, 64 122 %2 = add i64 %a, %1 123 ret i64 %2 124} 125 126