1; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 2; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 3; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 4 5; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports 6; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always 7; using two shifts. 8 9; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions 10; and therefore must set flags. {{s?}} below denotes this, instead of 11; duplicating tests. 12 13; zext 14 15define i8 @zext_1_8(i1 %a) nounwind ssp { 16; v7-LABEL: zext_1_8: 17; v7: and r0, r0, #1 18 %r = zext i1 %a to i8 19 ret i8 %r 20} 21 22define i16 @zext_1_16(i1 %a) nounwind ssp { 23; v7-LABEL: zext_1_16: 24; v7: and r0, r0, #1 25 %r = zext i1 %a to i16 26 ret i16 %r 27} 28 29define i32 @zext_1_32(i1 %a) nounwind ssp { 30; v7-LABEL: zext_1_32: 31; v7: and r0, r0, #1 32 %r = zext i1 %a to i32 33 ret i32 %r 34} 35 36define i16 @zext_8_16(i8 %a) nounwind ssp { 37; v7-LABEL: zext_8_16: 38; v7: and r0, r0, #255 39 %r = zext i8 %a to i16 40 ret i16 %r 41} 42 43define i32 @zext_8_32(i8 %a) nounwind ssp { 44; v7-LABEL: zext_8_32: 45; v7: and r0, r0, #255 46 %r = zext i8 %a to i32 47 ret i32 %r 48} 49 50define i32 @zext_16_32(i16 %a) nounwind ssp { 51; v7-LABEL: zext_16_32: 52; v7: uxth r0, r0 53 %r = zext i16 %a to i32 54 ret i32 %r 55} 56 57; sext 58 59define i8 @sext_1_8(i1 %a) nounwind ssp { 60; v7-LABEL: sext_1_8: 61; v7: lsl{{s?}} r0, r0, #31 62; v7: asr{{s?}} r0, r0, #31 63 %r = sext i1 %a to i8 64 ret i8 %r 65} 66 67define i16 @sext_1_16(i1 %a) nounwind ssp { 68; v7-LABEL: sext_1_16: 69; v7: lsl{{s?}} r0, r0, #31 70; v7: asr{{s?}} r0, r0, #31 71 %r = sext i1 %a to i16 72 ret i16 %r 73} 74 75define i32 @sext_1_32(i1 %a) nounwind ssp { 76; v7-LABEL: sext_1_32: 77; v7: lsl{{s?}} r0, r0, #31 78; v7: asr{{s?}} r0, r0, #31 79 %r = sext i1 %a to i32 80 ret i32 %r 81} 82 83define i16 @sext_8_16(i8 %a) nounwind ssp { 84; v7-LABEL: sext_8_16: 85; v7: sxtb r0, r0 86 %r = sext i8 %a to i16 87 ret i16 %r 88} 89 90define i32 @sext_8_32(i8 %a) nounwind ssp { 91; v7-LABEL: sext_8_32: 92; v7: sxtb r0, r0 93 %r = sext i8 %a to i32 94 ret i32 %r 95} 96 97define i32 @sext_16_32(i16 %a) nounwind ssp { 98; v7-LABEL: sext_16_32: 99; v7: sxth r0, r0 100 %r = sext i16 %a to i32 101 ret i32 %r 102} 103