1; REQUIRES: asserts 2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s 3 4; This test makes sure spills of 64-bit pairs in Thumb mode actually 5; generate thumb instructions. Previously we were inserting an ARM 6; STMIA which happened to have the same encoding. 7 8define void @foo(i64* %addr) { 9 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 10 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 11 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 12 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 15 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) 16 17 ; Make sure we are actually creating the Thumb versions of the spill 18 ; instructions. 19; CHECK: t2STRDi8 20; CHECK: t2LDRDi8 21 22 store volatile i64 %val1, i64* %addr 23 store volatile i64 %val2, i64* %addr 24 store volatile i64 %val3, i64* %addr 25 store volatile i64 %val4, i64* %addr 26 store volatile i64 %val5, i64* %addr 27 store volatile i64 %val6, i64* %addr 28 store volatile i64 %val7, i64* %addr 29 ret void 30} 31