1; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s 2; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s 3 4@ub1 = common global i8 0, align 1 5@ub2 = common global i8 0, align 1 6@ub3 = common global i8 0, align 1 7@uc1 = common global i8 0, align 1 8@uc2 = common global i8 0, align 1 9@uc3 = common global i8 0, align 1 10@us1 = common global i16 0, align 2 11@us2 = common global i16 0, align 2 12@us3 = common global i16 0, align 2 13@ub = common global i8 0, align 1 14@uc = common global i8 0, align 1 15@us = common global i16 0, align 2 16@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 17@ui = common global i32 0, align 4 18@ui1 = common global i32 0, align 4 19@ui2 = common global i32 0, align 4 20@ui3 = common global i32 0, align 4 21 22; Function Attrs: noinline nounwind 23define void @andUb() #0 { 24entry: 25 %0 = load i8, i8* @ub1, align 1 26 %1 = load i8, i8* @ub2, align 1 27 %conv0 = trunc i8 %0 to i1 28 %conv1 = trunc i8 %1 to i1 29 %and0 = and i1 %conv1, %conv0 30 %conv3 = zext i1 %and0 to i8 31 store i8 %conv3, i8* @ub, align 1, !tbaa !2 32; CHECK-LABEL: .ent andUb 33; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 34; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 35; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 36; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 37; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) 38; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 39; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 40; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 41; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] 42; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 43; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 44 ret void 45} 46 47; Function Attrs: noinline nounwind 48define void @andUb0() #0 { 49entry: 50 %0 = load i8, i8* @ub1, align 1, !tbaa !2 51 %conv = trunc i8 %0 to i1 52 %and = and i1 %conv, 0 53 %conv1 = zext i1 %and to i8 54 store i8 %conv1, i8* @ub, align 1, !tbaa !2 55; CHECK-LABEL: .ent andUb0 56; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 57; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 58; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 59; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 60; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 61; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 62; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero 63; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 64; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 65; CHECK: .end andUb0 66 ret void 67} 68 69; Function Attrs: noinline nounwind 70define void @andUb1() #0 { 71; clang uses i8 constants for booleans, so we test with an i8 1. 72entry: 73 %x = load i8, i8* @ub1, align 1, !tbaa !2 74 %and = and i8 %x, 1 75 %conv = trunc i8 %and to i1 76 %conv1 = zext i1 %conv to i8 77 store i8 %conv1, i8* @ub, align 1, !tbaa !2 78; CHECK-LABEL: .ent andUb1 79; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 80; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 81; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 82; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 83; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 84; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 85; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 86; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] 87; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 88; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 89; CHECK: .end andUb1 90 ret void 91} 92 93; Function Attrs: noinline nounwind 94define void @orUb() #0 { 95entry: 96 %0 = load i8, i8* @ub1, align 1 97 %1 = load i8, i8* @ub2, align 1 98 %conv0 = trunc i8 %0 to i1 99 %conv1 = trunc i8 %1 to i1 100 %or0 = or i1 %conv1, %conv0 101 %conv3 = zext i1 %or0 to i8 102 store i8 %conv3, i8* @ub, align 1, !tbaa !2 103; CHECK-LABEL: .ent orUb 104; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 105; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 106; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 107; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 108; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) 109; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 110; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 111; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 112; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] 113; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 114; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 115 ret void 116} 117 118; Function Attrs: noinline nounwind 119define void @orUb0() #0 { 120entry: 121 %0 = load i8, i8* @ub1, align 1, !tbaa !2 122 %conv = trunc i8 %0 to i1 123 %or = or i1 %conv, 0 124 %conv1 = zext i1 %or to i8 125 store i8 %conv1, i8* @ub, align 1, !tbaa !2 126; CHECK-LABEL: .ent orUb0 127; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 128; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 129; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 130; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 131; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 132; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 133; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 134; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 135; CHECK: .end orUb0 136 ret void 137} 138 139; Function Attrs: noinline nounwind 140define void @orUb1() #0 { 141entry: 142 %x = load i8, i8* @ub1, align 1, !tbaa !2 143 %or = or i8 %x, 1 144 %conv = trunc i8 %or to i1 145 %conv1 = zext i1 %conv to i8 146 store i8 %conv1, i8* @ub, align 1, !tbaa !2 147; CHECK-LABEL: .ent orUb1 148; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 149; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 150; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 151; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 152; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 153; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 154; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 155; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] 156; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 157; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 158; CHECK: .end orUb1 159 ret void 160} 161 162; Function Attrs: noinline nounwind 163define void @xorUb() #0 { 164entry: 165 %0 = load i8, i8* @ub1, align 1 166 %1 = load i8, i8* @ub2, align 1 167 %conv0 = trunc i8 %0 to i1 168 %conv1 = trunc i8 %1 to i1 169 %xor0 = xor i1 %conv1, %conv0 170 %conv3 = zext i1 %xor0 to i8 171 store i8 %conv3, i8* @ub, align 1, !tbaa !2 172; CHECK-LABEL: .ent xorUb 173; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 174; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 175; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 176; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 177; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) 178; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 179; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 180; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 181; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] 182; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 183; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 184 ret void 185} 186 187; Function Attrs: noinline nounwind 188define void @xorUb0() #0 { 189entry: 190 %0 = load i8, i8* @ub1, align 1, !tbaa !2 191 %conv = trunc i8 %0 to i1 192 %xor = xor i1 %conv, 0 193 %conv1 = zext i1 %xor to i8 194 store i8 %conv1, i8* @ub, align 1, !tbaa !2 195; CHECK-LABEL: .ent xorUb0 196; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 197; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 198; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 199; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 200; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 201; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 202; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero 203; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 204; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 205; CHECK: .end xorUb0 206 ret void 207} 208 209; Function Attrs: noinline nounwind 210define void @xorUb1() #0 { 211entry: 212 %x = load i8, i8* @ub1, align 1, !tbaa !2 213 %xor = xor i8 1, %x 214 %conv = trunc i8 %xor to i1 215 %conv1 = zext i1 %conv to i8 216 store i8 %conv1, i8* @ub, align 1, !tbaa !2 217; CHECK-LABEL: .ent xorUb1 218; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 219; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 220; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 221; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) 222; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 223; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) 224; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 225; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] 226; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 227; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 228; CHECK: .end xorUb1 229 ret void 230} 231 232; Function Attrs: noinline nounwind 233define void @andUc() #0 { 234entry: 235 %0 = load i8, i8* @uc1, align 1, !tbaa !2 236 %1 = load i8, i8* @uc2, align 1, !tbaa !2 237 %and3 = and i8 %1, %0 238 store i8 %and3, i8* @uc, align 1, !tbaa !2 239; CHECK-LABEL: .ent andUc 240; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 241; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 242; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 243; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 244; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) 245; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 246; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 247; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) 248; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UB1]] 249; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 250 ret void 251} 252 253; Function Attrs: noinline nounwind 254define void @andUc0() #0 { 255entry: 256 %0 = load i8, i8* @uc1, align 1, !tbaa !2 257 %and = and i8 %0, 67 258 store i8 %and, i8* @uc, align 1, !tbaa !2 259; CHECK-LABEL: .ent andUc0 260; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 261; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 262; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 263; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 264; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 265; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 266; CHECK-DAG: addiu $[[CONST_67:[0-9]+]], $zero, 67 267; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]] 268; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 269; CHECK: .end andUc0 270 ret void 271} 272 273; Function Attrs: noinline nounwind 274define void @andUc1() #0 { 275entry: 276 %0 = load i8, i8* @uc1, align 1, !tbaa !2 277 %and = and i8 %0, 167 278 store i8 %and, i8* @uc, align 1, !tbaa !2 279; CHECK-LABEL: .ent andUc1 280; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 281; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 282; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 283; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 284; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 285; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 286; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167 287; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]] 288; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 289; CHECK: .end andUc1 290 ret void 291} 292 293; Function Attrs: noinline nounwind 294define void @orUc() #0 { 295entry: 296 %0 = load i8, i8* @uc1, align 1, !tbaa !2 297 %1 = load i8, i8* @uc2, align 1, !tbaa !2 298 %or3 = or i8 %1, %0 299 store i8 %or3, i8* @uc, align 1, !tbaa !2 300; CHECK-LABEL: .ent orUc 301; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 302; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 303; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 304; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 305; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) 306; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 307; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 308; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) 309; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC2]], $[[UC1]] 310; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 311; CHECK: .end orUc 312 ret void 313} 314 315; Function Attrs: noinline nounwind 316define void @orUc0() #0 { 317entry: 318 %0 = load i8, i8* @uc1, align 1, !tbaa !2 319 %or = or i8 %0, 69 320 store i8 %or, i8* @uc, align 1, !tbaa !2 321; CHECK-LABEL: .ent orUc0 322; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 323; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 324; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 325; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 326; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 327; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 328; CHECK-DAG: addiu $[[CONST_69:[0-9]+]], $zero, 69 329; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]] 330; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 331; CHECK: .end orUc0 332 ret void 333} 334 335; Function Attrs: noinline nounwind 336define void @orUc1() #0 { 337entry: 338 %0 = load i8, i8* @uc1, align 1, !tbaa !2 339 %or = or i8 %0, 238 340 store i8 %or, i8* @uc, align 1, !tbaa !2 341; CHECK-LABEL: .ent orUc1 342; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 343; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 344; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 345; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 346; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 347; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 348; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238 349; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]] 350; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 351; CHECK: .end orUc1 352 ret void 353} 354 355; Function Attrs: noinline nounwind 356define void @xorUc() #0 { 357entry: 358 %0 = load i8, i8* @uc1, align 1, !tbaa !2 359 %1 = load i8, i8* @uc2, align 1, !tbaa !2 360 %xor3 = xor i8 %1, %0 361 store i8 %xor3, i8* @uc, align 1, !tbaa !2 362; CHECK-LABEL: .ent xorUc 363; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 364; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 365; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 366; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 367; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) 368; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 369; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 370; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) 371; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC2]], $[[UC1]] 372; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 373; CHECK: .end xorUc 374 ret void 375} 376 377; Function Attrs: noinline nounwind 378define void @xorUc0() #0 { 379entry: 380 %0 = load i8, i8* @uc1, align 1, !tbaa !2 381 %xor = xor i8 %0, 23 382 store i8 %xor, i8* @uc, align 1, !tbaa !2 383; CHECK-LABEL: .ent xorUc0 384; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 385; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 386; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 387; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 388; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 389; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 390; CHECK-DAG: addiu $[[CONST_23:[0-9]+]], $zero, 23 391; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]] 392; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 393; CHECK: .end xorUc0 394 ret void 395} 396 397; Function Attrs: noinline nounwind 398define void @xorUc1() #0 { 399entry: 400 %0 = load i8, i8* @uc1, align 1, !tbaa !2 401 %xor = xor i8 %0, 120 402 store i8 %xor, i8* @uc, align 1, !tbaa !2 403; CHECK-LABEL: .ent xorUc1 404; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 405; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 406; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 407; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) 408; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 409; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) 410; CHECK-DAG: addiu $[[CONST_120:[0-9]+]], $zero, 120 411; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]] 412; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) 413; CHECK: .end xorUc1 414 ret void 415} 416 417; Function Attrs: noinline nounwind 418define void @andUs() #0 { 419entry: 420 %0 = load i16, i16* @us1, align 2, !tbaa !5 421 %1 = load i16, i16* @us2, align 2, !tbaa !5 422 %and3 = and i16 %1, %0 423 store i16 %and3, i16* @us, align 2, !tbaa !5 424; CHECK-LABEL: .ent andUs 425; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 426; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 427; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 428; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 429; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) 430; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 431; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 432; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) 433; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[UB1]] 434; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 435; CHECK: .end andUs 436 ret void 437} 438 439; Function Attrs: noinline nounwind 440define void @andUs0() #0 { 441entry: 442 %0 = load i16, i16* @us1, align 2, !tbaa !5 443 %and = and i16 %0, 4660 444 store i16 %and, i16* @us, align 2, !tbaa !5 445; CHECK-LABEL: .ent andUs0 446; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 447; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 448; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 449; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 450; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 451; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 452; CHECK-DAG: addiu $[[CONST_4660:[0-9]+]], $zero, 4660 453; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]] 454; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 455; CHECK: .end andUs0 456 ret void 457} 458 459; Function Attrs: noinline nounwind 460define void @andUs1() #0 { 461entry: 462 %0 = load i16, i16* @us1, align 2, !tbaa !5 463 %and = and i16 %0, 61351 464 store i16 %and, i16* @us, align 2, !tbaa !5 465; CHECK-LABEL: .ent andUs1 466; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 467; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 468; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 469; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 470; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 471; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 472; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351 473; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]] 474; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 475; CHECK: .end andUs1 476 ret void 477} 478 479; Function Attrs: noinline nounwind 480define void @orUs() #0 { 481entry: 482 %0 = load i16, i16* @us1, align 2, !tbaa !5 483 %1 = load i16, i16* @us2, align 2, !tbaa !5 484 %or3 = or i16 %1, %0 485 store i16 %or3, i16* @us, align 2, !tbaa !5 486; CHECK-LABEL: .ent orUs 487; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 488; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 489; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 490; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 491; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) 492; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 493; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 494; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) 495; CHECK-DAG: or $[[RES:[0-9]+]], $[[US2]], $[[US1]] 496; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 497; CHECK: .end orUs 498 ret void 499} 500 501; Function Attrs: noinline nounwind 502define void @orUs0() #0 { 503entry: 504 %0 = load i16, i16* @us1, align 2, !tbaa !5 505 %or = or i16 %0, 17666 506 store i16 %or, i16* @us, align 2, !tbaa !5 507 ret void 508} 509 510; Function Attrs: noinline nounwind 511define void @orUs1() #0 { 512entry: 513 %0 = load i16, i16* @us1, align 2, !tbaa !5 514 %or = or i16 %0, 60945 515 store i16 %or, i16* @us, align 2, !tbaa !5 516; CHECK-LABEL: .ent orUs1 517; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 518; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 519; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 520; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 521; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 522; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 523; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945 524; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]] 525; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 526; CHECK: .end orUs1 527 ret void 528} 529 530; Function Attrs: noinline nounwind 531define void @xorUs() #0 { 532entry: 533 %0 = load i16, i16* @us1, align 2, !tbaa !5 534 %1 = load i16, i16* @us2, align 2, !tbaa !5 535 %xor3 = xor i16 %1, %0 536 store i16 %xor3, i16* @us, align 2, !tbaa !5 537; CHECK-LABEL: .ent xorUs 538; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 539; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 540; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 541; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 542; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) 543; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 544; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 545; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) 546; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US2]], $[[US1]] 547; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 548; CHECK: .end xorUs 549 ret void 550} 551 552; Function Attrs: noinline nounwind 553define void @xorUs0() #0 { 554entry: 555 %0 = load i16, i16* @us1, align 2, !tbaa !5 556 %xor = xor i16 %0, 6062 557 store i16 %xor, i16* @us, align 2, !tbaa !5 558; CHECK-LABEL: .ent xorUs0 559; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 560; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 561; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 562; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 563; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 564; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 565; CHECK-DAG: addiu $[[CONST_6062:[0-9]+]], $zero, 6062 566; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]] 567; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 568; CHECK: .end xorUs0 569 570 ret void 571} 572 573; Function Attrs: noinline nounwind 574define void @xorUs1() #0 { 575entry: 576 %0 = load i16, i16* @us1, align 2, !tbaa !5 577 %xor = xor i16 %0, 60024 578 store i16 %xor, i16* @us, align 2, !tbaa !5 579; CHECK-LABEL: .ent xorUs1 580; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) 581; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) 582; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 583; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) 584; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 585; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) 586; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024 587; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]] 588; CHECK: sh $[[RES]], 0($[[US_ADDR]]) 589; CHECK: .end xorUs1 590 ret void 591} 592 593attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 594attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 595attributes #2 = { nounwind } 596 597!llvm.module.flags = !{!0} 598!llvm.ident = !{!1} 599 600!0 = !{i32 1, !"PIC Level", i32 2} 601!1 = !{!"clang version 3.7.0 (trunk)"} 602!2 = !{!3, !3, i64 0} 603!3 = !{!"omnipotent char", !4, i64 0} 604!4 = !{!"Simple C/C++ TBAA"} 605!5 = !{!6, !6, i64 0} 606!6 = !{!"short", !3, i64 0} 607