1; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s 2; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s 3 4; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s 5; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s 6 7; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s 8; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s 9 10; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s 11; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s 12 13; Test the integer arguments for all ABI's and byte orders as specified by 14; section 5 of MD00305 (MIPS ABIs Described). 15; 16; N32/N64 are identical in this area so their checks have been combined into 17; the 'NEW' prefix (the N stands for New). 18; 19; Varargs are covered in arguments-hard-float-varargs.ll. 20 21@bytes = global [11 x i8] zeroinitializer 22@dwords = global [11 x i64] zeroinitializer 23@floats = global [11 x float] zeroinitializer 24@doubles = global [11 x double] zeroinitializer 25 26define void @align_to_arg_slots(i8 signext %a, i8 signext %b, i8 signext %c, 27 i8 signext %d, i8 signext %e, i8 signext %f, 28 i8 signext %g, i8 signext %h, i8 signext %i, 29 i8 signext %j) nounwind { 30entry: 31 %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1 32 store volatile i8 %a, i8* %0 33 %1 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 2 34 store volatile i8 %b, i8* %1 35 %2 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 3 36 store volatile i8 %c, i8* %2 37 %3 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 4 38 store volatile i8 %d, i8* %3 39 %4 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 5 40 store volatile i8 %e, i8* %4 41 %5 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 6 42 store volatile i8 %f, i8* %5 43 %6 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 7 44 store volatile i8 %g, i8* %6 45 %7 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 8 46 store volatile i8 %h, i8* %7 47 %8 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 9 48 store volatile i8 %i, i8* %8 49 %9 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 10 50 store volatile i8 %j, i8* %9 51 ret void 52} 53 54; ALL-LABEL: align_to_arg_slots: 55; We won't test the way the global address is calculated in this test. This is 56; just to get the register number for the other checks. 57; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) 58; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( 59 60; The first four arguments are the same in O32/N32/N64 61; ALL-DAG: sb $4, 1([[R1]]) 62; ALL-DAG: sb $5, 2([[R1]]) 63; ALL-DAG: sb $6, 3([[R1]]) 64; ALL-DAG: sb $7, 4([[R1]]) 65 66; N32/N64 get an extra four arguments in registers 67; O32 starts loading from the stack. The addresses start at 16 because space is 68; always reserved for the first four arguments. 69; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp) 70; O32-DAG: sb [[R3]], 5([[R1]]) 71; NEW-DAG: sb $8, 5([[R1]]) 72; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp) 73; O32-DAG: sb [[R3]], 6([[R1]]) 74; NEW-DAG: sb $9, 6([[R1]]) 75; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp) 76; O32-DAG: sb [[R3]], 7([[R1]]) 77; NEW-DAG: sb $10, 7([[R1]]) 78; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp) 79; O32-DAG: sb [[R3]], 8([[R1]]) 80; NEW-DAG: sb $11, 8([[R1]]) 81 82; O32/N32/N64 are accessing the stack at this point. 83; Unlike O32, N32/N64 do not reserve space for the arguments. 84; increase by 4 for O32 and 8 for N32/N64. 85; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp) 86; O32-DAG: sb [[R3]], 9([[R1]]) 87; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp) 88; NEW-DAG: sb [[R3]], 9([[R1]]) 89; O32-DAG: lw [[R3:\$[0-9]+]], 36($sp) 90; O32-DAG: sb [[R3]], 10([[R1]]) 91; NEW-DAG: ld [[R3:\$[0-9]+]], 8($sp) 92; NEW-DAG: sb [[R3]], 10([[R1]]) 93 94define void @slot_skipping(i8 signext %a, i64 signext %b, i8 signext %c, 95 i8 signext %d, i8 signext %e, i8 signext %f, 96 i8 signext %g, i64 signext %i, i8 signext %j) nounwind { 97entry: 98 %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1 99 store volatile i8 %a, i8* %0 100 %1 = getelementptr [11 x i64], [11 x i64]* @dwords, i32 0, i32 1 101 store volatile i64 %b, i64* %1 102 %2 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 2 103 store volatile i8 %c, i8* %2 104 %3 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 3 105 store volatile i8 %d, i8* %3 106 %4 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 4 107 store volatile i8 %e, i8* %4 108 %5 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 5 109 store volatile i8 %f, i8* %5 110 %6 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 6 111 store volatile i8 %g, i8* %6 112 %7 = getelementptr [11 x i64], [11 x i64]* @dwords, i32 0, i32 2 113 store volatile i64 %i, i64* %7 114 %8 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 7 115 store volatile i8 %j, i8* %8 116 ret void 117} 118 119; ALL-LABEL: slot_skipping: 120; We won't test the way the global address is calculated in this test. This is 121; just to get the register number for the other checks. 122; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) 123; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( 124; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) 125; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)( 126 127; The first argument is the same in O32/N32/N64. 128; ALL-DAG: sb $4, 1([[R1]]) 129 130; The second slot is insufficiently aligned for i64 on O32 so it is skipped. 131; Also, i64 occupies two slots on O32 and only one for N32/N64. 132; O32-DAG: sw $6, 8([[R2]]) 133; O32-DAG: sw $7, 12([[R2]]) 134; NEW-DAG: sd $5, 8([[R2]]) 135 136; N32/N64 get an extra four arguments in registers and still have two left from 137; the first four. 138; O32 starts loading from the stack. The addresses start at 16 because space is 139; always reserved for the first four arguments. 140; It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll 141; accept it for now. The only IR difference is that this argument has 142; anyext from i8 and align 8 on it. 143; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp) 144; O32-DAG: sb [[R3]], 2([[R1]]) 145; NEW-DAG: sb $6, 2([[R1]]) 146; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp) 147; O32-DAG: sb [[R3]], 3([[R1]]) 148; NEW-DAG: sb $7, 3([[R1]]) 149; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp) 150; O32-DAG: sb [[R3]], 4([[R1]]) 151; NEW-DAG: sb $8, 4([[R1]]) 152; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp) 153; O32-DAG: sb [[R3]], 5([[R1]]) 154; NEW-DAG: sb $9, 5([[R1]]) 155 156; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp) 157; O32-DAG: sb [[R3]], 6([[R1]]) 158; NEW-DAG: sb $10, 6([[R1]]) 159 160; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp) 161; O32-DAG: sw [[R3]], 16([[R2]]) 162; O32-DAG: lw [[R3:\$[0-9]+]], 44($sp) 163; O32-DAG: sw [[R3]], 20([[R2]]) 164; NEW-DAG: sd $11, 16([[R2]]) 165 166; O32/N32/N64 are accessing the stack at this point. 167; Unlike O32, N32/N64 do not reserve space for the arguments. 168; increase by 4 for O32 and 8 for N32/N64. 169; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp) 170; O32-DAG: sb [[R3]], 7([[R1]]) 171; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp) 172; NEW-DAG: sb [[R3]], 7([[R1]]) 173