1; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s 2; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s \ 3; RUN: -filetype=obj -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING 4 5; bnezc and beqzc have restriction that $rt != 0 6 7define i32 @f() { 8; CHECK-LABEL: f 9; CHECK-NOT: bnezc $0 10 11 %cmp = icmp eq i32 1, 1 12 br i1 %cmp, label %if.then, label %if.end 13 14 if.then: 15 ret i32 1 16 17 if.end: 18 ret i32 0 19} 20 21define i32 @f1() { 22; CHECK-LABEL: f1 23; CHECK-NOT: beqzc $0 24 25 %cmp = icmp eq i32 0, 0 26 br i1 %cmp, label %if.then, label %if.end 27 28 if.then: 29 ret i32 1 30 31 if.end: 32 ret i32 0 33} 34 35; We silently fixup cases where the register allocator or user has given us 36; an instruction with incorrect operands that is trivially acceptable. 37; beqc and bnec have the restriction that $rs < $rt. 38 39define i32 @f2(i32 %a, i32 %b) { 40; ENCODING-LABEL: f2 41; ENCODING-NOT: beqc $5, $4 42; ENCODING-NOT: bnec $5, $4 43 44 %cmp = icmp eq i32 %b, %a 45 br i1 %cmp, label %if.then, label %if.end 46 47 if.then: 48 ret i32 1 49 50 if.end: 51 ret i32 0 52} 53 54