1; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s 2; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s 3 4define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { 5entry: 6; ALL: dsllv 7 %shl = shl i64 %a0, %a1 8 ret i64 %shl 9} 10 11define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { 12entry: 13; ALL: dsrav 14 %shr = ashr i64 %a0, %a1 15 ret i64 %shr 16} 17 18define i64 @f2(i64 %a0, i64 %a1) nounwind readnone { 19entry: 20; ALL: dsrlv 21 %shr = lshr i64 %a0, %a1 22 ret i64 %shr 23} 24 25define i64 @f3(i64 %a0) nounwind readnone { 26entry: 27; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 28 %shl = shl i64 %a0, 10 29 ret i64 %shl 30} 31 32define i64 @f4(i64 %a0) nounwind readnone { 33entry: 34; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 35 %shr = ashr i64 %a0, 10 36 ret i64 %shr 37} 38 39define i64 @f5(i64 %a0) nounwind readnone { 40entry: 41; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 42 %shr = lshr i64 %a0, 10 43 ret i64 %shr 44} 45 46define i64 @f6(i64 %a0) nounwind readnone { 47entry: 48; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 49 %shl = shl i64 %a0, 40 50 ret i64 %shl 51} 52 53define i64 @f7(i64 %a0) nounwind readnone { 54entry: 55; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 56 %shr = ashr i64 %a0, 40 57 ret i64 %shr 58} 59 60define i64 @f8(i64 %a0) nounwind readnone { 61entry: 62; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 63 %shr = lshr i64 %a0, 40 64 ret i64 %shr 65} 66 67define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { 68entry: 69; CHECK-NOT: sll 70; ALL: drotrv 71 %shr = lshr i64 %a0, %a1 72 %sub = sub i64 64, %a1 73 %shl = shl i64 %a0, %sub 74 %or = or i64 %shl, %shr 75 ret i64 %or 76} 77 78define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { 79entry: 80; CHECK-NOT: sll 81; ALL: drotrv 82 %shl = shl i64 %a0, %a1 83 %sub = sub i64 64, %a1 84 %shr = lshr i64 %a0, %sub 85 %or = or i64 %shr, %shl 86 ret i64 %or 87} 88 89define i64 @f11(i64 %a0) nounwind readnone { 90entry: 91; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 92 %shr = lshr i64 %a0, 10 93 %shl = shl i64 %a0, 54 94 %or = or i64 %shr, %shl 95 ret i64 %or 96} 97 98define i64 @f12(i64 %a0) nounwind readnone { 99entry: 100; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 101 %shl = shl i64 %a0, 10 102 %shr = lshr i64 %a0, 54 103 %or = or i64 %shl, %shr 104 ret i64 %or 105} 106 107 108