1; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL 2; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB 3; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL 4; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB 5; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32R6-EL 6; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32R6-EB 7%struct.S2 = type { %struct.S1, %struct.S1 } 8%struct.S1 = type { i8, i8 } 9%struct.S4 = type { [7 x i8] } 10 11@s2 = common global %struct.S2 zeroinitializer, align 1 12@s4 = common global %struct.S4 zeroinitializer, align 1 13 14define void @bar1() nounwind { 15entry: 16; ALL-LABEL: bar1: 17 18; ALL-DAG: lw $[[R0:[0-9]+]], %got(s2)( 19 20; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 21; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 22; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[PART2]], 8 23; MIPS32-EL-DAG: or $4, $[[T0]], $[[PART1]] 24 25; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 26; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 27; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[PART1]], 8 28; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[PART2]] 29; MIPS32-EB-DAG: sll $4, $[[T1]], 16 30 31; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]]) 32 33 tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind 34 ret void 35} 36 37define void @bar2() nounwind { 38entry: 39; ALL-LABEL: bar2: 40 41; ALL-DAG: lw $[[R2:[0-9]+]], %got(s4)( 42 43; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]]) 44; MIPS32-EL-DAG: lwr $[[R1]], 0($[[R2]]) 45; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 46; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 47; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) 48; MIPS32-EL-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8 49; MIPS32-EL-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] 50; MIPS32-EL-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16 51; MIPS32-EL-DAG: or $5, $[[T4]], $[[T5]] 52 53; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]]) 54; MIPS32-EB-DAG: lwr $[[R1]], 3($[[R2]]) 55; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 56; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 57; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) 58; MIPS32-EB-DAG: sll $[[T3:[0-9]+]], $[[T0]], 8 59; MIPS32-EB-DAG: or $[[T4:[0-9]+]], $[[T3]], $[[T1]] 60; MIPS32-EB-DAG: sll $[[T5:[0-9]+]], $[[T4]], 16 61; MIPS32-EB-DAG: sll $[[T6:[0-9]+]], $[[T2]], 8 62; MIPS32-EB-DAG: or $5, $[[T5]], $[[T6]] 63 64; FIXME: We should be able to do better than this using lhu 65; MIPS32R6-EL-DAG: lw $4, 0($[[R2]]) 66; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]]) 67; MIPS32R6-EL-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]]) 68; MIPS32R6-EL-DAG: sll $[[T2:[0-9]+]], $[[T1]], 16 69; MIPS32R6-EL-DAG: or $5, $[[T0]], $[[T2]] 70 71; FIXME: We should be able to do better than this using lhu 72; MIPS32R6-EB-DAG: lw $4, 0($[[R2]]) 73; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]]) 74; MIPS32R6-EB-DAG: lbu $[[T1:[0-9]+]], 6($[[R2]]) 75; MIPS32R6-EB-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16 76; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8 77; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]] 78 79 tail call void @foo4(%struct.S4* byval @s4) nounwind 80 ret void 81} 82 83declare void @foo2(%struct.S1* byval) 84 85declare void @foo4(%struct.S4* byval) 86