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1; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
2
3define i32 @t0(i64 %x) {
4; CHECK-LABEL: t0:
5; CHECK:       # BB#0:{{.*}} %entry
6; CHECK:    movd %[[REG1:[a-z]+]], %mm0
7; CHECK-NEXT:    pshufw $238, %mm0, %mm0
8; CHECK-NEXT:    movd %mm0, %eax
9; CHECK-NEXT:    retq
10entry:
11  %0 = bitcast i64 %x to <4 x i16>
12  %1 = bitcast <4 x i16> %0 to x86_mmx
13  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
14  %3 = bitcast x86_mmx %2 to <4 x i16>
15  %4 = bitcast <4 x i16> %3 to <1 x i64>
16  %5 = extractelement <1 x i64> %4, i32 0
17  %6 = bitcast i64 %5 to <2 x i32>
18  %7 = extractelement <2 x i32> %6, i32 0
19  ret i32 %7
20}
21
22define i64 @t1(i64 %x, i32 %n) {
23; CHECK-LABEL: t1:
24; CHECK:       # BB#0:{{.*}} %entry
25; CHECK:    movd %[[REG2:[a-z]+]], %mm0
26; CHECK-NEXT:    movd %[[REG1]], %mm1
27; CHECK-NEXT:    psllq %mm0, %mm1
28; CHECK-NEXT:    movd %mm1, %rax
29; CHECK-NEXT:    retq
30entry:
31  %0 = bitcast i64 %x to x86_mmx
32  %1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
33  %2 = bitcast x86_mmx %1 to i64
34  ret i64 %2
35}
36
37define i64 @t2(i64 %x, i32 %n, i32 %w) {
38; CHECK-LABEL: t2:
39; CHECK:       # BB#0:{{.*}} %entry
40; CHECK:  movd %[[REG4:[a-z]+]], %mm0
41; CHECK-NEXT:  movd %[[REG6:[a-z0-9]+]], %mm1
42; CHECK-NEXT:  psllq %mm0, %mm1
43; CHECK-NEXT:  movd %[[REG1]], %mm0
44; CHECK-NEXT:  por %mm1, %mm0
45; CHECK-NEXT:  movd %mm0, %rax
46; CHECK-NEXT:  retq
47entry:
48  %0 = insertelement <2 x i32> undef, i32 %w, i32 0
49  %1 = insertelement <2 x i32> %0, i32 0, i32 1
50  %2 = bitcast <2 x i32> %1 to x86_mmx
51  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
52  %4 = bitcast i64 %x to x86_mmx
53  %5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
54  %6 = bitcast x86_mmx %5 to i64
55  ret i64 %6
56}
57
58define i64 @t3(<1 x i64>* %y, i32* %n) {
59; CHECK-LABEL: t3:
60; CHECK:       # BB#0:{{.*}} %entry
61; CHECK:    movq (%[[REG1]]), %mm0
62; CHECK-NEXT:    psllq (%[[REG3:[a-z]+]]), %mm0
63; CHECK-NEXT:    movd %mm0, %rax
64; CHECK-NEXT:    retq
65entry:
66  %0 = bitcast <1 x i64>* %y to x86_mmx*
67  %1 = load x86_mmx, x86_mmx* %0, align 8
68  %2 = load i32, i32* %n, align 4
69  %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
70  %4 = bitcast x86_mmx %3 to i64
71  ret i64 %4
72}
73
74declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
75declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
76declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
77
78