1; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -show-mc-encoding | FileCheck %s 2 3define i32 @test1(i32 %X, i32* %y) nounwind { 4 %tmp = load i32, i32* %y ; <i32> [#uses=1] 5 %tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1] 6 br i1 %tmp.upgrd.1, label %ReturnBlock, label %cond_true 7 8cond_true: ; preds = %0 9 ret i32 1 10 11ReturnBlock: ; preds = %0 12 ret i32 0 13; CHECK-LABEL: test1: 14; CHECK: cmpl $0, (%rsi) 15} 16 17define i32 @test2(i32 %X, i32* %y) nounwind { 18 %tmp = load i32, i32* %y ; <i32> [#uses=1] 19 %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1] 20 %tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1] 21 br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true 22 23cond_true: ; preds = %0 24 ret i32 1 25 26ReturnBlock: ; preds = %0 27 ret i32 0 28; CHECK-LABEL: test2: 29; CHECK: testl $536870911, (%rsi) 30} 31 32define i8 @test2b(i8 %X, i8* %y) nounwind { 33 %tmp = load i8, i8* %y ; <i8> [#uses=1] 34 %tmp1 = shl i8 %tmp, 3 ; <i8> [#uses=1] 35 %tmp1.upgrd.2 = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1] 36 br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true 37 38cond_true: ; preds = %0 39 ret i8 1 40 41ReturnBlock: ; preds = %0 42 ret i8 0 43; CHECK-LABEL: test2b: 44; CHECK: testb $31, (%rsi) 45} 46 47define i64 @test3(i64 %x) nounwind { 48 %t = icmp eq i64 %x, 0 49 %r = zext i1 %t to i64 50 ret i64 %r 51; CHECK-LABEL: test3: 52; CHECK: xorl %eax, %eax 53; CHECK: testq %rdi, %rdi 54; CHECK: sete %al 55; CHECK: ret 56} 57 58define i64 @test4(i64 %x) nounwind { 59 %t = icmp slt i64 %x, 1 60 %r = zext i1 %t to i64 61 ret i64 %r 62; CHECK-LABEL: test4: 63; CHECK: xorl %eax, %eax 64; CHECK: testq %rdi, %rdi 65; CHECK: setle %al 66; CHECK: ret 67} 68 69 70define i32 @test5(double %A) nounwind { 71 entry: 72 %tmp2 = fcmp ogt double %A, 1.500000e+02; <i1> [#uses=1] 73 %tmp5 = fcmp ult double %A, 7.500000e+01; <i1> [#uses=1] 74 %bothcond = or i1 %tmp2, %tmp5; <i1> [#uses=1] 75 br i1 %bothcond, label %bb8, label %bb12 76 77 bb8:; preds = %entry 78 %tmp9 = tail call i32 (...) @foo( ) nounwind ; <i32> [#uses=1] 79 ret i32 %tmp9 80 81 bb12:; preds = %entry 82 ret i32 32 83; CHECK-LABEL: test5: 84; CHECK: ucomisd LCPI5_0(%rip), %xmm0 85; CHECK: ucomisd LCPI5_1(%rip), %xmm0 86} 87 88declare i32 @foo(...) 89 90define i32 @test6() nounwind align 2 { 91 %A = alloca {i64, i64}, align 8 92 %B = getelementptr inbounds {i64, i64}, {i64, i64}* %A, i64 0, i32 1 93 %C = load i64, i64* %B 94 %D = icmp eq i64 %C, 0 95 br i1 %D, label %T, label %F 96T: 97 ret i32 1 98 99F: 100 ret i32 0 101; CHECK-LABEL: test6: 102; CHECK: cmpq $0, -8(%rsp) 103; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] 104} 105 106; rdar://11866926 107define i32 @test7(i64 %res) nounwind { 108entry: 109; CHECK-LABEL: test7: 110; CHECK-NOT: movabsq 111; CHECK: shrq $32, %rdi 112; CHECK: sete 113 %lnot = icmp ult i64 %res, 4294967296 114 %lnot.ext = zext i1 %lnot to i32 115 ret i32 %lnot.ext 116} 117 118define i32 @test8(i64 %res) nounwind { 119entry: 120; CHECK-LABEL: test8: 121; CHECK-NOT: movabsq 122; CHECK: shrq $32, %rdi 123; CHECK: cmpq $3, %rdi 124 %lnot = icmp ult i64 %res, 12884901888 125 %lnot.ext = zext i1 %lnot to i32 126 ret i32 %lnot.ext 127} 128 129define i32 @test9(i64 %res) nounwind { 130entry: 131; CHECK-LABEL: test9: 132; CHECK-NOT: movabsq 133; CHECK: shrq $33, %rdi 134; CHECK: sete 135 %lnot = icmp ult i64 %res, 8589934592 136 %lnot.ext = zext i1 %lnot to i32 137 ret i32 %lnot.ext 138} 139 140define i32 @test10(i64 %res) nounwind { 141entry: 142; CHECK-LABEL: test10: 143; CHECK-NOT: movabsq 144; CHECK: shrq $32, %rdi 145; CHECK: setne 146 %lnot = icmp uge i64 %res, 4294967296 147 %lnot.ext = zext i1 %lnot to i32 148 ret i32 %lnot.ext 149} 150 151; rdar://9758774 152define i32 @test11(i64 %l) nounwind { 153entry: 154; CHECK-LABEL: test11: 155; CHECK-NOT: movabsq 156; CHECK-NOT: andq 157; CHECK: shrq $47, %rdi 158; CHECK: cmpq $1, %rdi 159 %shr.mask = and i64 %l, -140737488355328 160 %cmp = icmp eq i64 %shr.mask, 140737488355328 161 %conv = zext i1 %cmp to i32 162 ret i32 %conv 163} 164 165define i32 @test12() uwtable ssp { 166; CHECK-LABEL: test12: 167; CHECK: testb 168 %1 = call zeroext i1 @test12b() 169 br i1 %1, label %2, label %3 170 171; <label>:2 ; preds = %0 172 ret i32 1 173 174; <label>:3 ; preds = %0 175 ret i32 2 176} 177 178declare zeroext i1 @test12b() 179 180define i32 @test13(i32 %mask, i32 %base, i32 %intra) { 181 %and = and i32 %mask, 8 182 %tobool = icmp ne i32 %and, 0 183 %cond = select i1 %tobool, i32 %intra, i32 %base 184 ret i32 %cond 185 186; CHECK-LABEL: test13: 187; CHECK: testb $8, %dil 188; CHECK: cmovnel 189} 190 191define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 { 192 %s = lshr i32 %mask, 7 193 %tobool = icmp sgt i32 %s, -1 194 %cond = select i1 %tobool, i32 %intra, i32 %base 195 ret i32 %cond 196 197; CHECK-LABEL: test14: 198; CHECK: shrl $7, %edi 199; CHECK-NEXT: cmovnsl %edx, %esi 200} 201 202; PR19964 203define zeroext i1 @test15(i32 %bf.load, i32 %n) { 204 %bf.lshr = lshr i32 %bf.load, 16 205 %cmp2 = icmp eq i32 %bf.lshr, 0 206 %cmp5 = icmp uge i32 %bf.lshr, %n 207 %.cmp5 = or i1 %cmp2, %cmp5 208 ret i1 %.cmp5 209 210; CHECK-LABEL: test15: 211; CHECK: shrl $16, %edi 212; CHECK: cmpl %esi, %edi 213} 214 215define i8 @test16(i16 signext %L) { 216 %lshr = lshr i16 %L, 15 217 %trunc = trunc i16 %lshr to i8 218 %not = xor i8 %trunc, 1 219 ret i8 %not 220 221; CHECK-LABEL: test16: 222; CHECK: testw %di, %di 223; CHECK: setns %al 224} 225 226define i8 @test17(i32 %L) { 227 %lshr = lshr i32 %L, 31 228 %trunc = trunc i32 %lshr to i8 229 %not = xor i8 %trunc, 1 230 ret i8 %not 231 232; CHECK-LABEL: test17: 233; CHECK: testl %edi, %edi 234; CHECK: setns %al 235} 236 237define i8 @test18(i64 %L) { 238 %lshr = lshr i64 %L, 63 239 %trunc = trunc i64 %lshr to i8 240 %not = xor i8 %trunc, 1 241 ret i8 %not 242 243; CHECK-LABEL: test18: 244; CHECK: testq %rdi, %rdi 245; CHECK: setns %al 246} 247 248define zeroext i1 @test19(i32 %L) { 249 %lshr = lshr i32 %L, 31 250 %trunc = trunc i32 %lshr to i1 251 %not = xor i1 %trunc, 1 252 ret i1 %not 253 254; CHECK-LABEL: test19: 255; CHECK: testl %edi, %edi 256; CHECK: setns %al 257} 258 259@d = global i8 0, align 1 260 261; This test failed due to incorrect handling of "shift + icmp" sequence 262define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) { 263 %bf.shl = shl i32 %bf.load, 8 264 %bf.ashr = ashr exact i32 %bf.shl, 8 265 %tobool4 = icmp ne i32 %bf.ashr, 0 266 %conv = zext i1 %tobool4 to i32 267 %conv6 = zext i8 %x1 to i32 268 %add = add nuw nsw i32 %conv, %conv6 269 %tobool7 = icmp ne i32 %add, 0 270 %frombool = zext i1 %tobool7 to i8 271 store i8 %frombool, i8* %b_addr, align 1 272 %tobool14 = icmp ne i32 %bf.shl, 0 273 %frombool15 = zext i1 %tobool14 to i8 274 store i8 %frombool15, i8* @d, align 1 275 ret void 276 277; CHECK-LABEL: test20 278; CHECK: andl 279; CHECK: setne 280; CHECK: addl 281; CHECK: setne 282; CHECK: testl 283; CHECK: setne 284}