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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
9
10;
11; Signed Maximum (GT)
12;
13
14define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) {
15; SSE2-LABEL: max_gt_v2i64:
16; SSE2:       # BB#0:
17; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
18; SSE2-NEXT:    movdqa %xmm1, %xmm3
19; SSE2-NEXT:    pxor %xmm2, %xmm3
20; SSE2-NEXT:    pxor %xmm0, %xmm2
21; SSE2-NEXT:    movdqa %xmm2, %xmm4
22; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
23; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
24; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
25; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
26; SSE2-NEXT:    pand %xmm5, %xmm2
27; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
28; SSE2-NEXT:    por %xmm2, %xmm3
29; SSE2-NEXT:    pand %xmm3, %xmm0
30; SSE2-NEXT:    pandn %xmm1, %xmm3
31; SSE2-NEXT:    por %xmm3, %xmm0
32; SSE2-NEXT:    retq
33;
34; SSE41-LABEL: max_gt_v2i64:
35; SSE41:       # BB#0:
36; SSE41-NEXT:    movdqa %xmm0, %xmm2
37; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
38; SSE41-NEXT:    movdqa %xmm1, %xmm3
39; SSE41-NEXT:    pxor %xmm0, %xmm3
40; SSE41-NEXT:    pxor %xmm2, %xmm0
41; SSE41-NEXT:    movdqa %xmm0, %xmm4
42; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
43; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
44; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
45; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
46; SSE41-NEXT:    pand %xmm5, %xmm3
47; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
48; SSE41-NEXT:    por %xmm3, %xmm0
49; SSE41-NEXT:    blendvpd %xmm2, %xmm1
50; SSE41-NEXT:    movapd %xmm1, %xmm0
51; SSE41-NEXT:    retq
52;
53; SSE42-LABEL: max_gt_v2i64:
54; SSE42:       # BB#0:
55; SSE42-NEXT:    movdqa %xmm0, %xmm2
56; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
57; SSE42-NEXT:    blendvpd %xmm2, %xmm1
58; SSE42-NEXT:    movapd %xmm1, %xmm0
59; SSE42-NEXT:    retq
60;
61; AVX-LABEL: max_gt_v2i64:
62; AVX:       # BB#0:
63; AVX-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
64; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
65; AVX-NEXT:    retq
66  %1 = icmp sgt <2 x i64> %a, %b
67  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
68  ret <2 x i64> %2
69}
70
71define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) {
72; SSE2-LABEL: max_gt_v4i64:
73; SSE2:       # BB#0:
74; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0]
75; SSE2-NEXT:    movdqa %xmm3, %xmm5
76; SSE2-NEXT:    pxor %xmm4, %xmm5
77; SSE2-NEXT:    movdqa %xmm1, %xmm6
78; SSE2-NEXT:    pxor %xmm4, %xmm6
79; SSE2-NEXT:    movdqa %xmm6, %xmm7
80; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
81; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
82; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
83; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
84; SSE2-NEXT:    pand %xmm8, %xmm5
85; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
86; SSE2-NEXT:    por %xmm5, %xmm6
87; SSE2-NEXT:    movdqa %xmm2, %xmm5
88; SSE2-NEXT:    pxor %xmm4, %xmm5
89; SSE2-NEXT:    pxor %xmm0, %xmm4
90; SSE2-NEXT:    movdqa %xmm4, %xmm7
91; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
92; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
93; SSE2-NEXT:    pcmpeqd %xmm5, %xmm4
94; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
95; SSE2-NEXT:    pand %xmm8, %xmm4
96; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
97; SSE2-NEXT:    por %xmm4, %xmm5
98; SSE2-NEXT:    pand %xmm5, %xmm0
99; SSE2-NEXT:    pandn %xmm2, %xmm5
100; SSE2-NEXT:    por %xmm5, %xmm0
101; SSE2-NEXT:    pand %xmm6, %xmm1
102; SSE2-NEXT:    pandn %xmm3, %xmm6
103; SSE2-NEXT:    por %xmm6, %xmm1
104; SSE2-NEXT:    retq
105;
106; SSE41-LABEL: max_gt_v4i64:
107; SSE41:       # BB#0:
108; SSE41-NEXT:    movdqa %xmm0, %xmm8
109; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
110; SSE41-NEXT:    movdqa %xmm3, %xmm5
111; SSE41-NEXT:    pxor %xmm0, %xmm5
112; SSE41-NEXT:    movdqa %xmm1, %xmm6
113; SSE41-NEXT:    pxor %xmm0, %xmm6
114; SSE41-NEXT:    movdqa %xmm6, %xmm7
115; SSE41-NEXT:    pcmpgtd %xmm5, %xmm7
116; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
117; SSE41-NEXT:    pcmpeqd %xmm5, %xmm6
118; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
119; SSE41-NEXT:    pand %xmm4, %xmm6
120; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
121; SSE41-NEXT:    por %xmm6, %xmm5
122; SSE41-NEXT:    movdqa %xmm2, %xmm4
123; SSE41-NEXT:    pxor %xmm0, %xmm4
124; SSE41-NEXT:    pxor %xmm8, %xmm0
125; SSE41-NEXT:    movdqa %xmm0, %xmm6
126; SSE41-NEXT:    pcmpgtd %xmm4, %xmm6
127; SSE41-NEXT:    pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
128; SSE41-NEXT:    pcmpeqd %xmm4, %xmm0
129; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
130; SSE41-NEXT:    pand %xmm7, %xmm4
131; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
132; SSE41-NEXT:    por %xmm4, %xmm0
133; SSE41-NEXT:    blendvpd %xmm8, %xmm2
134; SSE41-NEXT:    movdqa %xmm5, %xmm0
135; SSE41-NEXT:    blendvpd %xmm1, %xmm3
136; SSE41-NEXT:    movapd %xmm2, %xmm0
137; SSE41-NEXT:    movapd %xmm3, %xmm1
138; SSE41-NEXT:    retq
139;
140; SSE42-LABEL: max_gt_v4i64:
141; SSE42:       # BB#0:
142; SSE42-NEXT:    movdqa %xmm0, %xmm4
143; SSE42-NEXT:    movdqa %xmm1, %xmm5
144; SSE42-NEXT:    pcmpgtq %xmm3, %xmm5
145; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
146; SSE42-NEXT:    blendvpd %xmm4, %xmm2
147; SSE42-NEXT:    movdqa %xmm5, %xmm0
148; SSE42-NEXT:    blendvpd %xmm1, %xmm3
149; SSE42-NEXT:    movapd %xmm2, %xmm0
150; SSE42-NEXT:    movapd %xmm3, %xmm1
151; SSE42-NEXT:    retq
152;
153; AVX1-LABEL: max_gt_v4i64:
154; AVX1:       # BB#0:
155; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
156; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
157; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
158; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm3
159; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
160; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
161; AVX1-NEXT:    retq
162;
163; AVX2-LABEL: max_gt_v4i64:
164; AVX2:       # BB#0:
165; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
166; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
167; AVX2-NEXT:    retq
168;
169; AVX512-LABEL: max_gt_v4i64:
170; AVX512:       # BB#0:
171; AVX512-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
172; AVX512-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
173; AVX512-NEXT:    retq
174  %1 = icmp sgt <4 x i64> %a, %b
175  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
176  ret <4 x i64> %2
177}
178
179define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) {
180; SSE2-LABEL: max_gt_v4i32:
181; SSE2:       # BB#0:
182; SSE2-NEXT:    movdqa %xmm0, %xmm2
183; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
184; SSE2-NEXT:    pand %xmm2, %xmm0
185; SSE2-NEXT:    pandn %xmm1, %xmm2
186; SSE2-NEXT:    por %xmm0, %xmm2
187; SSE2-NEXT:    movdqa %xmm2, %xmm0
188; SSE2-NEXT:    retq
189;
190; SSE41-LABEL: max_gt_v4i32:
191; SSE41:       # BB#0:
192; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
193; SSE41-NEXT:    retq
194;
195; SSE42-LABEL: max_gt_v4i32:
196; SSE42:       # BB#0:
197; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
198; SSE42-NEXT:    retq
199;
200; AVX-LABEL: max_gt_v4i32:
201; AVX:       # BB#0:
202; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
203; AVX-NEXT:    retq
204  %1 = icmp sgt <4 x i32> %a, %b
205  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
206  ret <4 x i32> %2
207}
208
209define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) {
210; SSE2-LABEL: max_gt_v8i32:
211; SSE2:       # BB#0:
212; SSE2-NEXT:    movdqa %xmm1, %xmm4
213; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
214; SSE2-NEXT:    movdqa %xmm0, %xmm5
215; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
216; SSE2-NEXT:    pand %xmm5, %xmm0
217; SSE2-NEXT:    pandn %xmm2, %xmm5
218; SSE2-NEXT:    por %xmm0, %xmm5
219; SSE2-NEXT:    pand %xmm4, %xmm1
220; SSE2-NEXT:    pandn %xmm3, %xmm4
221; SSE2-NEXT:    por %xmm1, %xmm4
222; SSE2-NEXT:    movdqa %xmm5, %xmm0
223; SSE2-NEXT:    movdqa %xmm4, %xmm1
224; SSE2-NEXT:    retq
225;
226; SSE41-LABEL: max_gt_v8i32:
227; SSE41:       # BB#0:
228; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
229; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
230; SSE41-NEXT:    retq
231;
232; SSE42-LABEL: max_gt_v8i32:
233; SSE42:       # BB#0:
234; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
235; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
236; SSE42-NEXT:    retq
237;
238; AVX1-LABEL: max_gt_v8i32:
239; AVX1:       # BB#0:
240; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
241; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
242; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
243; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
244; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
245; AVX1-NEXT:    retq
246;
247; AVX2-LABEL: max_gt_v8i32:
248; AVX2:       # BB#0:
249; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
250; AVX2-NEXT:    retq
251;
252; AVX512-LABEL: max_gt_v8i32:
253; AVX512:       # BB#0:
254; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
255; AVX512-NEXT:    retq
256  %1 = icmp sgt <8 x i32> %a, %b
257  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
258  ret <8 x i32> %2
259}
260
261define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) {
262; SSE-LABEL: max_gt_v8i16:
263; SSE:       # BB#0:
264; SSE-NEXT:    pmaxsw %xmm1, %xmm0
265; SSE-NEXT:    retq
266;
267; AVX-LABEL: max_gt_v8i16:
268; AVX:       # BB#0:
269; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
270; AVX-NEXT:    retq
271  %1 = icmp sgt <8 x i16> %a, %b
272  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
273  ret <8 x i16> %2
274}
275
276define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) {
277; SSE-LABEL: max_gt_v16i16:
278; SSE:       # BB#0:
279; SSE-NEXT:    pmaxsw %xmm2, %xmm0
280; SSE-NEXT:    pmaxsw %xmm3, %xmm1
281; SSE-NEXT:    retq
282;
283; AVX1-LABEL: max_gt_v16i16:
284; AVX1:       # BB#0:
285; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
286; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
287; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
288; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
289; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
290; AVX1-NEXT:    retq
291;
292; AVX2-LABEL: max_gt_v16i16:
293; AVX2:       # BB#0:
294; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
295; AVX2-NEXT:    retq
296;
297; AVX512-LABEL: max_gt_v16i16:
298; AVX512:       # BB#0:
299; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
300; AVX512-NEXT:    retq
301  %1 = icmp sgt <16 x i16> %a, %b
302  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
303  ret <16 x i16> %2
304}
305
306define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) {
307; SSE2-LABEL: max_gt_v16i8:
308; SSE2:       # BB#0:
309; SSE2-NEXT:    movdqa %xmm0, %xmm2
310; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
311; SSE2-NEXT:    pand %xmm2, %xmm0
312; SSE2-NEXT:    pandn %xmm1, %xmm2
313; SSE2-NEXT:    por %xmm0, %xmm2
314; SSE2-NEXT:    movdqa %xmm2, %xmm0
315; SSE2-NEXT:    retq
316;
317; SSE41-LABEL: max_gt_v16i8:
318; SSE41:       # BB#0:
319; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
320; SSE41-NEXT:    retq
321;
322; SSE42-LABEL: max_gt_v16i8:
323; SSE42:       # BB#0:
324; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
325; SSE42-NEXT:    retq
326;
327; AVX-LABEL: max_gt_v16i8:
328; AVX:       # BB#0:
329; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
330; AVX-NEXT:    retq
331  %1 = icmp sgt <16 x i8> %a, %b
332  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
333  ret <16 x i8> %2
334}
335
336define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) {
337; SSE2-LABEL: max_gt_v32i8:
338; SSE2:       # BB#0:
339; SSE2-NEXT:    movdqa %xmm1, %xmm4
340; SSE2-NEXT:    pcmpgtb %xmm3, %xmm4
341; SSE2-NEXT:    movdqa %xmm0, %xmm5
342; SSE2-NEXT:    pcmpgtb %xmm2, %xmm5
343; SSE2-NEXT:    pand %xmm5, %xmm0
344; SSE2-NEXT:    pandn %xmm2, %xmm5
345; SSE2-NEXT:    por %xmm0, %xmm5
346; SSE2-NEXT:    pand %xmm4, %xmm1
347; SSE2-NEXT:    pandn %xmm3, %xmm4
348; SSE2-NEXT:    por %xmm1, %xmm4
349; SSE2-NEXT:    movdqa %xmm5, %xmm0
350; SSE2-NEXT:    movdqa %xmm4, %xmm1
351; SSE2-NEXT:    retq
352;
353; SSE41-LABEL: max_gt_v32i8:
354; SSE41:       # BB#0:
355; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
356; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
357; SSE41-NEXT:    retq
358;
359; SSE42-LABEL: max_gt_v32i8:
360; SSE42:       # BB#0:
361; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
362; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
363; SSE42-NEXT:    retq
364;
365; AVX1-LABEL: max_gt_v32i8:
366; AVX1:       # BB#0:
367; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
368; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
369; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
370; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
371; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
372; AVX1-NEXT:    retq
373;
374; AVX2-LABEL: max_gt_v32i8:
375; AVX2:       # BB#0:
376; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
377; AVX2-NEXT:    retq
378;
379; AVX512-LABEL: max_gt_v32i8:
380; AVX512:       # BB#0:
381; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
382; AVX512-NEXT:    retq
383  %1 = icmp sgt <32 x i8> %a, %b
384  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
385  ret <32 x i8> %2
386}
387
388;
389; Signed Maximum (GE)
390;
391
392define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) {
393; SSE2-LABEL: max_ge_v2i64:
394; SSE2:       # BB#0:
395; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
396; SSE2-NEXT:    movdqa %xmm0, %xmm3
397; SSE2-NEXT:    pxor %xmm2, %xmm3
398; SSE2-NEXT:    pxor %xmm1, %xmm2
399; SSE2-NEXT:    movdqa %xmm2, %xmm4
400; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
401; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
402; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
403; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
404; SSE2-NEXT:    pand %xmm5, %xmm2
405; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
406; SSE2-NEXT:    por %xmm2, %xmm3
407; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
408; SSE2-NEXT:    pxor %xmm3, %xmm2
409; SSE2-NEXT:    pandn %xmm0, %xmm3
410; SSE2-NEXT:    pandn %xmm1, %xmm2
411; SSE2-NEXT:    por %xmm3, %xmm2
412; SSE2-NEXT:    movdqa %xmm2, %xmm0
413; SSE2-NEXT:    retq
414;
415; SSE41-LABEL: max_ge_v2i64:
416; SSE41:       # BB#0:
417; SSE41-NEXT:    movdqa %xmm0, %xmm2
418; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
419; SSE41-NEXT:    movdqa %xmm2, %xmm3
420; SSE41-NEXT:    pxor %xmm0, %xmm3
421; SSE41-NEXT:    pxor %xmm1, %xmm0
422; SSE41-NEXT:    movdqa %xmm0, %xmm4
423; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
424; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
425; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
426; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
427; SSE41-NEXT:    pand %xmm5, %xmm0
428; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
429; SSE41-NEXT:    por %xmm0, %xmm3
430; SSE41-NEXT:    pcmpeqd %xmm0, %xmm0
431; SSE41-NEXT:    pxor %xmm3, %xmm0
432; SSE41-NEXT:    blendvpd %xmm2, %xmm1
433; SSE41-NEXT:    movapd %xmm1, %xmm0
434; SSE41-NEXT:    retq
435;
436; SSE42-LABEL: max_ge_v2i64:
437; SSE42:       # BB#0:
438; SSE42-NEXT:    movdqa %xmm0, %xmm2
439; SSE42-NEXT:    movdqa %xmm1, %xmm3
440; SSE42-NEXT:    pcmpgtq %xmm2, %xmm3
441; SSE42-NEXT:    pcmpeqd %xmm0, %xmm0
442; SSE42-NEXT:    pxor %xmm3, %xmm0
443; SSE42-NEXT:    blendvpd %xmm2, %xmm1
444; SSE42-NEXT:    movapd %xmm1, %xmm0
445; SSE42-NEXT:    retq
446;
447; AVX-LABEL: max_ge_v2i64:
448; AVX:       # BB#0:
449; AVX-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
450; AVX-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
451; AVX-NEXT:    vpxor %xmm3, %xmm2, %xmm2
452; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
453; AVX-NEXT:    retq
454  %1 = icmp sge <2 x i64> %a, %b
455  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
456  ret <2 x i64> %2
457}
458
459define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) {
460; SSE2-LABEL: max_ge_v4i64:
461; SSE2:       # BB#0:
462; SSE2-NEXT:    movdqa {{.*#+}} xmm7 = [2147483648,0,2147483648,0]
463; SSE2-NEXT:    movdqa %xmm1, %xmm4
464; SSE2-NEXT:    pxor %xmm7, %xmm4
465; SSE2-NEXT:    movdqa %xmm3, %xmm5
466; SSE2-NEXT:    pxor %xmm7, %xmm5
467; SSE2-NEXT:    movdqa %xmm5, %xmm6
468; SSE2-NEXT:    pcmpgtd %xmm4, %xmm6
469; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm6[0,0,2,2]
470; SSE2-NEXT:    pcmpeqd %xmm4, %xmm5
471; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
472; SSE2-NEXT:    pand %xmm8, %xmm4
473; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm6[1,1,3,3]
474; SSE2-NEXT:    por %xmm4, %xmm8
475; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
476; SSE2-NEXT:    movdqa %xmm8, %xmm9
477; SSE2-NEXT:    pxor %xmm4, %xmm9
478; SSE2-NEXT:    movdqa %xmm0, %xmm6
479; SSE2-NEXT:    pxor %xmm7, %xmm6
480; SSE2-NEXT:    pxor %xmm2, %xmm7
481; SSE2-NEXT:    movdqa %xmm7, %xmm5
482; SSE2-NEXT:    pcmpgtd %xmm6, %xmm5
483; SSE2-NEXT:    pshufd {{.*#+}} xmm10 = xmm5[0,0,2,2]
484; SSE2-NEXT:    pcmpeqd %xmm6, %xmm7
485; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
486; SSE2-NEXT:    pand %xmm10, %xmm6
487; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
488; SSE2-NEXT:    por %xmm6, %xmm5
489; SSE2-NEXT:    pxor %xmm5, %xmm4
490; SSE2-NEXT:    pandn %xmm0, %xmm5
491; SSE2-NEXT:    pandn %xmm2, %xmm4
492; SSE2-NEXT:    por %xmm5, %xmm4
493; SSE2-NEXT:    pandn %xmm1, %xmm8
494; SSE2-NEXT:    pandn %xmm3, %xmm9
495; SSE2-NEXT:    por %xmm8, %xmm9
496; SSE2-NEXT:    movdqa %xmm4, %xmm0
497; SSE2-NEXT:    movdqa %xmm9, %xmm1
498; SSE2-NEXT:    retq
499;
500; SSE41-LABEL: max_ge_v4i64:
501; SSE41:       # BB#0:
502; SSE41-NEXT:    movdqa %xmm0, %xmm8
503; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
504; SSE41-NEXT:    movdqa %xmm1, %xmm5
505; SSE41-NEXT:    pxor %xmm0, %xmm5
506; SSE41-NEXT:    movdqa %xmm3, %xmm6
507; SSE41-NEXT:    pxor %xmm0, %xmm6
508; SSE41-NEXT:    movdqa %xmm6, %xmm7
509; SSE41-NEXT:    pcmpgtd %xmm5, %xmm7
510; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
511; SSE41-NEXT:    pcmpeqd %xmm5, %xmm6
512; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
513; SSE41-NEXT:    pand %xmm4, %xmm6
514; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
515; SSE41-NEXT:    por %xmm6, %xmm5
516; SSE41-NEXT:    pcmpeqd %xmm9, %xmm9
517; SSE41-NEXT:    pxor %xmm9, %xmm5
518; SSE41-NEXT:    movdqa %xmm8, %xmm6
519; SSE41-NEXT:    pxor %xmm0, %xmm6
520; SSE41-NEXT:    pxor %xmm2, %xmm0
521; SSE41-NEXT:    movdqa %xmm0, %xmm7
522; SSE41-NEXT:    pcmpgtd %xmm6, %xmm7
523; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
524; SSE41-NEXT:    pcmpeqd %xmm6, %xmm0
525; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
526; SSE41-NEXT:    pand %xmm4, %xmm6
527; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm7[1,1,3,3]
528; SSE41-NEXT:    por %xmm6, %xmm0
529; SSE41-NEXT:    pxor %xmm9, %xmm0
530; SSE41-NEXT:    blendvpd %xmm8, %xmm2
531; SSE41-NEXT:    movdqa %xmm5, %xmm0
532; SSE41-NEXT:    blendvpd %xmm1, %xmm3
533; SSE41-NEXT:    movapd %xmm2, %xmm0
534; SSE41-NEXT:    movapd %xmm3, %xmm1
535; SSE41-NEXT:    retq
536;
537; SSE42-LABEL: max_ge_v4i64:
538; SSE42:       # BB#0:
539; SSE42-NEXT:    movdqa %xmm0, %xmm4
540; SSE42-NEXT:    movdqa %xmm3, %xmm5
541; SSE42-NEXT:    pcmpgtq %xmm1, %xmm5
542; SSE42-NEXT:    pcmpeqd %xmm0, %xmm0
543; SSE42-NEXT:    pxor %xmm0, %xmm5
544; SSE42-NEXT:    movdqa %xmm2, %xmm6
545; SSE42-NEXT:    pcmpgtq %xmm4, %xmm6
546; SSE42-NEXT:    pxor %xmm6, %xmm0
547; SSE42-NEXT:    blendvpd %xmm4, %xmm2
548; SSE42-NEXT:    movdqa %xmm5, %xmm0
549; SSE42-NEXT:    blendvpd %xmm1, %xmm3
550; SSE42-NEXT:    movapd %xmm2, %xmm0
551; SSE42-NEXT:    movapd %xmm3, %xmm1
552; SSE42-NEXT:    retq
553;
554; AVX1-LABEL: max_ge_v4i64:
555; AVX1:       # BB#0:
556; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
557; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
558; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
559; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
560; AVX1-NEXT:    vpxor %xmm3, %xmm2, %xmm2
561; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm4
562; AVX1-NEXT:    vpxor %xmm3, %xmm4, %xmm3
563; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
564; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
565; AVX1-NEXT:    retq
566;
567; AVX2-LABEL: max_ge_v4i64:
568; AVX2:       # BB#0:
569; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
570; AVX2-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
571; AVX2-NEXT:    vpxor %ymm3, %ymm2, %ymm2
572; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
573; AVX2-NEXT:    retq
574;
575; AVX512-LABEL: max_ge_v4i64:
576; AVX512:       # BB#0:
577; AVX512-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
578; AVX512-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
579; AVX512-NEXT:    vpxor %ymm3, %ymm2, %ymm2
580; AVX512-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
581; AVX512-NEXT:    retq
582  %1 = icmp sge <4 x i64> %a, %b
583  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
584  ret <4 x i64> %2
585}
586
587define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) {
588; SSE2-LABEL: max_ge_v4i32:
589; SSE2:       # BB#0:
590; SSE2-NEXT:    movdqa %xmm1, %xmm3
591; SSE2-NEXT:    pcmpgtd %xmm0, %xmm3
592; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
593; SSE2-NEXT:    pxor %xmm3, %xmm2
594; SSE2-NEXT:    pandn %xmm0, %xmm3
595; SSE2-NEXT:    pandn %xmm1, %xmm2
596; SSE2-NEXT:    por %xmm3, %xmm2
597; SSE2-NEXT:    movdqa %xmm2, %xmm0
598; SSE2-NEXT:    retq
599;
600; SSE41-LABEL: max_ge_v4i32:
601; SSE41:       # BB#0:
602; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
603; SSE41-NEXT:    retq
604;
605; SSE42-LABEL: max_ge_v4i32:
606; SSE42:       # BB#0:
607; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
608; SSE42-NEXT:    retq
609;
610; AVX-LABEL: max_ge_v4i32:
611; AVX:       # BB#0:
612; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
613; AVX-NEXT:    retq
614  %1 = icmp sge <4 x i32> %a, %b
615  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
616  ret <4 x i32> %2
617}
618
619define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) {
620; SSE2-LABEL: max_ge_v8i32:
621; SSE2:       # BB#0:
622; SSE2-NEXT:    movdqa %xmm3, %xmm6
623; SSE2-NEXT:    pcmpgtd %xmm1, %xmm6
624; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
625; SSE2-NEXT:    movdqa %xmm6, %xmm5
626; SSE2-NEXT:    pxor %xmm4, %xmm5
627; SSE2-NEXT:    movdqa %xmm2, %xmm7
628; SSE2-NEXT:    pcmpgtd %xmm0, %xmm7
629; SSE2-NEXT:    pxor %xmm7, %xmm4
630; SSE2-NEXT:    pandn %xmm0, %xmm7
631; SSE2-NEXT:    pandn %xmm2, %xmm4
632; SSE2-NEXT:    por %xmm7, %xmm4
633; SSE2-NEXT:    pandn %xmm1, %xmm6
634; SSE2-NEXT:    pandn %xmm3, %xmm5
635; SSE2-NEXT:    por %xmm6, %xmm5
636; SSE2-NEXT:    movdqa %xmm4, %xmm0
637; SSE2-NEXT:    movdqa %xmm5, %xmm1
638; SSE2-NEXT:    retq
639;
640; SSE41-LABEL: max_ge_v8i32:
641; SSE41:       # BB#0:
642; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
643; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
644; SSE41-NEXT:    retq
645;
646; SSE42-LABEL: max_ge_v8i32:
647; SSE42:       # BB#0:
648; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
649; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
650; SSE42-NEXT:    retq
651;
652; AVX1-LABEL: max_ge_v8i32:
653; AVX1:       # BB#0:
654; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
655; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
656; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
657; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
658; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
659; AVX1-NEXT:    retq
660;
661; AVX2-LABEL: max_ge_v8i32:
662; AVX2:       # BB#0:
663; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
664; AVX2-NEXT:    retq
665;
666; AVX512-LABEL: max_ge_v8i32:
667; AVX512:       # BB#0:
668; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
669; AVX512-NEXT:    retq
670  %1 = icmp sge <8 x i32> %a, %b
671  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
672  ret <8 x i32> %2
673}
674
675define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) {
676; SSE-LABEL: max_ge_v8i16:
677; SSE:       # BB#0:
678; SSE-NEXT:    pmaxsw %xmm1, %xmm0
679; SSE-NEXT:    retq
680;
681; AVX-LABEL: max_ge_v8i16:
682; AVX:       # BB#0:
683; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
684; AVX-NEXT:    retq
685  %1 = icmp sge <8 x i16> %a, %b
686  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
687  ret <8 x i16> %2
688}
689
690define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) {
691; SSE-LABEL: max_ge_v16i16:
692; SSE:       # BB#0:
693; SSE-NEXT:    pmaxsw %xmm2, %xmm0
694; SSE-NEXT:    pmaxsw %xmm3, %xmm1
695; SSE-NEXT:    retq
696;
697; AVX1-LABEL: max_ge_v16i16:
698; AVX1:       # BB#0:
699; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
700; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
701; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
702; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
703; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
704; AVX1-NEXT:    retq
705;
706; AVX2-LABEL: max_ge_v16i16:
707; AVX2:       # BB#0:
708; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
709; AVX2-NEXT:    retq
710;
711; AVX512-LABEL: max_ge_v16i16:
712; AVX512:       # BB#0:
713; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
714; AVX512-NEXT:    retq
715  %1 = icmp sge <16 x i16> %a, %b
716  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
717  ret <16 x i16> %2
718}
719
720define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) {
721; SSE2-LABEL: max_ge_v16i8:
722; SSE2:       # BB#0:
723; SSE2-NEXT:    movdqa %xmm1, %xmm3
724; SSE2-NEXT:    pcmpgtb %xmm0, %xmm3
725; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
726; SSE2-NEXT:    pxor %xmm3, %xmm2
727; SSE2-NEXT:    pandn %xmm0, %xmm3
728; SSE2-NEXT:    pandn %xmm1, %xmm2
729; SSE2-NEXT:    por %xmm3, %xmm2
730; SSE2-NEXT:    movdqa %xmm2, %xmm0
731; SSE2-NEXT:    retq
732;
733; SSE41-LABEL: max_ge_v16i8:
734; SSE41:       # BB#0:
735; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
736; SSE41-NEXT:    retq
737;
738; SSE42-LABEL: max_ge_v16i8:
739; SSE42:       # BB#0:
740; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
741; SSE42-NEXT:    retq
742;
743; AVX-LABEL: max_ge_v16i8:
744; AVX:       # BB#0:
745; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
746; AVX-NEXT:    retq
747  %1 = icmp sge <16 x i8> %a, %b
748  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
749  ret <16 x i8> %2
750}
751
752define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) {
753; SSE2-LABEL: max_ge_v32i8:
754; SSE2:       # BB#0:
755; SSE2-NEXT:    movdqa %xmm3, %xmm6
756; SSE2-NEXT:    pcmpgtb %xmm1, %xmm6
757; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
758; SSE2-NEXT:    movdqa %xmm6, %xmm5
759; SSE2-NEXT:    pxor %xmm4, %xmm5
760; SSE2-NEXT:    movdqa %xmm2, %xmm7
761; SSE2-NEXT:    pcmpgtb %xmm0, %xmm7
762; SSE2-NEXT:    pxor %xmm7, %xmm4
763; SSE2-NEXT:    pandn %xmm0, %xmm7
764; SSE2-NEXT:    pandn %xmm2, %xmm4
765; SSE2-NEXT:    por %xmm7, %xmm4
766; SSE2-NEXT:    pandn %xmm1, %xmm6
767; SSE2-NEXT:    pandn %xmm3, %xmm5
768; SSE2-NEXT:    por %xmm6, %xmm5
769; SSE2-NEXT:    movdqa %xmm4, %xmm0
770; SSE2-NEXT:    movdqa %xmm5, %xmm1
771; SSE2-NEXT:    retq
772;
773; SSE41-LABEL: max_ge_v32i8:
774; SSE41:       # BB#0:
775; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
776; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
777; SSE41-NEXT:    retq
778;
779; SSE42-LABEL: max_ge_v32i8:
780; SSE42:       # BB#0:
781; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
782; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
783; SSE42-NEXT:    retq
784;
785; AVX1-LABEL: max_ge_v32i8:
786; AVX1:       # BB#0:
787; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
788; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
789; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
790; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
791; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
792; AVX1-NEXT:    retq
793;
794; AVX2-LABEL: max_ge_v32i8:
795; AVX2:       # BB#0:
796; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
797; AVX2-NEXT:    retq
798;
799; AVX512-LABEL: max_ge_v32i8:
800; AVX512:       # BB#0:
801; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
802; AVX512-NEXT:    retq
803  %1 = icmp sge <32 x i8> %a, %b
804  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
805  ret <32 x i8> %2
806}
807
808;
809; Signed Minimum (LT)
810;
811
812define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) {
813; SSE2-LABEL: min_lt_v2i64:
814; SSE2:       # BB#0:
815; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
816; SSE2-NEXT:    movdqa %xmm0, %xmm3
817; SSE2-NEXT:    pxor %xmm2, %xmm3
818; SSE2-NEXT:    pxor %xmm1, %xmm2
819; SSE2-NEXT:    movdqa %xmm2, %xmm4
820; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
821; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
822; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
823; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
824; SSE2-NEXT:    pand %xmm5, %xmm2
825; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
826; SSE2-NEXT:    por %xmm2, %xmm3
827; SSE2-NEXT:    pand %xmm3, %xmm0
828; SSE2-NEXT:    pandn %xmm1, %xmm3
829; SSE2-NEXT:    por %xmm3, %xmm0
830; SSE2-NEXT:    retq
831;
832; SSE41-LABEL: min_lt_v2i64:
833; SSE41:       # BB#0:
834; SSE41-NEXT:    movdqa %xmm0, %xmm2
835; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
836; SSE41-NEXT:    movdqa %xmm2, %xmm3
837; SSE41-NEXT:    pxor %xmm0, %xmm3
838; SSE41-NEXT:    pxor %xmm1, %xmm0
839; SSE41-NEXT:    movdqa %xmm0, %xmm4
840; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
841; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
842; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
843; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
844; SSE41-NEXT:    pand %xmm5, %xmm3
845; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
846; SSE41-NEXT:    por %xmm3, %xmm0
847; SSE41-NEXT:    blendvpd %xmm2, %xmm1
848; SSE41-NEXT:    movapd %xmm1, %xmm0
849; SSE41-NEXT:    retq
850;
851; SSE42-LABEL: min_lt_v2i64:
852; SSE42:       # BB#0:
853; SSE42-NEXT:    movdqa %xmm0, %xmm2
854; SSE42-NEXT:    movdqa %xmm1, %xmm0
855; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
856; SSE42-NEXT:    blendvpd %xmm2, %xmm1
857; SSE42-NEXT:    movapd %xmm1, %xmm0
858; SSE42-NEXT:    retq
859;
860; AVX-LABEL: min_lt_v2i64:
861; AVX:       # BB#0:
862; AVX-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
863; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
864; AVX-NEXT:    retq
865  %1 = icmp slt <2 x i64> %a, %b
866  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
867  ret <2 x i64> %2
868}
869
870define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) {
871; SSE2-LABEL: min_lt_v4i64:
872; SSE2:       # BB#0:
873; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0]
874; SSE2-NEXT:    movdqa %xmm1, %xmm5
875; SSE2-NEXT:    pxor %xmm4, %xmm5
876; SSE2-NEXT:    movdqa %xmm3, %xmm6
877; SSE2-NEXT:    pxor %xmm4, %xmm6
878; SSE2-NEXT:    movdqa %xmm6, %xmm7
879; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
880; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
881; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
882; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
883; SSE2-NEXT:    pand %xmm8, %xmm5
884; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
885; SSE2-NEXT:    por %xmm5, %xmm6
886; SSE2-NEXT:    movdqa %xmm0, %xmm5
887; SSE2-NEXT:    pxor %xmm4, %xmm5
888; SSE2-NEXT:    pxor %xmm2, %xmm4
889; SSE2-NEXT:    movdqa %xmm4, %xmm7
890; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
891; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
892; SSE2-NEXT:    pcmpeqd %xmm5, %xmm4
893; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
894; SSE2-NEXT:    pand %xmm8, %xmm4
895; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
896; SSE2-NEXT:    por %xmm4, %xmm5
897; SSE2-NEXT:    pand %xmm5, %xmm0
898; SSE2-NEXT:    pandn %xmm2, %xmm5
899; SSE2-NEXT:    por %xmm5, %xmm0
900; SSE2-NEXT:    pand %xmm6, %xmm1
901; SSE2-NEXT:    pandn %xmm3, %xmm6
902; SSE2-NEXT:    por %xmm6, %xmm1
903; SSE2-NEXT:    retq
904;
905; SSE41-LABEL: min_lt_v4i64:
906; SSE41:       # BB#0:
907; SSE41-NEXT:    movdqa %xmm0, %xmm8
908; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
909; SSE41-NEXT:    movdqa %xmm1, %xmm5
910; SSE41-NEXT:    pxor %xmm0, %xmm5
911; SSE41-NEXT:    movdqa %xmm3, %xmm6
912; SSE41-NEXT:    pxor %xmm0, %xmm6
913; SSE41-NEXT:    movdqa %xmm6, %xmm7
914; SSE41-NEXT:    pcmpgtd %xmm5, %xmm7
915; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
916; SSE41-NEXT:    pcmpeqd %xmm5, %xmm6
917; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
918; SSE41-NEXT:    pand %xmm4, %xmm6
919; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
920; SSE41-NEXT:    por %xmm6, %xmm5
921; SSE41-NEXT:    movdqa %xmm8, %xmm4
922; SSE41-NEXT:    pxor %xmm0, %xmm4
923; SSE41-NEXT:    pxor %xmm2, %xmm0
924; SSE41-NEXT:    movdqa %xmm0, %xmm6
925; SSE41-NEXT:    pcmpgtd %xmm4, %xmm6
926; SSE41-NEXT:    pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
927; SSE41-NEXT:    pcmpeqd %xmm4, %xmm0
928; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
929; SSE41-NEXT:    pand %xmm7, %xmm4
930; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
931; SSE41-NEXT:    por %xmm4, %xmm0
932; SSE41-NEXT:    blendvpd %xmm8, %xmm2
933; SSE41-NEXT:    movdqa %xmm5, %xmm0
934; SSE41-NEXT:    blendvpd %xmm1, %xmm3
935; SSE41-NEXT:    movapd %xmm2, %xmm0
936; SSE41-NEXT:    movapd %xmm3, %xmm1
937; SSE41-NEXT:    retq
938;
939; SSE42-LABEL: min_lt_v4i64:
940; SSE42:       # BB#0:
941; SSE42-NEXT:    movdqa %xmm0, %xmm4
942; SSE42-NEXT:    movdqa %xmm3, %xmm5
943; SSE42-NEXT:    pcmpgtq %xmm1, %xmm5
944; SSE42-NEXT:    movdqa %xmm2, %xmm0
945; SSE42-NEXT:    pcmpgtq %xmm4, %xmm0
946; SSE42-NEXT:    blendvpd %xmm4, %xmm2
947; SSE42-NEXT:    movdqa %xmm5, %xmm0
948; SSE42-NEXT:    blendvpd %xmm1, %xmm3
949; SSE42-NEXT:    movapd %xmm2, %xmm0
950; SSE42-NEXT:    movapd %xmm3, %xmm1
951; SSE42-NEXT:    retq
952;
953; AVX1-LABEL: min_lt_v4i64:
954; AVX1:       # BB#0:
955; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
956; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
957; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
958; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm3
959; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
960; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
961; AVX1-NEXT:    retq
962;
963; AVX2-LABEL: min_lt_v4i64:
964; AVX2:       # BB#0:
965; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
966; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
967; AVX2-NEXT:    retq
968;
969; AVX512-LABEL: min_lt_v4i64:
970; AVX512:       # BB#0:
971; AVX512-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
972; AVX512-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
973; AVX512-NEXT:    retq
974  %1 = icmp slt <4 x i64> %a, %b
975  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
976  ret <4 x i64> %2
977}
978
979define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) {
980; SSE2-LABEL: min_lt_v4i32:
981; SSE2:       # BB#0:
982; SSE2-NEXT:    movdqa %xmm1, %xmm2
983; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
984; SSE2-NEXT:    pand %xmm2, %xmm0
985; SSE2-NEXT:    pandn %xmm1, %xmm2
986; SSE2-NEXT:    por %xmm2, %xmm0
987; SSE2-NEXT:    retq
988;
989; SSE41-LABEL: min_lt_v4i32:
990; SSE41:       # BB#0:
991; SSE41-NEXT:    pminsd %xmm1, %xmm0
992; SSE41-NEXT:    retq
993;
994; SSE42-LABEL: min_lt_v4i32:
995; SSE42:       # BB#0:
996; SSE42-NEXT:    pminsd %xmm1, %xmm0
997; SSE42-NEXT:    retq
998;
999; AVX-LABEL: min_lt_v4i32:
1000; AVX:       # BB#0:
1001; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1002; AVX-NEXT:    retq
1003  %1 = icmp slt <4 x i32> %a, %b
1004  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1005  ret <4 x i32> %2
1006}
1007
1008define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) {
1009; SSE2-LABEL: min_lt_v8i32:
1010; SSE2:       # BB#0:
1011; SSE2-NEXT:    movdqa %xmm3, %xmm4
1012; SSE2-NEXT:    pcmpgtd %xmm1, %xmm4
1013; SSE2-NEXT:    movdqa %xmm2, %xmm5
1014; SSE2-NEXT:    pcmpgtd %xmm0, %xmm5
1015; SSE2-NEXT:    pand %xmm5, %xmm0
1016; SSE2-NEXT:    pandn %xmm2, %xmm5
1017; SSE2-NEXT:    por %xmm5, %xmm0
1018; SSE2-NEXT:    pand %xmm4, %xmm1
1019; SSE2-NEXT:    pandn %xmm3, %xmm4
1020; SSE2-NEXT:    por %xmm4, %xmm1
1021; SSE2-NEXT:    retq
1022;
1023; SSE41-LABEL: min_lt_v8i32:
1024; SSE41:       # BB#0:
1025; SSE41-NEXT:    pminsd %xmm2, %xmm0
1026; SSE41-NEXT:    pminsd %xmm3, %xmm1
1027; SSE41-NEXT:    retq
1028;
1029; SSE42-LABEL: min_lt_v8i32:
1030; SSE42:       # BB#0:
1031; SSE42-NEXT:    pminsd %xmm2, %xmm0
1032; SSE42-NEXT:    pminsd %xmm3, %xmm1
1033; SSE42-NEXT:    retq
1034;
1035; AVX1-LABEL: min_lt_v8i32:
1036; AVX1:       # BB#0:
1037; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1038; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1039; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1040; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1041; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1042; AVX1-NEXT:    retq
1043;
1044; AVX2-LABEL: min_lt_v8i32:
1045; AVX2:       # BB#0:
1046; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1047; AVX2-NEXT:    retq
1048;
1049; AVX512-LABEL: min_lt_v8i32:
1050; AVX512:       # BB#0:
1051; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1052; AVX512-NEXT:    retq
1053  %1 = icmp slt <8 x i32> %a, %b
1054  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1055  ret <8 x i32> %2
1056}
1057
1058define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) {
1059; SSE-LABEL: min_lt_v8i16:
1060; SSE:       # BB#0:
1061; SSE-NEXT:    pminsw %xmm1, %xmm0
1062; SSE-NEXT:    retq
1063;
1064; AVX-LABEL: min_lt_v8i16:
1065; AVX:       # BB#0:
1066; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1067; AVX-NEXT:    retq
1068  %1 = icmp slt <8 x i16> %a, %b
1069  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1070  ret <8 x i16> %2
1071}
1072
1073define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) {
1074; SSE-LABEL: min_lt_v16i16:
1075; SSE:       # BB#0:
1076; SSE-NEXT:    pminsw %xmm2, %xmm0
1077; SSE-NEXT:    pminsw %xmm3, %xmm1
1078; SSE-NEXT:    retq
1079;
1080; AVX1-LABEL: min_lt_v16i16:
1081; AVX1:       # BB#0:
1082; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1083; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1084; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1085; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1086; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1087; AVX1-NEXT:    retq
1088;
1089; AVX2-LABEL: min_lt_v16i16:
1090; AVX2:       # BB#0:
1091; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1092; AVX2-NEXT:    retq
1093;
1094; AVX512-LABEL: min_lt_v16i16:
1095; AVX512:       # BB#0:
1096; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1097; AVX512-NEXT:    retq
1098  %1 = icmp slt <16 x i16> %a, %b
1099  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1100  ret <16 x i16> %2
1101}
1102
1103define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) {
1104; SSE2-LABEL: min_lt_v16i8:
1105; SSE2:       # BB#0:
1106; SSE2-NEXT:    movdqa %xmm1, %xmm2
1107; SSE2-NEXT:    pcmpgtb %xmm0, %xmm2
1108; SSE2-NEXT:    pand %xmm2, %xmm0
1109; SSE2-NEXT:    pandn %xmm1, %xmm2
1110; SSE2-NEXT:    por %xmm2, %xmm0
1111; SSE2-NEXT:    retq
1112;
1113; SSE41-LABEL: min_lt_v16i8:
1114; SSE41:       # BB#0:
1115; SSE41-NEXT:    pminsb %xmm1, %xmm0
1116; SSE41-NEXT:    retq
1117;
1118; SSE42-LABEL: min_lt_v16i8:
1119; SSE42:       # BB#0:
1120; SSE42-NEXT:    pminsb %xmm1, %xmm0
1121; SSE42-NEXT:    retq
1122;
1123; AVX-LABEL: min_lt_v16i8:
1124; AVX:       # BB#0:
1125; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1126; AVX-NEXT:    retq
1127  %1 = icmp slt <16 x i8> %a, %b
1128  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1129  ret <16 x i8> %2
1130}
1131
1132define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) {
1133; SSE2-LABEL: min_lt_v32i8:
1134; SSE2:       # BB#0:
1135; SSE2-NEXT:    movdqa %xmm3, %xmm4
1136; SSE2-NEXT:    pcmpgtb %xmm1, %xmm4
1137; SSE2-NEXT:    movdqa %xmm2, %xmm5
1138; SSE2-NEXT:    pcmpgtb %xmm0, %xmm5
1139; SSE2-NEXT:    pand %xmm5, %xmm0
1140; SSE2-NEXT:    pandn %xmm2, %xmm5
1141; SSE2-NEXT:    por %xmm5, %xmm0
1142; SSE2-NEXT:    pand %xmm4, %xmm1
1143; SSE2-NEXT:    pandn %xmm3, %xmm4
1144; SSE2-NEXT:    por %xmm4, %xmm1
1145; SSE2-NEXT:    retq
1146;
1147; SSE41-LABEL: min_lt_v32i8:
1148; SSE41:       # BB#0:
1149; SSE41-NEXT:    pminsb %xmm2, %xmm0
1150; SSE41-NEXT:    pminsb %xmm3, %xmm1
1151; SSE41-NEXT:    retq
1152;
1153; SSE42-LABEL: min_lt_v32i8:
1154; SSE42:       # BB#0:
1155; SSE42-NEXT:    pminsb %xmm2, %xmm0
1156; SSE42-NEXT:    pminsb %xmm3, %xmm1
1157; SSE42-NEXT:    retq
1158;
1159; AVX1-LABEL: min_lt_v32i8:
1160; AVX1:       # BB#0:
1161; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1162; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1163; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1164; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1165; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1166; AVX1-NEXT:    retq
1167;
1168; AVX2-LABEL: min_lt_v32i8:
1169; AVX2:       # BB#0:
1170; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1171; AVX2-NEXT:    retq
1172;
1173; AVX512-LABEL: min_lt_v32i8:
1174; AVX512:       # BB#0:
1175; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1176; AVX512-NEXT:    retq
1177  %1 = icmp slt <32 x i8> %a, %b
1178  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1179  ret <32 x i8> %2
1180}
1181
1182;
1183; Signed Minimum (LE)
1184;
1185
1186define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) {
1187; SSE2-LABEL: min_le_v2i64:
1188; SSE2:       # BB#0:
1189; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
1190; SSE2-NEXT:    movdqa %xmm1, %xmm3
1191; SSE2-NEXT:    pxor %xmm2, %xmm3
1192; SSE2-NEXT:    pxor %xmm0, %xmm2
1193; SSE2-NEXT:    movdqa %xmm2, %xmm4
1194; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
1195; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1196; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
1197; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
1198; SSE2-NEXT:    pand %xmm5, %xmm2
1199; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1200; SSE2-NEXT:    por %xmm2, %xmm3
1201; SSE2-NEXT:    pcmpeqd %xmm2, %xmm2
1202; SSE2-NEXT:    pxor %xmm3, %xmm2
1203; SSE2-NEXT:    pandn %xmm0, %xmm3
1204; SSE2-NEXT:    pandn %xmm1, %xmm2
1205; SSE2-NEXT:    por %xmm3, %xmm2
1206; SSE2-NEXT:    movdqa %xmm2, %xmm0
1207; SSE2-NEXT:    retq
1208;
1209; SSE41-LABEL: min_le_v2i64:
1210; SSE41:       # BB#0:
1211; SSE41-NEXT:    movdqa %xmm0, %xmm2
1212; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
1213; SSE41-NEXT:    movdqa %xmm1, %xmm3
1214; SSE41-NEXT:    pxor %xmm0, %xmm3
1215; SSE41-NEXT:    pxor %xmm2, %xmm0
1216; SSE41-NEXT:    movdqa %xmm0, %xmm4
1217; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
1218; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1219; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
1220; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
1221; SSE41-NEXT:    pand %xmm5, %xmm0
1222; SSE41-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1223; SSE41-NEXT:    por %xmm0, %xmm3
1224; SSE41-NEXT:    pcmpeqd %xmm0, %xmm0
1225; SSE41-NEXT:    pxor %xmm3, %xmm0
1226; SSE41-NEXT:    blendvpd %xmm2, %xmm1
1227; SSE41-NEXT:    movapd %xmm1, %xmm0
1228; SSE41-NEXT:    retq
1229;
1230; SSE42-LABEL: min_le_v2i64:
1231; SSE42:       # BB#0:
1232; SSE42-NEXT:    movdqa %xmm0, %xmm2
1233; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
1234; SSE42-NEXT:    pcmpeqd %xmm3, %xmm3
1235; SSE42-NEXT:    pxor %xmm3, %xmm0
1236; SSE42-NEXT:    blendvpd %xmm2, %xmm1
1237; SSE42-NEXT:    movapd %xmm1, %xmm0
1238; SSE42-NEXT:    retq
1239;
1240; AVX-LABEL: min_le_v2i64:
1241; AVX:       # BB#0:
1242; AVX-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
1243; AVX-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
1244; AVX-NEXT:    vpxor %xmm3, %xmm2, %xmm2
1245; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1246; AVX-NEXT:    retq
1247  %1 = icmp sle <2 x i64> %a, %b
1248  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
1249  ret <2 x i64> %2
1250}
1251
1252define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) {
1253; SSE2-LABEL: min_le_v4i64:
1254; SSE2:       # BB#0:
1255; SSE2-NEXT:    movdqa {{.*#+}} xmm7 = [2147483648,0,2147483648,0]
1256; SSE2-NEXT:    movdqa %xmm3, %xmm4
1257; SSE2-NEXT:    pxor %xmm7, %xmm4
1258; SSE2-NEXT:    movdqa %xmm1, %xmm5
1259; SSE2-NEXT:    pxor %xmm7, %xmm5
1260; SSE2-NEXT:    movdqa %xmm5, %xmm6
1261; SSE2-NEXT:    pcmpgtd %xmm4, %xmm6
1262; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm6[0,0,2,2]
1263; SSE2-NEXT:    pcmpeqd %xmm4, %xmm5
1264; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
1265; SSE2-NEXT:    pand %xmm8, %xmm4
1266; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm6[1,1,3,3]
1267; SSE2-NEXT:    por %xmm4, %xmm8
1268; SSE2-NEXT:    pcmpeqd %xmm4, %xmm4
1269; SSE2-NEXT:    movdqa %xmm8, %xmm9
1270; SSE2-NEXT:    pxor %xmm4, %xmm9
1271; SSE2-NEXT:    movdqa %xmm2, %xmm6
1272; SSE2-NEXT:    pxor %xmm7, %xmm6
1273; SSE2-NEXT:    pxor %xmm0, %xmm7
1274; SSE2-NEXT:    movdqa %xmm7, %xmm5
1275; SSE2-NEXT:    pcmpgtd %xmm6, %xmm5
1276; SSE2-NEXT:    pshufd {{.*#+}} xmm10 = xmm5[0,0,2,2]
1277; SSE2-NEXT:    pcmpeqd %xmm6, %xmm7
1278; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
1279; SSE2-NEXT:    pand %xmm10, %xmm6
1280; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
1281; SSE2-NEXT:    por %xmm6, %xmm5
1282; SSE2-NEXT:    pxor %xmm5, %xmm4
1283; SSE2-NEXT:    pandn %xmm0, %xmm5
1284; SSE2-NEXT:    pandn %xmm2, %xmm4
1285; SSE2-NEXT:    por %xmm5, %xmm4
1286; SSE2-NEXT:    pandn %xmm1, %xmm8
1287; SSE2-NEXT:    pandn %xmm3, %xmm9
1288; SSE2-NEXT:    por %xmm8, %xmm9
1289; SSE2-NEXT:    movdqa %xmm4, %xmm0
1290; SSE2-NEXT:    movdqa %xmm9, %xmm1
1291; SSE2-NEXT:    retq
1292;
1293; SSE41-LABEL: min_le_v4i64:
1294; SSE41:       # BB#0:
1295; SSE41-NEXT:    movdqa %xmm0, %xmm8
1296; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,0,2147483648,0]
1297; SSE41-NEXT:    movdqa %xmm3, %xmm5
1298; SSE41-NEXT:    pxor %xmm0, %xmm5
1299; SSE41-NEXT:    movdqa %xmm1, %xmm6
1300; SSE41-NEXT:    pxor %xmm0, %xmm6
1301; SSE41-NEXT:    movdqa %xmm6, %xmm7
1302; SSE41-NEXT:    pcmpgtd %xmm5, %xmm7
1303; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
1304; SSE41-NEXT:    pcmpeqd %xmm5, %xmm6
1305; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
1306; SSE41-NEXT:    pand %xmm4, %xmm6
1307; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
1308; SSE41-NEXT:    por %xmm6, %xmm5
1309; SSE41-NEXT:    pcmpeqd %xmm9, %xmm9
1310; SSE41-NEXT:    pxor %xmm9, %xmm5
1311; SSE41-NEXT:    movdqa %xmm2, %xmm6
1312; SSE41-NEXT:    pxor %xmm0, %xmm6
1313; SSE41-NEXT:    pxor %xmm8, %xmm0
1314; SSE41-NEXT:    movdqa %xmm0, %xmm7
1315; SSE41-NEXT:    pcmpgtd %xmm6, %xmm7
1316; SSE41-NEXT:    pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
1317; SSE41-NEXT:    pcmpeqd %xmm6, %xmm0
1318; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
1319; SSE41-NEXT:    pand %xmm4, %xmm6
1320; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm7[1,1,3,3]
1321; SSE41-NEXT:    por %xmm6, %xmm0
1322; SSE41-NEXT:    pxor %xmm9, %xmm0
1323; SSE41-NEXT:    blendvpd %xmm8, %xmm2
1324; SSE41-NEXT:    movdqa %xmm5, %xmm0
1325; SSE41-NEXT:    blendvpd %xmm1, %xmm3
1326; SSE41-NEXT:    movapd %xmm2, %xmm0
1327; SSE41-NEXT:    movapd %xmm3, %xmm1
1328; SSE41-NEXT:    retq
1329;
1330; SSE42-LABEL: min_le_v4i64:
1331; SSE42:       # BB#0:
1332; SSE42-NEXT:    movdqa %xmm0, %xmm4
1333; SSE42-NEXT:    movdqa %xmm1, %xmm5
1334; SSE42-NEXT:    pcmpgtq %xmm3, %xmm5
1335; SSE42-NEXT:    pcmpeqd %xmm6, %xmm6
1336; SSE42-NEXT:    pxor %xmm6, %xmm5
1337; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
1338; SSE42-NEXT:    pxor %xmm6, %xmm0
1339; SSE42-NEXT:    blendvpd %xmm4, %xmm2
1340; SSE42-NEXT:    movdqa %xmm5, %xmm0
1341; SSE42-NEXT:    blendvpd %xmm1, %xmm3
1342; SSE42-NEXT:    movapd %xmm2, %xmm0
1343; SSE42-NEXT:    movapd %xmm3, %xmm1
1344; SSE42-NEXT:    retq
1345;
1346; AVX1-LABEL: min_le_v4i64:
1347; AVX1:       # BB#0:
1348; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1349; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1350; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
1351; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm3, %xmm3
1352; AVX1-NEXT:    vpxor %xmm3, %xmm2, %xmm2
1353; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm4
1354; AVX1-NEXT:    vpxor %xmm3, %xmm4, %xmm3
1355; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
1356; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1357; AVX1-NEXT:    retq
1358;
1359; AVX2-LABEL: min_le_v4i64:
1360; AVX2:       # BB#0:
1361; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
1362; AVX2-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
1363; AVX2-NEXT:    vpxor %ymm3, %ymm2, %ymm2
1364; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1365; AVX2-NEXT:    retq
1366;
1367; AVX512-LABEL: min_le_v4i64:
1368; AVX512:       # BB#0:
1369; AVX512-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
1370; AVX512-NEXT:    vpcmpeqd %ymm3, %ymm3, %ymm3
1371; AVX512-NEXT:    vpxor %ymm3, %ymm2, %ymm2
1372; AVX512-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1373; AVX512-NEXT:    retq
1374  %1 = icmp sle <4 x i64> %a, %b
1375  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
1376  ret <4 x i64> %2
1377}
1378
1379define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) {
1380; SSE2-LABEL: min_le_v4i32:
1381; SSE2:       # BB#0:
1382; SSE2-NEXT:    movdqa %xmm0, %xmm2
1383; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
1384; SSE2-NEXT:    pcmpeqd %xmm3, %xmm3
1385; SSE2-NEXT:    pxor %xmm2, %xmm3
1386; SSE2-NEXT:    pandn %xmm0, %xmm2
1387; SSE2-NEXT:    pandn %xmm1, %xmm3
1388; SSE2-NEXT:    por %xmm3, %xmm2
1389; SSE2-NEXT:    movdqa %xmm2, %xmm0
1390; SSE2-NEXT:    retq
1391;
1392; SSE41-LABEL: min_le_v4i32:
1393; SSE41:       # BB#0:
1394; SSE41-NEXT:    pminsd %xmm1, %xmm0
1395; SSE41-NEXT:    retq
1396;
1397; SSE42-LABEL: min_le_v4i32:
1398; SSE42:       # BB#0:
1399; SSE42-NEXT:    pminsd %xmm1, %xmm0
1400; SSE42-NEXT:    retq
1401;
1402; AVX-LABEL: min_le_v4i32:
1403; AVX:       # BB#0:
1404; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1405; AVX-NEXT:    retq
1406  %1 = icmp sle <4 x i32> %a, %b
1407  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1408  ret <4 x i32> %2
1409}
1410
1411define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) {
1412; SSE2-LABEL: min_le_v8i32:
1413; SSE2:       # BB#0:
1414; SSE2-NEXT:    movdqa %xmm1, %xmm6
1415; SSE2-NEXT:    pcmpgtd %xmm3, %xmm6
1416; SSE2-NEXT:    pcmpeqd %xmm7, %xmm7
1417; SSE2-NEXT:    movdqa %xmm6, %xmm4
1418; SSE2-NEXT:    pxor %xmm7, %xmm4
1419; SSE2-NEXT:    movdqa %xmm0, %xmm5
1420; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
1421; SSE2-NEXT:    pxor %xmm5, %xmm7
1422; SSE2-NEXT:    pandn %xmm0, %xmm5
1423; SSE2-NEXT:    pandn %xmm2, %xmm7
1424; SSE2-NEXT:    por %xmm7, %xmm5
1425; SSE2-NEXT:    pandn %xmm1, %xmm6
1426; SSE2-NEXT:    pandn %xmm3, %xmm4
1427; SSE2-NEXT:    por %xmm6, %xmm4
1428; SSE2-NEXT:    movdqa %xmm5, %xmm0
1429; SSE2-NEXT:    movdqa %xmm4, %xmm1
1430; SSE2-NEXT:    retq
1431;
1432; SSE41-LABEL: min_le_v8i32:
1433; SSE41:       # BB#0:
1434; SSE41-NEXT:    pminsd %xmm2, %xmm0
1435; SSE41-NEXT:    pminsd %xmm3, %xmm1
1436; SSE41-NEXT:    retq
1437;
1438; SSE42-LABEL: min_le_v8i32:
1439; SSE42:       # BB#0:
1440; SSE42-NEXT:    pminsd %xmm2, %xmm0
1441; SSE42-NEXT:    pminsd %xmm3, %xmm1
1442; SSE42-NEXT:    retq
1443;
1444; AVX1-LABEL: min_le_v8i32:
1445; AVX1:       # BB#0:
1446; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1447; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1448; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1449; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1450; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1451; AVX1-NEXT:    retq
1452;
1453; AVX2-LABEL: min_le_v8i32:
1454; AVX2:       # BB#0:
1455; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1456; AVX2-NEXT:    retq
1457;
1458; AVX512-LABEL: min_le_v8i32:
1459; AVX512:       # BB#0:
1460; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1461; AVX512-NEXT:    retq
1462  %1 = icmp sle <8 x i32> %a, %b
1463  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1464  ret <8 x i32> %2
1465}
1466
1467define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) {
1468; SSE-LABEL: min_le_v8i16:
1469; SSE:       # BB#0:
1470; SSE-NEXT:    pminsw %xmm1, %xmm0
1471; SSE-NEXT:    retq
1472;
1473; AVX-LABEL: min_le_v8i16:
1474; AVX:       # BB#0:
1475; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1476; AVX-NEXT:    retq
1477  %1 = icmp sle <8 x i16> %a, %b
1478  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1479  ret <8 x i16> %2
1480}
1481
1482define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) {
1483; SSE-LABEL: min_le_v16i16:
1484; SSE:       # BB#0:
1485; SSE-NEXT:    pminsw %xmm2, %xmm0
1486; SSE-NEXT:    pminsw %xmm3, %xmm1
1487; SSE-NEXT:    retq
1488;
1489; AVX1-LABEL: min_le_v16i16:
1490; AVX1:       # BB#0:
1491; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1492; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1493; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1494; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1495; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1496; AVX1-NEXT:    retq
1497;
1498; AVX2-LABEL: min_le_v16i16:
1499; AVX2:       # BB#0:
1500; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1501; AVX2-NEXT:    retq
1502;
1503; AVX512-LABEL: min_le_v16i16:
1504; AVX512:       # BB#0:
1505; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1506; AVX512-NEXT:    retq
1507  %1 = icmp sle <16 x i16> %a, %b
1508  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1509  ret <16 x i16> %2
1510}
1511
1512define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) {
1513; SSE2-LABEL: min_le_v16i8:
1514; SSE2:       # BB#0:
1515; SSE2-NEXT:    movdqa %xmm0, %xmm2
1516; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
1517; SSE2-NEXT:    pcmpeqd %xmm3, %xmm3
1518; SSE2-NEXT:    pxor %xmm2, %xmm3
1519; SSE2-NEXT:    pandn %xmm0, %xmm2
1520; SSE2-NEXT:    pandn %xmm1, %xmm3
1521; SSE2-NEXT:    por %xmm3, %xmm2
1522; SSE2-NEXT:    movdqa %xmm2, %xmm0
1523; SSE2-NEXT:    retq
1524;
1525; SSE41-LABEL: min_le_v16i8:
1526; SSE41:       # BB#0:
1527; SSE41-NEXT:    pminsb %xmm1, %xmm0
1528; SSE41-NEXT:    retq
1529;
1530; SSE42-LABEL: min_le_v16i8:
1531; SSE42:       # BB#0:
1532; SSE42-NEXT:    pminsb %xmm1, %xmm0
1533; SSE42-NEXT:    retq
1534;
1535; AVX-LABEL: min_le_v16i8:
1536; AVX:       # BB#0:
1537; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1538; AVX-NEXT:    retq
1539  %1 = icmp sle <16 x i8> %a, %b
1540  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1541  ret <16 x i8> %2
1542}
1543
1544define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) {
1545; SSE2-LABEL: min_le_v32i8:
1546; SSE2:       # BB#0:
1547; SSE2-NEXT:    movdqa %xmm1, %xmm6
1548; SSE2-NEXT:    pcmpgtb %xmm3, %xmm6
1549; SSE2-NEXT:    pcmpeqd %xmm7, %xmm7
1550; SSE2-NEXT:    movdqa %xmm6, %xmm4
1551; SSE2-NEXT:    pxor %xmm7, %xmm4
1552; SSE2-NEXT:    movdqa %xmm0, %xmm5
1553; SSE2-NEXT:    pcmpgtb %xmm2, %xmm5
1554; SSE2-NEXT:    pxor %xmm5, %xmm7
1555; SSE2-NEXT:    pandn %xmm0, %xmm5
1556; SSE2-NEXT:    pandn %xmm2, %xmm7
1557; SSE2-NEXT:    por %xmm7, %xmm5
1558; SSE2-NEXT:    pandn %xmm1, %xmm6
1559; SSE2-NEXT:    pandn %xmm3, %xmm4
1560; SSE2-NEXT:    por %xmm6, %xmm4
1561; SSE2-NEXT:    movdqa %xmm5, %xmm0
1562; SSE2-NEXT:    movdqa %xmm4, %xmm1
1563; SSE2-NEXT:    retq
1564;
1565; SSE41-LABEL: min_le_v32i8:
1566; SSE41:       # BB#0:
1567; SSE41-NEXT:    pminsb %xmm2, %xmm0
1568; SSE41-NEXT:    pminsb %xmm3, %xmm1
1569; SSE41-NEXT:    retq
1570;
1571; SSE42-LABEL: min_le_v32i8:
1572; SSE42:       # BB#0:
1573; SSE42-NEXT:    pminsb %xmm2, %xmm0
1574; SSE42-NEXT:    pminsb %xmm3, %xmm1
1575; SSE42-NEXT:    retq
1576;
1577; AVX1-LABEL: min_le_v32i8:
1578; AVX1:       # BB#0:
1579; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1580; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1581; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1582; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1583; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1584; AVX1-NEXT:    retq
1585;
1586; AVX2-LABEL: min_le_v32i8:
1587; AVX2:       # BB#0:
1588; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1589; AVX2-NEXT:    retq
1590;
1591; AVX512-LABEL: min_le_v32i8:
1592; AVX512:       # BB#0:
1593; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1594; AVX512-NEXT:    retq
1595  %1 = icmp sle <32 x i8> %a, %b
1596  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1597  ret <32 x i8> %2
1598}
1599
1600;
1601; Constant Folding
1602;
1603
1604define <2 x i64> @max_gt_v2i64c() {
1605; SSE-LABEL: max_gt_v2i64c:
1606; SSE:       # BB#0:
1607; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1608; SSE-NEXT:    retq
1609;
1610; AVX-LABEL: max_gt_v2i64c:
1611; AVX:       # BB#0:
1612; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1613; AVX-NEXT:    retq
1614  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1615  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1616  %3 = icmp sgt <2 x i64> %1, %2
1617  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1618  ret <2 x i64> %4
1619}
1620
1621define <4 x i64> @max_gt_v4i64c() {
1622; SSE-LABEL: max_gt_v4i64c:
1623; SSE:       # BB#0:
1624; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1625; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1626; SSE-NEXT:    retq
1627;
1628; AVX-LABEL: max_gt_v4i64c:
1629; AVX:       # BB#0:
1630; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1631; AVX-NEXT:    retq
1632  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1633  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1634  %3 = icmp sgt <4 x i64> %1, %2
1635  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1636  ret <4 x i64> %4
1637}
1638
1639define <4 x i32> @max_gt_v4i32c() {
1640; SSE-LABEL: max_gt_v4i32c:
1641; SSE:       # BB#0:
1642; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1643; SSE-NEXT:    retq
1644;
1645; AVX-LABEL: max_gt_v4i32c:
1646; AVX:       # BB#0:
1647; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1648; AVX-NEXT:    retq
1649  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1650  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1651  %3 = icmp sgt <4 x i32> %1, %2
1652  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1653  ret <4 x i32> %4
1654}
1655
1656define <8 x i32> @max_gt_v8i32c() {
1657; SSE-LABEL: max_gt_v8i32c:
1658; SSE:       # BB#0:
1659; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1660; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1661; SSE-NEXT:    retq
1662;
1663; AVX-LABEL: max_gt_v8i32c:
1664; AVX:       # BB#0:
1665; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1666; AVX-NEXT:    retq
1667  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1668  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1669  %3 = icmp sgt <8 x i32> %1, %2
1670  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1671  ret <8 x i32> %4
1672}
1673
1674define <8 x i16> @max_gt_v8i16c() {
1675; SSE-LABEL: max_gt_v8i16c:
1676; SSE:       # BB#0:
1677; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1678; SSE-NEXT:    retq
1679;
1680; AVX-LABEL: max_gt_v8i16c:
1681; AVX:       # BB#0:
1682; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1683; AVX-NEXT:    retq
1684  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1685  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1686  %3 = icmp sgt <8 x i16> %1, %2
1687  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1688  ret <8 x i16> %4
1689}
1690
1691define <16 x i16> @max_gt_v16i16c() {
1692; SSE-LABEL: max_gt_v16i16c:
1693; SSE:       # BB#0:
1694; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1695; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1696; SSE-NEXT:    retq
1697;
1698; AVX-LABEL: max_gt_v16i16c:
1699; AVX:       # BB#0:
1700; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1701; AVX-NEXT:    retq
1702  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1703  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1704  %3 = icmp sgt <16 x i16> %1, %2
1705  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1706  ret <16 x i16> %4
1707}
1708
1709define <16 x i8> @max_gt_v16i8c() {
1710; SSE-LABEL: max_gt_v16i8c:
1711; SSE:       # BB#0:
1712; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1713; SSE-NEXT:    retq
1714;
1715; AVX-LABEL: max_gt_v16i8c:
1716; AVX:       # BB#0:
1717; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1718; AVX-NEXT:    retq
1719  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1720  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1721  %3 = icmp sgt <16 x i8> %1, %2
1722  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1723  ret <16 x i8> %4
1724}
1725
1726define <2 x i64> @max_ge_v2i64c() {
1727; SSE-LABEL: max_ge_v2i64c:
1728; SSE:       # BB#0:
1729; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1730; SSE-NEXT:    retq
1731;
1732; AVX-LABEL: max_ge_v2i64c:
1733; AVX:       # BB#0:
1734; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1735; AVX-NEXT:    retq
1736  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1737  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1738  %3 = icmp sge <2 x i64> %1, %2
1739  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1740  ret <2 x i64> %4
1741}
1742
1743define <4 x i64> @max_ge_v4i64c() {
1744; SSE-LABEL: max_ge_v4i64c:
1745; SSE:       # BB#0:
1746; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1747; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1748; SSE-NEXT:    retq
1749;
1750; AVX-LABEL: max_ge_v4i64c:
1751; AVX:       # BB#0:
1752; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1753; AVX-NEXT:    retq
1754  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1755  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1756  %3 = icmp sge <4 x i64> %1, %2
1757  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1758  ret <4 x i64> %4
1759}
1760
1761define <4 x i32> @max_ge_v4i32c() {
1762; SSE-LABEL: max_ge_v4i32c:
1763; SSE:       # BB#0:
1764; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1765; SSE-NEXT:    retq
1766;
1767; AVX-LABEL: max_ge_v4i32c:
1768; AVX:       # BB#0:
1769; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1770; AVX-NEXT:    retq
1771  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1772  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1773  %3 = icmp sge <4 x i32> %1, %2
1774  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1775  ret <4 x i32> %4
1776}
1777
1778define <8 x i32> @max_ge_v8i32c() {
1779; SSE-LABEL: max_ge_v8i32c:
1780; SSE:       # BB#0:
1781; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1782; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1783; SSE-NEXT:    retq
1784;
1785; AVX-LABEL: max_ge_v8i32c:
1786; AVX:       # BB#0:
1787; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1788; AVX-NEXT:    retq
1789  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1790  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1791  %3 = icmp sge <8 x i32> %1, %2
1792  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1793  ret <8 x i32> %4
1794}
1795
1796define <8 x i16> @max_ge_v8i16c() {
1797; SSE-LABEL: max_ge_v8i16c:
1798; SSE:       # BB#0:
1799; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1800; SSE-NEXT:    retq
1801;
1802; AVX-LABEL: max_ge_v8i16c:
1803; AVX:       # BB#0:
1804; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1805; AVX-NEXT:    retq
1806  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1807  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1808  %3 = icmp sge <8 x i16> %1, %2
1809  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1810  ret <8 x i16> %4
1811}
1812
1813define <16 x i16> @max_ge_v16i16c() {
1814; SSE-LABEL: max_ge_v16i16c:
1815; SSE:       # BB#0:
1816; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1817; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1818; SSE-NEXT:    retq
1819;
1820; AVX-LABEL: max_ge_v16i16c:
1821; AVX:       # BB#0:
1822; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1823; AVX-NEXT:    retq
1824  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1825  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1826  %3 = icmp sge <16 x i16> %1, %2
1827  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1828  ret <16 x i16> %4
1829}
1830
1831define <16 x i8> @max_ge_v16i8c() {
1832; SSE-LABEL: max_ge_v16i8c:
1833; SSE:       # BB#0:
1834; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1835; SSE-NEXT:    retq
1836;
1837; AVX-LABEL: max_ge_v16i8c:
1838; AVX:       # BB#0:
1839; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1840; AVX-NEXT:    retq
1841  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1842  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1843  %3 = icmp sge <16 x i8> %1, %2
1844  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1845  ret <16 x i8> %4
1846}
1847
1848define <2 x i64> @min_lt_v2i64c() {
1849; SSE-LABEL: min_lt_v2i64c:
1850; SSE:       # BB#0:
1851; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1852; SSE-NEXT:    retq
1853;
1854; AVX-LABEL: min_lt_v2i64c:
1855; AVX:       # BB#0:
1856; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1857; AVX-NEXT:    retq
1858  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1859  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1860  %3 = icmp slt <2 x i64> %1, %2
1861  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1862  ret <2 x i64> %4
1863}
1864
1865define <4 x i64> @min_lt_v4i64c() {
1866; SSE-LABEL: min_lt_v4i64c:
1867; SSE:       # BB#0:
1868; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1869; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1870; SSE-NEXT:    retq
1871;
1872; AVX-LABEL: min_lt_v4i64c:
1873; AVX:       # BB#0:
1874; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1875; AVX-NEXT:    retq
1876  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1877  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1878  %3 = icmp slt <4 x i64> %1, %2
1879  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1880  ret <4 x i64> %4
1881}
1882
1883define <4 x i32> @min_lt_v4i32c() {
1884; SSE-LABEL: min_lt_v4i32c:
1885; SSE:       # BB#0:
1886; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1887; SSE-NEXT:    retq
1888;
1889; AVX-LABEL: min_lt_v4i32c:
1890; AVX:       # BB#0:
1891; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1892; AVX-NEXT:    retq
1893  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1894  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1895  %3 = icmp slt <4 x i32> %1, %2
1896  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1897  ret <4 x i32> %4
1898}
1899
1900define <8 x i32> @min_lt_v8i32c() {
1901; SSE-LABEL: min_lt_v8i32c:
1902; SSE:       # BB#0:
1903; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1904; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
1905; SSE-NEXT:    retq
1906;
1907; AVX-LABEL: min_lt_v8i32c:
1908; AVX:       # BB#0:
1909; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1910; AVX-NEXT:    retq
1911  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1912  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1913  %3 = icmp slt <8 x i32> %1, %2
1914  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1915  ret <8 x i32> %4
1916}
1917
1918define <8 x i16> @min_lt_v8i16c() {
1919; SSE-LABEL: min_lt_v8i16c:
1920; SSE:       # BB#0:
1921; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1922; SSE-NEXT:    retq
1923;
1924; AVX-LABEL: min_lt_v8i16c:
1925; AVX:       # BB#0:
1926; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1927; AVX-NEXT:    retq
1928  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1929  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1930  %3 = icmp slt <8 x i16> %1, %2
1931  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1932  ret <8 x i16> %4
1933}
1934
1935define <16 x i16> @min_lt_v16i16c() {
1936; SSE-LABEL: min_lt_v16i16c:
1937; SSE:       # BB#0:
1938; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
1939; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
1940; SSE-NEXT:    retq
1941;
1942; AVX-LABEL: min_lt_v16i16c:
1943; AVX:       # BB#0:
1944; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
1945; AVX-NEXT:    retq
1946  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1947  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1948  %3 = icmp slt <16 x i16> %1, %2
1949  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1950  ret <16 x i16> %4
1951}
1952
1953define <16 x i8> @min_lt_v16i8c() {
1954; SSE-LABEL: min_lt_v16i8c:
1955; SSE:       # BB#0:
1956; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1957; SSE-NEXT:    retq
1958;
1959; AVX-LABEL: min_lt_v16i8c:
1960; AVX:       # BB#0:
1961; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1962; AVX-NEXT:    retq
1963  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1964  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1965  %3 = icmp slt <16 x i8> %1, %2
1966  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1967  ret <16 x i8> %4
1968}
1969
1970define <2 x i64> @min_le_v2i64c() {
1971; SSE-LABEL: min_le_v2i64c:
1972; SSE:       # BB#0:
1973; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1974; SSE-NEXT:    retq
1975;
1976; AVX-LABEL: min_le_v2i64c:
1977; AVX:       # BB#0:
1978; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1979; AVX-NEXT:    retq
1980  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1981  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1982  %3 = icmp sle <2 x i64> %1, %2
1983  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1984  ret <2 x i64> %4
1985}
1986
1987define <4 x i64> @min_le_v4i64c() {
1988; SSE-LABEL: min_le_v4i64c:
1989; SSE:       # BB#0:
1990; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1991; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1992; SSE-NEXT:    retq
1993;
1994; AVX-LABEL: min_le_v4i64c:
1995; AVX:       # BB#0:
1996; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1997; AVX-NEXT:    retq
1998  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1999  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
2000  %3 = icmp sle <4 x i64> %1, %2
2001  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
2002  ret <4 x i64> %4
2003}
2004
2005define <4 x i32> @min_le_v4i32c() {
2006; SSE-LABEL: min_le_v4i32c:
2007; SSE:       # BB#0:
2008; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
2009; SSE-NEXT:    retq
2010;
2011; AVX-LABEL: min_le_v4i32c:
2012; AVX:       # BB#0:
2013; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
2014; AVX-NEXT:    retq
2015  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
2016  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
2017  %3 = icmp sle <4 x i32> %1, %2
2018  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
2019  ret <4 x i32> %4
2020}
2021
2022define <8 x i32> @min_le_v8i32c() {
2023; SSE-LABEL: min_le_v8i32c:
2024; SSE:       # BB#0:
2025; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
2026; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
2027; SSE-NEXT:    retq
2028;
2029; AVX-LABEL: min_le_v8i32c:
2030; AVX:       # BB#0:
2031; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
2032; AVX-NEXT:    retq
2033  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
2034  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
2035  %3 = icmp sle <8 x i32> %1, %2
2036  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
2037  ret <8 x i32> %4
2038}
2039
2040define <8 x i16> @min_le_v8i16c() {
2041; SSE-LABEL: min_le_v8i16c:
2042; SSE:       # BB#0:
2043; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2044; SSE-NEXT:    retq
2045;
2046; AVX-LABEL: min_le_v8i16c:
2047; AVX:       # BB#0:
2048; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2049; AVX-NEXT:    retq
2050  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
2051  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
2052  %3 = icmp sle <8 x i16> %1, %2
2053  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
2054  ret <8 x i16> %4
2055}
2056
2057define <16 x i16> @min_le_v16i16c() {
2058; SSE-LABEL: min_le_v16i16c:
2059; SSE:       # BB#0:
2060; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
2061; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
2062; SSE-NEXT:    retq
2063;
2064; AVX-LABEL: min_le_v16i16c:
2065; AVX:       # BB#0:
2066; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2067; AVX-NEXT:    retq
2068  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
2069  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
2070  %3 = icmp sle <16 x i16> %1, %2
2071  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
2072  ret <16 x i16> %4
2073}
2074
2075define <16 x i8> @min_le_v16i8c() {
2076; SSE-LABEL: min_le_v16i8c:
2077; SSE:       # BB#0:
2078; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2079; SSE-NEXT:    retq
2080;
2081; AVX-LABEL: min_le_v16i8c:
2082; AVX:       # BB#0:
2083; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2084; AVX-NEXT:    retq
2085  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
2086  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
2087  %3 = icmp sle <16 x i8> %1, %2
2088  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
2089  ret <16 x i8> %4
2090}
2091