1; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s 2define i32 @ashr(i32 %a, i32 %b) nounwind { 3 %1 = ashr i32 %a, %b 4 ret i32 %1 5} 6; CHECK-LABEL: ashr: 7; CHECK-NEXT: ashr r0, r0, r1 8 9define i32 @ashri1(i32 %a) nounwind { 10 %1 = ashr i32 %a, 24 11 ret i32 %1 12} 13; CHECK-LABEL: ashri1: 14; CHECK-NEXT: ashr r0, r0, 24 15 16define i32 @ashri2(i32 %a) nounwind { 17 %1 = ashr i32 %a, 31 18 ret i32 %1 19} 20; CHECK-LABEL: ashri2: 21; CHECK-NEXT: ashr r0, r0, 32 22 23define i32 @f1(i32 %a) nounwind nounwind { 24 %1 = icmp slt i32 %a, 0 25 br i1 %1, label %less, label %not_less 26less: 27 ret i32 10 28not_less: 29 ret i32 17 30} 31; CHECK-LABEL: f1: 32; CHECK-NEXT: ashr r0, r0, 32 33; CHECK-NEXT: bt r0 34 35define i32 @f2(i32 %a) nounwind { 36 %1 = icmp sge i32 %a, 0 37 br i1 %1, label %greater, label %not_greater 38greater: 39 ret i32 10 40not_greater: 41 ret i32 17 42} 43; CHECK-LABEL: f2: 44; CHECK-NEXT: ashr r0, r0, 32 45; CHECK-NEXT: bt r0 46 47define i32 @f3(i32 %a) nounwind { 48 %1 = icmp slt i32 %a, 0 49 %2 = select i1 %1, i32 10, i32 17 50 ret i32 %2 51} 52; CHECK-LABEL: f3: 53; CHECK-NEXT: ashr r0, r0, 32 54; CHECK-NEXT: bt r0 55; CHECK-NEXT: ldc r0, 17 56; CHECK: ldc r0, 10 57 58define i32 @f4(i32 %a) nounwind { 59 %1 = icmp sge i32 %a, 0 60 %2 = select i1 %1, i32 10, i32 17 61 ret i32 %2 62} 63; CHECK-LABEL: f4: 64; CHECK-NEXT: ashr r0, r0, 32 65; CHECK-NEXT: bt r0 66; CHECK-NEXT: ldc r0, 10 67; CHECK: ldc r0, 17 68 69define i32 @f5(i32 %a) nounwind { 70 %1 = icmp sge i32 %a, 0 71 %2 = zext i1 %1 to i32 72 ret i32 %2 73} 74; CHECK-LABEL: f5: 75; CHECK-NEXT: ashr r0, r0, 32 76; CHECK-NEXT: eq r0, r0, 0 77