1; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck %s 2 3; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads 4; feeding a phi that zext's each loaded value. 5define i32 @test_free_zext(i32* %ptr, i32* %ptr2, i32 %c) { 6; CHECK-LABEL: @test_free_zext( 7bb1: 8; CHECK-LABEL: bb1: 9; CHECK: %[[T1:.*]] = load 10; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 11 %load1 = load i32, i32* %ptr, align 4 12 %cmp = icmp ne i32 %c, 0 13 br i1 %cmp, label %bb2, label %bb3 14bb2: 15; CHECK-LABEL: bb2: 16; CHECK: %[[T2:.*]] = load 17; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535 18 %load2 = load i32, i32* %ptr2, align 4 19 br label %bb3 20bb3: 21; CHECK-LABEL: bb3: 22; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2]], %bb2 ] 23 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %bb2 ] 24 %and = and i32 %phi, 65535 25 ret i32 %and 26} 27 28; Test for CodeGenPrepare::optimizeLoadExt(): exercise all opcode 29; cases of active bit calculation. 30define i32 @test_free_zext2(i32* %ptr, i16* %dst16, i32* %dst32, i32 %c) { 31; CHECK-LABEL: @test_free_zext2( 32bb1: 33; CHECK-LABEL: bb1: 34; CHECK: %[[T1:.*]] = load 35; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 36 %load1 = load i32, i32* %ptr, align 4 37 %cmp = icmp ne i32 %c, 0 38 br i1 %cmp, label %bb2, label %bb4 39bb2: 40; CHECK-LABEL: bb2: 41 %trunc = trunc i32 %load1 to i16 42 store i16 %trunc, i16* %dst16, align 2 43 br i1 %cmp, label %bb3, label %bb4 44bb3: 45; CHECK-LABEL: bb3: 46 %shl = shl i32 %load1, 16 47 store i32 %shl, i32* %dst32, align 4 48 br label %bb4 49bb4: 50; CHECK-LABEL: bb4: 51; CHECK-NOT: and 52; CHECK: ret i32 %[[A1]] 53 %and = and i32 %load1, 65535 54 ret i32 %and 55} 56 57; Test for CodeGenPrepare::optimizeLoadExt(): check case of zext-able 58; load feeding a phi in the same block. 59define void @test_free_zext3(i32* %ptr, i32* %ptr2, i32* %dst, i64* %c) { 60; CHECK-LABEL: @test_free_zext3( 61bb1: 62; CHECK-LABEL: bb1: 63; CHECK: %[[T1:.*]] = load 64; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 65 %load1 = load i32, i32* %ptr, align 4 66 br label %loop 67loop: 68; CHECK-LABEL: loop: 69; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2]], %loop ] 70 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ] 71 %and = and i32 %phi, 65535 72 store i32 %and, i32* %dst, align 4 73 %idx = load volatile i64, i64* %c, align 4 74 %addr = getelementptr inbounds i32, i32* %ptr2, i64 %idx 75; CHECK: %[[T2:.*]] = load i32 76; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535 77 %load2 = load i32, i32* %addr, align 4 78 %cmp = icmp ne i64 %idx, 0 79 br i1 %cmp, label %loop, label %end 80end: 81 ret void 82} 83