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1{
2 "enums": {
3  "COMMAND__SAIC": {
4   "entries": [
5    {"name": "INCREMENT", "value": 0},
6    {"name": "NO_INCREMENT", "value": 1}
7   ]
8  },
9  "COMMAND__SAS": {
10   "entries": [
11    {"name": "MEMORY", "value": 0},
12    {"name": "REGISTER", "value": 1}
13   ]
14  },
15  "COMMAND__SRC_SWAP": {
16   "entries": [
17    {"name": "NONE", "value": 0},
18    {"name": "8_IN_16", "value": 1},
19    {"name": "8_IN_32", "value": 2},
20    {"name": "8_IN_64", "value": 3}
21   ]
22  },
23  "CONTROL__DST_SEL": {
24   "entries": [
25    {"name": "MEM_MAPPED_REGISTER", "value": 0},
26    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27    {"name": "TC_L2", "value": 2},
28    {"name": "GDS", "value": 3},
29    {"name": "RESERVED", "value": 4}
30   ]
31  },
32  "CONTROL__DST_SEL_cik": {
33   "entries": [
34    {"name": "MEM_MAPPED_REGISTER", "value": 0},
35    {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36    {"name": "TC_L2", "value": 2},
37    {"name": "GDS", "value": 3},
38    {"name": "RESERVED", "value": 4},
39    {"name": "MEM", "value": 5}
40   ]
41  },
42  "CONTROL__ENGINE_SEL": {
43   "entries": [
44    {"name": "ME", "value": 0},
45    {"name": "PFP", "value": 1},
46    {"name": "CE", "value": 2},
47    {"name": "DE", "value": 3}
48   ]
49  },
50  "CP_DMA_WORD1__DST_SEL": {
51   "entries": [
52    {"name": "DST_ADDR", "value": 0},
53    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
54   ]
55  },
56  "CP_DMA_WORD1__DST_SEL_cik": {
57   "entries": [
58    {"name": "DST_ADDR", "value": 0},
59    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
60    {"name": "DST_ADDR_TC_L2", "value": 3}
61   ]
62  },
63  "CP_DMA_WORD1__DST_SEL_gfx9": {
64   "entries": [
65    {"name": "DST_ADDR", "value": 0},
66    {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67    {"name": "NOWHERE", "value": 2},
68    {"name": "DST_ADDR_TC_L2", "value": 3}
69   ]
70  },
71  "CP_DMA_WORD1__ENGINE": {
72   "entries": [
73    {"name": "ME", "value": 0},
74    {"name": "PFP", "value": 1}
75   ]
76  },
77  "CP_DMA_WORD1__SRC_SEL": {
78   "entries": [
79    {"name": "SRC_ADDR", "value": 0},
80    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
81    {"name": "DATA", "value": 2}
82   ]
83  },
84  "CP_DMA_WORD1__SRC_SEL_cik": {
85   "entries": [
86    {"name": "SRC_ADDR", "value": 0},
87    {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
88    {"name": "DATA", "value": 2},
89    {"name": "SRC_ADDR_TC_L2", "value": 3}
90   ]
91  },
92  "GCR_GL1_RANGE": {
93   "entries": [
94    {"name": "GL1_ALL", "value": 0},
95    {"name": "GL1_RANGE", "value": 2},
96    {"name": "GL1_FIRST_LAST", "value": 3}
97   ]
98  },
99  "GCR_GL2_RANGE": {
100   "entries": [
101    {"name": "GL2_ALL", "value": 0},
102    {"name": "GL2_VOL", "value": 1},
103    {"name": "GL2_RANGE", "value": 2},
104    {"name": "GL2_FIRST_LAST", "value": 3}
105   ]
106  },
107  "GCR_GLI_INV": {
108   "entries": [
109    {"name": "GLI_NOP", "value": 0},
110    {"name": "GLI_ALL", "value": 1},
111    {"name": "GLI_RANGE", "value": 2},
112    {"name": "GLI_FIRST_LAST", "value": 3}
113   ]
114  },
115  "GCR_SEQ": {
116   "entries": [
117    {"name": "SEQ_PARALLEL", "value": 0},
118    {"name": "SEQ_FORWARD", "value": 1},
119    {"name": "SEQ_REVERSE", "value": 2}
120   ]
121  }
122 },
123 "register_mappings": [
124  {
125   "chips": ["gfx6", "gfx7", "gfx8", "gfx81"],
126   "map": {"at": 1044, "to": "pkt3"},
127   "name": "COMMAND",
128   "type_ref": "COMMAND"
129  },
130  {
131   "chips": ["gfx9", "gfx10", "gfx103"],
132   "map": {"at": 1044, "to": "pkt3"},
133   "name": "COMMAND",
134   "type_ref": "COMMAND_gfx9"
135  },
136  {
137   "chips": ["gfx6"],
138   "map": {"at": 880, "to": "pkt3"},
139   "name": "CONTROL",
140   "type_ref": "CONTROL"
141  },
142  {
143   "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
144   "map": {"at": 880, "to": "pkt3"},
145   "name": "CONTROL",
146   "type_ref": "CONTROL_cik"
147  },
148  {
149   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
150   "map": {"at": 1040, "to": "pkt3"},
151   "name": "CP_DMA_WORD0",
152   "type_ref": "CP_DMA_WORD0"
153  },
154  {
155   "chips": ["gfx6"],
156   "map": {"at": 1041, "to": "pkt3"},
157   "name": "CP_DMA_WORD1",
158   "type_ref": "CP_DMA_WORD1"
159  },
160  {
161   "chips": ["gfx7", "gfx8", "gfx81"],
162   "map": {"at": 1041, "to": "pkt3"},
163   "name": "CP_DMA_WORD1",
164   "type_ref": "CP_DMA_WORD1_cik"
165  },
166  {
167   "chips": ["gfx9", "gfx10", "gfx103"],
168   "map": {"at": 1041, "to": "pkt3"},
169   "name": "CP_DMA_WORD1",
170   "type_ref": "CP_DMA_WORD1_gfx9"
171  },
172  {
173   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
174   "map": {"at": 1042, "to": "pkt3"},
175   "name": "CP_DMA_WORD2",
176   "type_ref": "CP_DMA_WORD2"
177  },
178  {
179   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
180   "map": {"at": 1043, "to": "pkt3"},
181   "name": "CP_DMA_WORD3",
182   "type_ref": "CP_DMA_WORD3"
183  },
184  {
185   "chips": ["gfx6"],
186   "map": {"at": 1280, "to": "pkt3"},
187   "name": "DMA_DATA_WORD0",
188   "type_ref": "DMA_DATA_WORD0"
189  },
190  {
191   "chips": ["gfx7", "gfx8", "gfx81"],
192   "map": {"at": 1280, "to": "pkt3"},
193   "name": "DMA_DATA_WORD0",
194   "type_ref": "DMA_DATA_WORD0_cik"
195  },
196  {
197   "chips": ["gfx9", "gfx10", "gfx103"],
198   "map": {"at": 1280, "to": "pkt3"},
199   "name": "DMA_DATA_WORD0",
200   "type_ref": "DMA_DATA_WORD0_gfx9"
201  },
202  {
203   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
204   "map": {"at": 882, "to": "pkt3"},
205   "name": "DST_ADDR_HI"
206  },
207  {
208   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
209   "map": {"at": 1284, "to": "pkt3"},
210   "name": "DST_ADDR_HI"
211  },
212  {
213   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
214   "map": {"at": 881, "to": "pkt3"},
215   "name": "DST_ADDR_LO"
216  },
217  {
218   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
219   "map": {"at": 1283, "to": "pkt3"},
220   "name": "DST_ADDR_LO"
221  },
222  {
223   "chips": ["gfx10", "gfx103"],
224   "map": {"at": 1414, "to": "pkt3"},
225   "name": "GCR_CNTL",
226   "type_ref": "GCR_CNTL"
227  },
228  {
229   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
230   "map": {"at": 1009, "to": "pkt3"},
231   "name": "IB_BASE_HI"
232  },
233  {
234   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
235   "map": {"at": 1008, "to": "pkt3"},
236   "name": "IB_BASE_LO"
237  },
238  {
239   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
240   "map": {"at": 1010, "to": "pkt3"},
241   "name": "IB_CONTROL",
242   "type_ref": "IB_CONTROL"
243  },
244  {
245   "chips": ["gfx10", "gfx103"],
246   "map": {"at": 1168, "to": "pkt3"},
247   "name": "RELEASE_MEM_OP",
248   "type_ref": "RELEASE_MEM_OP"
249  },
250  {
251   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
252   "map": {"at": 1282, "to": "pkt3"},
253   "name": "SRC_ADDR_HI"
254  },
255  {
256   "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
257   "map": {"at": 1281, "to": "pkt3"},
258   "name": "SRC_ADDR_LO"
259  }
260 ],
261 "register_types": {
262  "COMMAND": {
263   "fields": [
264    {"bits": [0, 20], "name": "BYTE_COUNT"},
265    {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
266    {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
267    {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
268    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
269    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
270    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
271    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
272    {"bits": [30, 30], "name": "RAW_WAIT"}
273   ]
274  },
275  "COMMAND_gfx9": {
276   "fields": [
277    {"bits": [0, 25], "name": "BYTE_COUNT"},
278    {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
279    {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
280    {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
281    {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
282    {"bits": [30, 30], "name": "RAW_WAIT"},
283    {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
284   ]
285  },
286  "CONTROL": {
287   "fields": [
288    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
289    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
290    {"bits": [20, 20], "name": "WR_CONFIRM"},
291    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
292   ]
293  },
294  "CONTROL_cik": {
295   "fields": [
296    {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
297    {"bits": [16, 16], "name": "WR_ONE_ADDR"},
298    {"bits": [20, 20], "name": "WR_CONFIRM"},
299    {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
300   ]
301  },
302  "CP_DMA_WORD0": {
303   "fields": [
304    {"bits": [0, 31], "name": "SRC_ADDR_LO"}
305   ]
306  },
307  "CP_DMA_WORD1": {
308   "fields": [
309    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
310    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
311    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
312    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
313    {"bits": [31, 31], "name": "CP_SYNC"}
314   ]
315  },
316  "CP_DMA_WORD1_cik": {
317   "fields": [
318    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
319    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
320    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
321    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
322    {"bits": [31, 31], "name": "CP_SYNC"}
323   ]
324  },
325  "CP_DMA_WORD1_gfx9": {
326   "fields": [
327    {"bits": [0, 15], "name": "SRC_ADDR_HI"},
328    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
329    {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
330    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
331    {"bits": [31, 31], "name": "CP_SYNC"}
332   ]
333  },
334  "CP_DMA_WORD2": {
335   "fields": [
336    {"bits": [0, 31], "name": "DST_ADDR_LO"}
337   ]
338  },
339  "CP_DMA_WORD3": {
340   "fields": [
341    {"bits": [0, 15], "name": "DST_ADDR_HI"}
342   ]
343  },
344  "DMA_DATA_WORD0": {
345   "fields": [
346    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
347    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
348    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
349    {"bits": [31, 31], "name": "CP_SYNC"}
350   ]
351  },
352  "DMA_DATA_WORD0_cik": {
353   "fields": [
354    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
355    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
356    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
357    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
358    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
359    {"bits": [31, 31], "name": "CP_SYNC"}
360   ]
361  },
362  "DMA_DATA_WORD0_gfx9": {
363   "fields": [
364    {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
365    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
366    {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
367    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
368    {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
369    {"bits": [31, 31], "name": "CP_SYNC"}
370   ]
371  },
372  "GCR_CNTL": {
373   "fields": [
374    {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
375    {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
376    {"bits": [4, 4], "name": "GLM_WB"},
377    {"bits": [5, 5], "name": "GLM_INV"},
378    {"bits": [6, 6], "name": "GLK_WB"},
379    {"bits": [7, 7], "name": "GLK_INV"},
380    {"bits": [8, 8], "name": "GLV_INV"},
381    {"bits": [9, 9], "name": "GL1_INV"},
382    {"bits": [10, 10], "name": "GL2_US"},
383    {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
384    {"bits": [13, 13], "name": "GL2_DISCARD"},
385    {"bits": [14, 14], "name": "GL2_INV"},
386    {"bits": [15, 15], "name": "GL2_WB"},
387    {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
388    {"bits": [18, 18], "name": "RANGE_IS_PA"}
389   ]
390  },
391  "IB_CONTROL": {
392   "fields": [
393    {"bits": [0, 19], "name": "IB_SIZE"},
394    {"bits": [20, 20], "name": "CHAIN"},
395    {"bits": [23, 23], "name": "VALID"}
396   ]
397  },
398  "RELEASE_MEM_OP": {
399   "fields": [
400    {"bits": [0, 5], "name": "EVENT_TYPE"},
401    {"bits": [8, 11], "name": "EVENT_INDEX"},
402    {"bits": [12, 12], "name": "GLM_WB"},
403    {"bits": [13, 13], "name": "GLM_INV"},
404    {"bits": [14, 14], "name": "GLV_INV"},
405    {"bits": [15, 15], "name": "GL1_INV"},
406    {"bits": [16, 16], "name": "GL2_US"},
407    {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
408    {"bits": [19, 19], "name": "GL2_DISCARD"},
409    {"bits": [20, 20], "name": "GL2_INV"},
410    {"bits": [21, 21], "name": "GL2_WB"},
411    {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
412   ]
413  }
414 }
415}
416