1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<domain name="DSI" width="32"> 8 <enum name="dsi_traffic_mode"> 9 <value name="NON_BURST_SYNCH_PULSE" value="0"/> 10 <value name="NON_BURST_SYNCH_EVENT" value="1"/> 11 <value name="BURST_MODE" value="2"/> 12 </enum> 13 <enum name="dsi_vid_dst_format"> 14 <value name="VID_DST_FORMAT_RGB565" value="0"/> 15 <value name="VID_DST_FORMAT_RGB666" value="1"/> 16 <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/> 17 <value name="VID_DST_FORMAT_RGB888" value="3"/> 18 </enum> 19 <enum name="dsi_rgb_swap"> 20 <value name="SWAP_RGB" value="0"/> 21 <value name="SWAP_RBG" value="1"/> 22 <value name="SWAP_BGR" value="2"/> 23 <value name="SWAP_BRG" value="3"/> 24 <value name="SWAP_GRB" value="4"/> 25 <value name="SWAP_GBR" value="5"/> 26 </enum> 27 <enum name="dsi_cmd_trigger"> 28 <value name="TRIGGER_NONE" value="0"/> 29 <value name="TRIGGER_SEOF" value="1"/> 30 <value name="TRIGGER_TE" value="2"/> 31 <value name="TRIGGER_SW" value="4"/> 32 <value name="TRIGGER_SW_SEOF" value="5"/> 33 <value name="TRIGGER_SW_TE" value="6"/> 34 </enum> 35 <enum name="dsi_cmd_dst_format"> 36 <value name="CMD_DST_FORMAT_RGB111" value="0"/> 37 <value name="CMD_DST_FORMAT_RGB332" value="3"/> 38 <value name="CMD_DST_FORMAT_RGB444" value="4"/> 39 <value name="CMD_DST_FORMAT_RGB565" value="6"/> 40 <value name="CMD_DST_FORMAT_RGB666" value="7"/> 41 <value name="CMD_DST_FORMAT_RGB888" value="8"/> 42 </enum> 43 <enum name="dsi_lane_swap"> 44 <value name="LANE_SWAP_0123" value="0"/> 45 <value name="LANE_SWAP_3012" value="1"/> 46 <value name="LANE_SWAP_2301" value="2"/> 47 <value name="LANE_SWAP_1230" value="3"/> 48 <value name="LANE_SWAP_0321" value="4"/> 49 <value name="LANE_SWAP_1032" value="5"/> 50 <value name="LANE_SWAP_2103" value="6"/> 51 <value name="LANE_SWAP_3210" value="7"/> 52 </enum> 53 <bitset name="DSI_IRQ"> 54 <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/> 55 <bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/> 56 <bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/> 57 <bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/> 58 <bitfield name="VIDEO_DONE" pos="16" type="boolean"/> 59 <bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/> 60 <bitfield name="BTA_DONE" pos="20" type="boolean"/> 61 <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/> 62 <bitfield name="ERROR" pos="24" type="boolean"/> 63 <bitfield name="MASK_ERROR" pos="25" type="boolean"/> 64 </bitset> 65 66 <reg32 offset="0x00000" name="6G_HW_VERSION"> 67 <bitfield name="MAJOR" low="28" high="31" type="uint"/> 68 <bitfield name="MINOR" low="16" high="27" type="uint"/> 69 <bitfield name="STEP" low="0" high="15" type="uint"/> 70 </reg32> 71 72 <reg32 offset="0x00000" name="CTRL"> 73 <bitfield name="ENABLE" pos="0" type="boolean"/> 74 <bitfield name="VID_MODE_EN" pos="1" type="boolean"/> 75 <bitfield name="CMD_MODE_EN" pos="2" type="boolean"/> 76 <bitfield name="LANE0" pos="4" type="boolean"/> 77 <bitfield name="LANE1" pos="5" type="boolean"/> 78 <bitfield name="LANE2" pos="6" type="boolean"/> 79 <bitfield name="LANE3" pos="7" type="boolean"/> 80 <bitfield name="CLK_EN" pos="8" type="boolean"/> 81 <bitfield name="ECC_CHECK" pos="20" type="boolean"/> 82 <bitfield name="CRC_CHECK" pos="24" type="boolean"/> 83 </reg32> 84 85 <reg32 offset="0x00004" name="STATUS0"> 86 <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/> 87 <bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/> 88 <bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/> 89 <bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/> 90 <bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() --> 91 <bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/> 92 </reg32> 93 94 <reg32 offset="0x00008" name="FIFO_STATUS"> 95 <bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/> 96 <bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/> 97 <bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/> 98 <bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/> 99 <bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/> 100 <bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/> 101 <bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/> 102 <bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/> 103 <bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/> 104 <bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/> 105 <bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/> 106 <bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/> 107 <bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/> 108 <bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/> 109 <bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/> 110 <bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/> 111 <bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/> 112 <bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/> 113 <bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/> 114 <bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/> 115 <bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/> 116 <bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/> 117 <bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/> 118 <bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/> 119 <bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/> 120 </reg32> 121 <reg32 offset="0x0000c" name="VID_CFG0"> 122 <bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? --> 123 <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/> 124 <bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/> 125 <bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/> 126 <bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/> 127 <bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/> 128 <bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/> 129 <bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/> 130 <bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/> 131 </reg32> 132 <reg32 offset="0x0001c" name="VID_CFG1"> 133 <bitfield name="R_SEL" pos="0" type="boolean"/> 134 <bitfield name="G_SEL" pos="4" type="boolean"/> 135 <bitfield name="B_SEL" pos="8" type="boolean"/> 136 <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/> 137 </reg32> 138 <reg32 offset="0x00020" name="ACTIVE_H"> 139 <bitfield name="START" low="0" high="11" type="uint"/> 140 <bitfield name="END" low="16" high="27" type="uint"/> 141 </reg32> 142 <reg32 offset="0x00024" name="ACTIVE_V"> 143 <bitfield name="START" low="0" high="11" type="uint"/> 144 <bitfield name="END" low="16" high="27" type="uint"/> 145 </reg32> 146 <reg32 offset="0x00028" name="TOTAL"> 147 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 148 <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 149 </reg32> 150 <reg32 offset="0x0002c" name="ACTIVE_HSYNC"> 151 <bitfield name="START" low="0" high="11" type="uint"/> 152 <bitfield name="END" low="16" high="27" type="uint"/> 153 </reg32> 154 <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS"> 155 <bitfield name="START" low="0" high="11" type="uint"/> 156 <bitfield name="END" low="16" high="27" type="uint"/> 157 </reg32> 158 <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS"> 159 <bitfield name="START" low="0" high="11" type="uint"/> 160 <bitfield name="END" low="16" high="27" type="uint"/> 161 </reg32> 162 163 <reg32 offset="0x00038" name="CMD_DMA_CTRL"> 164 <bitfield name="BROADCAST_EN" pos="31" type="boolean"/> 165 <bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/> 166 <bitfield name="LOW_POWER" pos="26" type="boolean"/> 167 </reg32> 168 <reg32 offset="0x0003c" name="CMD_CFG0"> 169 <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/> 170 <bitfield name="R_SEL" pos="4" type="boolean"/> 171 <bitfield name="G_SEL" pos="8" type="boolean"/> 172 <bitfield name="B_SEL" pos="12" type="boolean"/> 173 <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/> 174 <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/> 175 </reg32> 176 <reg32 offset="0x00040" name="CMD_CFG1"> 177 <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/> 178 <bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/> 179 <bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/> 180 </reg32> 181 <reg32 offset="0x00044" name="DMA_BASE"/> 182 <reg32 offset="0x00048" name="DMA_LEN"/> 183 <reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL"> 184 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/> 185 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/> 186 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/> 187 </reg32> 188 <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL"> 189 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 190 <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 191 </reg32> 192 <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL"> 193 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/> 194 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/> 195 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/> 196 </reg32> 197 <reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL"> 198 <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> 199 <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> 200 </reg32> 201 <reg32 offset="0x00064" name="ACK_ERR_STATUS"/> 202 <array offset="0x00068" name="RDBK" length="4" stride="4"> 203 <reg32 offset="0x0" name="DATA"/> 204 </array> 205 <reg32 offset="0x00080" name="TRIG_CTRL"> 206 <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/> 207 <bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/> 208 <bitfield name="STREAM" low="8" high="9" type="uint"/> 209 <bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/> 210 <bitfield name="TE" pos="31" type="boolean"/> 211 </reg32> 212 <reg32 offset="0x0008c" name="TRIG_DMA"/> 213 <reg32 offset="0x000b0" name="DLN0_PHY_ERR"> 214 <bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/> 215 <bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/> 216 <bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/> 217 <bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/> 218 <bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/> 219 </reg32> 220 <reg32 offset="0x000b4" name="LP_TIMER_CTRL"> 221 <bitfield name="LP_RX_TO" low="0" high="15" type="uint"/> 222 <bitfield name="BTA_TO" low="16" high="31" type="uint"/> 223 </reg32> 224 <reg32 offset="0x000b8" name="HS_TIMER_CTRL"> 225 <bitfield name="HS_TX_TO" low="0" high="15" type="uint"/> 226 <bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/> 227 <bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/> 228 </reg32> 229 <reg32 offset="0x000bc" name="TIMEOUT_STATUS"/> 230 <reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL"> 231 <bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/> 232 <bitfield name="T_CLK_POST" low="8" high="13" type="uint"/> 233 </reg32> 234 <reg32 offset="0x000c8" name="EOT_PACKET_CTRL"> 235 <bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/> 236 <bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/> 237 </reg32> 238 <reg32 offset="0x000a4" name="LANE_STATUS"> 239 <bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/> 240 <bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/> 241 <bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/> 242 <bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/> 243 <bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/> 244 <bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/> 245 <bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/> 246 <bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/> 247 <bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/> 248 <bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/> 249 <bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/> 250 </reg32> 251 <reg32 offset="0x000a8" name="LANE_CTRL"> 252 <bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/> 253 </reg32> 254 <reg32 offset="0x000ac" name="LANE_SWAP_CTRL"> 255 <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/> 256 </reg32> 257 <reg32 offset="0x00108" name="ERR_INT_MASK0"/> 258 <reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/> 259 <reg32 offset="0x00114" name="RESET"/> 260 <reg32 offset="0x00118" name="CLK_CTRL"> 261 <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/> 262 <bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/> 263 <bitfield name="PCLK_ON" pos="2" type="boolean"/> 264 <bitfield name="DSICLK_ON" pos="3" type="boolean"/> 265 <bitfield name="BYTECLK_ON" pos="4" type="boolean"/> 266 <bitfield name="ESCCLK_ON" pos="5" type="boolean"/> 267 <bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/> 268 </reg32> 269 <reg32 offset="0x0011c" name="CLK_STATUS"> 270 <bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/> 271 <bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/> 272 <bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/> 273 <bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/> 274 <bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/> 275 <bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/> 276 <bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/> 277 <bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/> 278 <bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/> 279 <bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/> 280 <bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/> 281 <bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/> 282 <bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/> 283 <bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/> 284 <bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/> 285 <bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/> 286 </reg32> 287 <reg32 offset="0x00128" name="PHY_RESET"> 288 <bitfield name="RESET" pos="0" type="boolean"/> 289 </reg32> 290 <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND"> 291 <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/> 292 </reg32> 293 <reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2"> 294 <bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/> 295 <bitfield name="R_SEL" pos="4" type="boolean"/> 296 <bitfield name="G_SEL" pos="5" type="boolean"/> 297 <bitfield name="B_SEL" pos="6" type="boolean"/> 298 <bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/> 299 <bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/> 300 <bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/> 301 <bitfield name="BURST_MODE" pos="16" type="boolean"/> 302 </reg32> 303 <reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL"> 304 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/> 305 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/> 306 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/> 307 </reg32> 308 <reg32 offset="0x001d0" name="RDBK_DATA_CTRL"> 309 <bitfield name="COUNT" low="16" high="23" type="uint"/> 310 <bitfield name="CLR" pos="0" type="boolean"/> 311 </reg32> 312 <reg32 offset="0x001f0" name="VERSION"> 313 <bitfield name="MAJOR" low="24" high="31" type="uint"/> 314 </reg32> 315 316 <reg32 offset="0x00200" name="PHY_PLL_CTRL_0"> 317 <bitfield name="ENABLE" pos="0" type="boolean"/> 318 </reg32> 319 <reg32 offset="0x00204" name="PHY_PLL_CTRL_1"/> 320 <reg32 offset="0x00208" name="PHY_PLL_CTRL_2"/> 321 <reg32 offset="0x0020c" name="PHY_PLL_CTRL_3"/> 322 <reg32 offset="0x00210" name="PHY_PLL_CTRL_4"/> 323 <reg32 offset="0x00214" name="PHY_PLL_CTRL_5"/> 324 <reg32 offset="0x00218" name="PHY_PLL_CTRL_6"/> 325 <reg32 offset="0x0021c" name="PHY_PLL_CTRL_7"/> 326 <reg32 offset="0x00220" name="PHY_PLL_CTRL_8"/> 327 <reg32 offset="0x00224" name="PHY_PLL_CTRL_9"/> 328 <reg32 offset="0x00228" name="PHY_PLL_CTRL_10"/> 329 <reg32 offset="0x0022c" name="PHY_PLL_CTRL_11"/> 330 <reg32 offset="0x00230" name="PHY_PLL_CTRL_12"/> 331 <reg32 offset="0x00234" name="PHY_PLL_CTRL_13"/> 332 <reg32 offset="0x00238" name="PHY_PLL_CTRL_14"/> 333 <reg32 offset="0x0023c" name="PHY_PLL_CTRL_15"/> 334 <reg32 offset="0x00240" name="PHY_PLL_CTRL_16"/> 335 <reg32 offset="0x00244" name="PHY_PLL_CTRL_17"/> 336 <reg32 offset="0x00248" name="PHY_PLL_CTRL_18"/> 337 <reg32 offset="0x0024c" name="PHY_PLL_CTRL_19"/> 338 <reg32 offset="0x00250" name="PHY_PLL_CTRL_20"/> 339 340 <reg32 offset="0x00280" name="PHY_PLL_STATUS"> 341 <bitfield name="PLL_BUSY" pos="0" type="boolean"/> 342 </reg32> 343</domain> 344 345<domain name="DSI_8x60" width="32"> 346 <reg32 offset="0x00258" name="PHY_TPA_CTRL_1"/> 347 <reg32 offset="0x0025c" name="PHY_TPA_CTRL_2"/> 348 <reg32 offset="0x00260" name="PHY_TIMING_CTRL_0"/> 349 <reg32 offset="0x00264" name="PHY_TIMING_CTRL_1"/> 350 <reg32 offset="0x00268" name="PHY_TIMING_CTRL_2"/> 351 <reg32 offset="0x0026c" name="PHY_TIMING_CTRL_3"/> 352 <reg32 offset="0x00270" name="PHY_TIMING_CTRL_4"/> 353 <reg32 offset="0x00274" name="PHY_TIMING_CTRL_5"/> 354 <reg32 offset="0x00278" name="PHY_TIMING_CTRL_6"/> 355 <reg32 offset="0x0027c" name="PHY_TIMING_CTRL_7"/> 356 <reg32 offset="0x00280" name="PHY_TIMING_CTRL_8"/> 357 <reg32 offset="0x00284" name="PHY_TIMING_CTRL_9"/> 358 <reg32 offset="0x00288" name="PHY_TIMING_CTRL_10"/> 359 <reg32 offset="0x0028c" name="PHY_TIMING_CTRL_11"/> 360 <reg32 offset="0x00290" name="PHY_CTRL_0"/> 361 <reg32 offset="0x00294" name="PHY_CTRL_1"/> 362 <reg32 offset="0x00298" name="PHY_CTRL_2"/> 363 <reg32 offset="0x0029c" name="PHY_CTRL_3"/> 364 <reg32 offset="0x002a0" name="PHY_STRENGTH_0"/> 365 <reg32 offset="0x002a4" name="PHY_STRENGTH_1"/> 366 <reg32 offset="0x002a8" name="PHY_STRENGTH_2"/> 367 <reg32 offset="0x002ac" name="PHY_STRENGTH_3"/> 368 <reg32 offset="0x002cc" name="PHY_REGULATOR_CTRL_0"/> 369 <reg32 offset="0x002d0" name="PHY_REGULATOR_CTRL_1"/> 370 <reg32 offset="0x002d4" name="PHY_REGULATOR_CTRL_2"/> 371 <reg32 offset="0x002d8" name="PHY_REGULATOR_CTRL_3"/> 372 <reg32 offset="0x002dc" name="PHY_REGULATOR_CTRL_4"/> 373 374 <reg32 offset="0x000f0" name="PHY_CAL_HW_TRIGGER"/> 375 <reg32 offset="0x000f4" name="PHY_CAL_CTRL"/> 376 <reg32 offset="0x000fc" name="PHY_CAL_STATUS"> 377 <bitfield name="CAL_BUSY" pos="28" type="boolean"/> 378 </reg32> 379</domain> 380 381<domain name="DSI_28nm_8960_PHY" width="32"> 382 383 <array offset="0x00000" name="LN" length="4" stride="0x40"> 384 <reg32 offset="0x00" name="CFG_0"/> 385 <reg32 offset="0x04" name="CFG_1"/> 386 <reg32 offset="0x08" name="CFG_2"/> 387 <reg32 offset="0x0c" name="TEST_DATAPATH"/> 388 <reg32 offset="0x14" name="TEST_STR_0"/> 389 <reg32 offset="0x18" name="TEST_STR_1"/> 390 </array> 391 392 <reg32 offset="0x00100" name="LNCK_CFG_0"/> 393 <reg32 offset="0x00104" name="LNCK_CFG_1"/> 394 <reg32 offset="0x00108" name="LNCK_CFG_2"/> 395 396 <reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/> 397 <reg32 offset="0x00114" name="LNCK_TEST_STR0"/> 398 <reg32 offset="0x00118" name="LNCK_TEST_STR1"/> 399 400 <reg32 offset="0x00140" name="TIMING_CTRL_0"> 401 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/> 402 </reg32> 403 <reg32 offset="0x00144" name="TIMING_CTRL_1"> 404 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/> 405 </reg32> 406 <reg32 offset="0x00148" name="TIMING_CTRL_2"> 407 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/> 408 </reg32> 409 410 <reg32 offset="0x0014c" name="TIMING_CTRL_3"/> 411 412 <reg32 offset="0x00150" name="TIMING_CTRL_4"> 413 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/> 414 </reg32> 415 <reg32 offset="0x00154" name="TIMING_CTRL_5"> 416 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/> 417 </reg32> 418 <reg32 offset="0x00158" name="TIMING_CTRL_6"> 419 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/> 420 </reg32> 421 <reg32 offset="0x0015c" name="TIMING_CTRL_7"> 422 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/> 423 </reg32> 424 <reg32 offset="0x00160" name="TIMING_CTRL_8"> 425 <bitfield name="HS_RQST" low="0" high="7" type="uint"/> 426 </reg32> 427 <reg32 offset="0x00164" name="TIMING_CTRL_9"> 428 <bitfield name="TA_GO" low="0" high="2" type="uint"/> 429 <bitfield name="TA_SURE" low="4" high="6" type="uint"/> 430 </reg32> 431 <reg32 offset="0x00168" name="TIMING_CTRL_10"> 432 <bitfield name="TA_GET" low="0" high="2" type="uint"/> 433 </reg32> 434 <reg32 offset="0x0016c" name="TIMING_CTRL_11"> 435 <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/> 436 </reg32> 437 438 <reg32 offset="0x00170" name="CTRL_0"/> 439 <reg32 offset="0x00174" name="CTRL_1"/> 440 <reg32 offset="0x00178" name="CTRL_2"/> 441 <reg32 offset="0x0017c" name="CTRL_3"/> 442 443 <reg32 offset="0x00180" name="STRENGTH_0"/> 444 <reg32 offset="0x00184" name="STRENGTH_1"/> 445 <reg32 offset="0x00188" name="STRENGTH_2"/> 446 447 <reg32 offset="0x0018c" name="BIST_CTRL_0"/> 448 <reg32 offset="0x00190" name="BIST_CTRL_1"/> 449 <reg32 offset="0x00194" name="BIST_CTRL_2"/> 450 <reg32 offset="0x00198" name="BIST_CTRL_3"/> 451 <reg32 offset="0x0019c" name="BIST_CTRL_4"/> 452 453 <reg32 offset="0x001b0" name="LDO_CTRL"/> 454</domain> 455 456<domain name="DSI_28nm_8960_PHY_MISC" width="32"> 457 <reg32 offset="0x00000" name="REGULATOR_CTRL_0"/> 458 <reg32 offset="0x00004" name="REGULATOR_CTRL_1"/> 459 <reg32 offset="0x00008" name="REGULATOR_CTRL_2"/> 460 <reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/> 461 <reg32 offset="0x00010" name="REGULATOR_CTRL_4"/> 462 <reg32 offset="0x00014" name="REGULATOR_CTRL_5"/> 463 <reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/> 464 <reg32 offset="0x00028" name="CAL_HW_TRIGGER"/> 465 <reg32 offset="0x0002c" name="CAL_SW_CFG_0"/> 466 <reg32 offset="0x00030" name="CAL_SW_CFG_1"/> 467 <reg32 offset="0x00034" name="CAL_SW_CFG_2"/> 468 <reg32 offset="0x00038" name="CAL_HW_CFG_0"/> 469 <reg32 offset="0x0003c" name="CAL_HW_CFG_1"/> 470 <reg32 offset="0x00040" name="CAL_HW_CFG_2"/> 471 <reg32 offset="0x00044" name="CAL_HW_CFG_3"/> 472 <reg32 offset="0x00048" name="CAL_HW_CFG_4"/> 473 <reg32 offset="0x00050" name="CAL_STATUS"> 474 <bitfield name="CAL_BUSY" pos="4" type="boolean"/> 475 </reg32> 476</domain> 477 478<domain name="DSI_28nm_8960_PHY_PLL" width="32"> 479 <reg32 offset="0x00000" name="CTRL_0"> 480 <bitfield name="ENABLE" pos="0" type="boolean"/> 481 </reg32> 482 <reg32 offset="0x00004" name="CTRL_1"/> 483 <reg32 offset="0x00008" name="CTRL_2"/> 484 <reg32 offset="0x0000c" name="CTRL_3"/> 485 <reg32 offset="0x00010" name="CTRL_4"/> 486 <reg32 offset="0x00014" name="CTRL_5"/> 487 <reg32 offset="0x00018" name="CTRL_6"/> 488 <reg32 offset="0x0001c" name="CTRL_7"/> 489 <reg32 offset="0x00020" name="CTRL_8"/> 490 <reg32 offset="0x00024" name="CTRL_9"/> 491 <reg32 offset="0x00028" name="CTRL_10"/> 492 <reg32 offset="0x0002c" name="CTRL_11"/> 493 <reg32 offset="0x00030" name="CTRL_12"/> 494 <reg32 offset="0x00034" name="CTRL_13"/> 495 <reg32 offset="0x00038" name="CTRL_14"/> 496 <reg32 offset="0x0003c" name="CTRL_15"/> 497 <reg32 offset="0x00040" name="CTRL_16"/> 498 <reg32 offset="0x00044" name="CTRL_17"/> 499 <reg32 offset="0x00048" name="CTRL_18"/> 500 <reg32 offset="0x0004c" name="CTRL_19"/> 501 <reg32 offset="0x00050" name="CTRL_20"/> 502 503 <reg32 offset="0x00080" name="RDY"> 504 <bitfield name="PLL_RDY" pos="0" type="boolean"/> 505 </reg32> 506</domain> 507 508<domain name="DSI_28nm_PHY" width="32"> 509 <array offset="0x00000" name="LN" length="4" stride="0x40"> 510 <reg32 offset="0x00" name="CFG_0"/> 511 <reg32 offset="0x04" name="CFG_1"/> 512 <reg32 offset="0x08" name="CFG_2"/> 513 <reg32 offset="0x0c" name="CFG_3"/> 514 <reg32 offset="0x10" name="CFG_4"/> 515 <reg32 offset="0x14" name="TEST_DATAPATH"/> 516 <reg32 offset="0x18" name="DEBUG_SEL"/> 517 <reg32 offset="0x1c" name="TEST_STR_0"/> 518 <reg32 offset="0x20" name="TEST_STR_1"/> 519 </array> 520 521 <reg32 offset="0x00100" name="LNCK_CFG_0"/> 522 <reg32 offset="0x00104" name="LNCK_CFG_1"/> 523 <reg32 offset="0x00108" name="LNCK_CFG_2"/> 524 <reg32 offset="0x0010c" name="LNCK_CFG_3"/> 525 <reg32 offset="0x00110" name="LNCK_CFG_4"/> 526 <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/> 527 <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/> 528 <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/> 529 <reg32 offset="0x00120" name="LNCK_TEST_STR1"/> 530 531 <reg32 offset="0x00140" name="TIMING_CTRL_0"> 532 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/> 533 </reg32> 534 <reg32 offset="0x00144" name="TIMING_CTRL_1"> 535 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/> 536 </reg32> 537 <reg32 offset="0x00148" name="TIMING_CTRL_2"> 538 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/> 539 </reg32> 540 <reg32 offset="0x0014c" name="TIMING_CTRL_3"> 541 <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/> 542 </reg32> 543 <reg32 offset="0x00150" name="TIMING_CTRL_4"> 544 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/> 545 </reg32> 546 <reg32 offset="0x00154" name="TIMING_CTRL_5"> 547 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/> 548 </reg32> 549 <reg32 offset="0x00158" name="TIMING_CTRL_6"> 550 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/> 551 </reg32> 552 <reg32 offset="0x0015c" name="TIMING_CTRL_7"> 553 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/> 554 </reg32> 555 <reg32 offset="0x00160" name="TIMING_CTRL_8"> 556 <bitfield name="HS_RQST" low="0" high="7" type="uint"/> 557 </reg32> 558 <reg32 offset="0x00164" name="TIMING_CTRL_9"> 559 <bitfield name="TA_GO" low="0" high="2" type="uint"/> 560 <bitfield name="TA_SURE" low="4" high="6" type="uint"/> 561 </reg32> 562 <reg32 offset="0x00168" name="TIMING_CTRL_10"> 563 <bitfield name="TA_GET" low="0" high="2" type="uint"/> 564 </reg32> 565 <reg32 offset="0x0016c" name="TIMING_CTRL_11"> 566 <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/> 567 </reg32> 568 569 <reg32 offset="0x00170" name="CTRL_0"/> 570 <reg32 offset="0x00174" name="CTRL_1"/> 571 <reg32 offset="0x00178" name="CTRL_2"/> 572 <reg32 offset="0x0017c" name="CTRL_3"/> 573 <reg32 offset="0x00180" name="CTRL_4"/> 574 575 <reg32 offset="0x00184" name="STRENGTH_0"/> 576 <reg32 offset="0x00188" name="STRENGTH_1"/> 577 578 <reg32 offset="0x001b4" name="BIST_CTRL_0"/> 579 <reg32 offset="0x001b8" name="BIST_CTRL_1"/> 580 <reg32 offset="0x001bc" name="BIST_CTRL_2"/> 581 <reg32 offset="0x001c0" name="BIST_CTRL_3"/> 582 <reg32 offset="0x001c4" name="BIST_CTRL_4"/> 583 <reg32 offset="0x001c8" name="BIST_CTRL_5"/> 584 585 <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"> 586 <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/> 587 </reg32> 588 <reg32 offset="0x001dc" name="LDO_CNTRL"/> 589</domain> 590 591<domain name="DSI_28nm_PHY_REGULATOR" width="32"> 592 <reg32 offset="0x00000" name="CTRL_0"/> 593 <reg32 offset="0x00004" name="CTRL_1"/> 594 <reg32 offset="0x00008" name="CTRL_2"/> 595 <reg32 offset="0x0000c" name="CTRL_3"/> 596 <reg32 offset="0x00010" name="CTRL_4"/> 597 <reg32 offset="0x00014" name="CTRL_5"/> 598 <reg32 offset="0x00018" name="CAL_PWR_CFG"/> 599</domain> 600 601<domain name="DSI_28nm_PHY_PLL" width="32"> 602 <reg32 offset="0x00000" name="REFCLK_CFG"> 603 <bitfield name="DBLR" pos="0" type="boolean"/> 604 </reg32> 605 <reg32 offset="0x00004" name="POSTDIV1_CFG"/> 606 <reg32 offset="0x00008" name="CHGPUMP_CFG"/> 607 <reg32 offset="0x0000C" name="VCOLPF_CFG"/> 608 <reg32 offset="0x00010" name="VREG_CFG"> 609 <bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/> 610 </reg32> 611 <reg32 offset="0x00014" name="PWRGEN_CFG"/> 612 <reg32 offset="0x00018" name="DMUX_CFG"/> 613 <reg32 offset="0x0001C" name="AMUX_CFG"/> 614 <reg32 offset="0x00020" name="GLB_CFG"> 615 <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/> 616 <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/> 617 <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/> 618 <bitfield name="PLL_ENABLE" pos="3" type="boolean"/> 619 </reg32> 620 <reg32 offset="0x00024" name="POSTDIV2_CFG"/> 621 <reg32 offset="0x00028" name="POSTDIV3_CFG"/> 622 <reg32 offset="0x0002C" name="LPFR_CFG"/> 623 <reg32 offset="0x00030" name="LPFC1_CFG"/> 624 <reg32 offset="0x00034" name="LPFC2_CFG"/> 625 <reg32 offset="0x00038" name="SDM_CFG0"> 626 <bitfield name="BYP_DIV" low="0" high="5" type="uint"/> 627 <bitfield name="BYP" pos="6" type="boolean"/> 628 </reg32> 629 <reg32 offset="0x0003C" name="SDM_CFG1"> 630 <bitfield name="DC_OFFSET" low="0" high="5" type="uint"/> 631 <bitfield name="DITHER_EN" pos="6" type="uint"/> 632 </reg32> 633 <reg32 offset="0x00040" name="SDM_CFG2"> 634 <bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/> 635 </reg32> 636 <reg32 offset="0x00044" name="SDM_CFG3"> 637 <bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/> 638 </reg32> 639 <reg32 offset="0x00048" name="SDM_CFG4"/> 640 <reg32 offset="0x0004C" name="SSC_CFG0"/> 641 <reg32 offset="0x00050" name="SSC_CFG1"/> 642 <reg32 offset="0x00054" name="SSC_CFG2"/> 643 <reg32 offset="0x00058" name="SSC_CFG3"/> 644 <reg32 offset="0x0005C" name="LKDET_CFG0"/> 645 <reg32 offset="0x00060" name="LKDET_CFG1"/> 646 <reg32 offset="0x00064" name="LKDET_CFG2"/> 647 <reg32 offset="0x00068" name="TEST_CFG"> 648 <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/> 649 </reg32> 650 <reg32 offset="0x0006C" name="CAL_CFG0"/> 651 <reg32 offset="0x00070" name="CAL_CFG1"/> 652 <reg32 offset="0x00074" name="CAL_CFG2"/> 653 <reg32 offset="0x00078" name="CAL_CFG3"/> 654 <reg32 offset="0x0007C" name="CAL_CFG4"/> 655 <reg32 offset="0x00080" name="CAL_CFG5"/> 656 <reg32 offset="0x00084" name="CAL_CFG6"/> 657 <reg32 offset="0x00088" name="CAL_CFG7"/> 658 <reg32 offset="0x0008C" name="CAL_CFG8"/> 659 <reg32 offset="0x00090" name="CAL_CFG9"/> 660 <reg32 offset="0x00094" name="CAL_CFG10"/> 661 <reg32 offset="0x00098" name="CAL_CFG11"/> 662 <reg32 offset="0x0009C" name="EFUSE_CFG"/> 663 <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/> 664 <reg32 offset="0x000A4" name="CTRL_42"/> 665 <reg32 offset="0x000A8" name="CTRL_43"/> 666 <reg32 offset="0x000AC" name="CTRL_44"/> 667 <reg32 offset="0x000B0" name="CTRL_45"/> 668 <reg32 offset="0x000B4" name="CTRL_46"/> 669 <reg32 offset="0x000B8" name="CTRL_47"/> 670 <reg32 offset="0x000BC" name="CTRL_48"/> 671 <reg32 offset="0x000C0" name="STATUS"> 672 <bitfield name="PLL_RDY" pos="0" type="boolean"/> 673 </reg32> 674 <reg32 offset="0x000C4" name="DEBUG_BUS0"/> 675 <reg32 offset="0x000C8" name="DEBUG_BUS1"/> 676 <reg32 offset="0x000CC" name="DEBUG_BUS2"/> 677 <reg32 offset="0x000D0" name="DEBUG_BUS3"/> 678 <reg32 offset="0x000D4" name="CTRL_54"/> 679</domain> 680 681<domain name="DSI_20nm_PHY" width="32"> 682 <array offset="0x00000" name="LN" length="4" stride="0x40"> 683 <reg32 offset="0x00" name="CFG_0"/> 684 <reg32 offset="0x04" name="CFG_1"/> 685 <reg32 offset="0x08" name="CFG_2"/> 686 <reg32 offset="0x0c" name="CFG_3"/> 687 <reg32 offset="0x10" name="CFG_4"/> 688 <reg32 offset="0x14" name="TEST_DATAPATH"/> 689 <reg32 offset="0x18" name="DEBUG_SEL"/> 690 <reg32 offset="0x1c" name="TEST_STR_0"/> 691 <reg32 offset="0x20" name="TEST_STR_1"/> 692 </array> 693 694 <reg32 offset="0x00100" name="LNCK_CFG_0"/> 695 <reg32 offset="0x00104" name="LNCK_CFG_1"/> 696 <reg32 offset="0x00108" name="LNCK_CFG_2"/> 697 <reg32 offset="0x0010c" name="LNCK_CFG_3"/> 698 <reg32 offset="0x00110" name="LNCK_CFG_4"/> 699 <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/> 700 <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/> 701 <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/> 702 <reg32 offset="0x00120" name="LNCK_TEST_STR1"/> 703 704 <reg32 offset="0x00140" name="TIMING_CTRL_0"> 705 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/> 706 </reg32> 707 <reg32 offset="0x00144" name="TIMING_CTRL_1"> 708 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/> 709 </reg32> 710 <reg32 offset="0x00148" name="TIMING_CTRL_2"> 711 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/> 712 </reg32> 713 <reg32 offset="0x0014c" name="TIMING_CTRL_3"> 714 <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/> 715 </reg32> 716 <reg32 offset="0x00150" name="TIMING_CTRL_4"> 717 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/> 718 </reg32> 719 <reg32 offset="0x00154" name="TIMING_CTRL_5"> 720 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/> 721 </reg32> 722 <reg32 offset="0x00158" name="TIMING_CTRL_6"> 723 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/> 724 </reg32> 725 <reg32 offset="0x0015c" name="TIMING_CTRL_7"> 726 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/> 727 </reg32> 728 <reg32 offset="0x00160" name="TIMING_CTRL_8"> 729 <bitfield name="HS_RQST" low="0" high="7" type="uint"/> 730 </reg32> 731 <reg32 offset="0x00164" name="TIMING_CTRL_9"> 732 <bitfield name="TA_GO" low="0" high="2" type="uint"/> 733 <bitfield name="TA_SURE" low="4" high="6" type="uint"/> 734 </reg32> 735 <reg32 offset="0x00168" name="TIMING_CTRL_10"> 736 <bitfield name="TA_GET" low="0" high="2" type="uint"/> 737 </reg32> 738 <reg32 offset="0x0016c" name="TIMING_CTRL_11"> 739 <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/> 740 </reg32> 741 742 <reg32 offset="0x00170" name="CTRL_0"/> 743 <reg32 offset="0x00174" name="CTRL_1"/> 744 <reg32 offset="0x00178" name="CTRL_2"/> 745 <reg32 offset="0x0017c" name="CTRL_3"/> 746 <reg32 offset="0x00180" name="CTRL_4"/> 747 748 <reg32 offset="0x00184" name="STRENGTH_0"/> 749 <reg32 offset="0x00188" name="STRENGTH_1"/> 750 751 <reg32 offset="0x001b4" name="BIST_CTRL_0"/> 752 <reg32 offset="0x001b8" name="BIST_CTRL_1"/> 753 <reg32 offset="0x001bc" name="BIST_CTRL_2"/> 754 <reg32 offset="0x001c0" name="BIST_CTRL_3"/> 755 <reg32 offset="0x001c4" name="BIST_CTRL_4"/> 756 <reg32 offset="0x001c8" name="BIST_CTRL_5"/> 757 758 <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"> 759 <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/> 760 </reg32> 761 <reg32 offset="0x001dc" name="LDO_CNTRL"/> 762</domain> 763 764<domain name="DSI_20nm_PHY_REGULATOR" width="32"> 765 <reg32 offset="0x00000" name="CTRL_0"/> 766 <reg32 offset="0x00004" name="CTRL_1"/> 767 <reg32 offset="0x00008" name="CTRL_2"/> 768 <reg32 offset="0x0000c" name="CTRL_3"/> 769 <reg32 offset="0x00010" name="CTRL_4"/> 770 <reg32 offset="0x00014" name="CTRL_5"/> 771 <reg32 offset="0x00018" name="CAL_PWR_CFG"/> 772</domain> 773 774<domain name="DSI_14nm_PHY_CMN" width="32"> 775 <reg32 offset="0x00000" name="REVISION_ID0"/> 776 <reg32 offset="0x00004" name="REVISION_ID1"/> 777 <reg32 offset="0x00008" name="REVISION_ID2"/> 778 <reg32 offset="0x0000c" name="REVISION_ID3"/> 779 <reg32 offset="0x00010" name="CLK_CFG0"> 780 <bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/> 781 <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/> 782 </reg32> 783 <reg32 offset="0x00014" name="CLK_CFG1"> 784 <bitfield name="DSICLK_SEL" pos="0" type="boolean"/> 785 </reg32> 786 <reg32 offset="0x00018" name="GLBL_TEST_CTRL"> 787 <bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/> 788 </reg32> 789 <reg32 offset="0x0001C" name="CTRL_0"/> 790 <reg32 offset="0x00020" name="CTRL_1"> 791 </reg32> 792 <reg32 offset="0x00024" name="HW_TRIGGER"/> 793 <reg32 offset="0x00028" name="SW_CFG0"/> 794 <reg32 offset="0x0002C" name="SW_CFG1"/> 795 <reg32 offset="0x00030" name="SW_CFG2"/> 796 <reg32 offset="0x00034" name="HW_CFG0"/> 797 <reg32 offset="0x00038" name="HW_CFG1"/> 798 <reg32 offset="0x0003C" name="HW_CFG2"/> 799 <reg32 offset="0x00040" name="HW_CFG3"/> 800 <reg32 offset="0x00044" name="HW_CFG4"/> 801 <reg32 offset="0x00048" name="PLL_CNTRL"> 802 <bitfield name="PLL_START" pos="0" type="boolean"/> 803 </reg32> 804 <reg32 offset="0x0004C" name="LDO_CNTRL"> 805 <bitfield name="VREG_CTRL" low="0" high="5" type="uint"/> 806 </reg32> 807</domain> 808 809<domain name="DSI_14nm_PHY" width="32"> 810 <array offset="0x00000" name="LN" length="5" stride="0x80"> 811 <reg32 offset="0x00" name="CFG0"> 812 <bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/> 813 </reg32> 814 <reg32 offset="0x04" name="CFG1"> 815 <bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/> 816 </reg32> 817 <reg32 offset="0x08" name="CFG2"/> 818 <reg32 offset="0x0c" name="CFG3"/> 819 <reg32 offset="0x10" name="TEST_DATAPATH"/> 820 <reg32 offset="0x14" name="TEST_STR"/> 821 <reg32 offset="0x18" name="TIMING_CTRL_4"> 822 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/> 823 </reg32> 824 <reg32 offset="0x1c" name="TIMING_CTRL_5"> 825 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/> 826 </reg32> 827 <reg32 offset="0x20" name="TIMING_CTRL_6"> 828 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/> 829 </reg32> 830 <reg32 offset="0x24" name="TIMING_CTRL_7"> 831 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/> 832 </reg32> 833 <reg32 offset="0x28" name="TIMING_CTRL_8"> 834 <bitfield name="HS_RQST" low="0" high="7" type="uint"/> 835 </reg32> 836 <reg32 offset="0x2c" name="TIMING_CTRL_9"> 837 <bitfield name="TA_GO" low="0" high="2" type="uint"/> 838 <bitfield name="TA_SURE" low="4" high="6" type="uint"/> 839 </reg32> 840 <reg32 offset="0x30" name="TIMING_CTRL_10"> 841 <bitfield name="TA_GET" low="0" high="2" type="uint"/> 842 </reg32> 843 <reg32 offset="0x34" name="TIMING_CTRL_11"> 844 <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/> 845 </reg32> 846 <reg32 offset="0x38" name="STRENGTH_CTRL_0"/> 847 <reg32 offset="0x3c" name="STRENGTH_CTRL_1"/> 848 <reg32 offset="0x64" name="VREG_CNTRL"/> 849 </array> 850</domain> 851 852<domain name="DSI_14nm_PHY_PLL" width="32"> 853 <reg32 offset="0x000" name="IE_TRIM"/> 854 <reg32 offset="0x004" name="IP_TRIM"/> 855 <reg32 offset="0x010" name="IPTAT_TRIM"/> 856 <reg32 offset="0x01c" name="CLKBUFLR_EN"/> 857 <reg32 offset="0x028" name="SYSCLK_EN_RESET"/> 858 <reg32 offset="0x02c" name="RESETSM_CNTRL"/> 859 <reg32 offset="0x030" name="RESETSM_CNTRL2"/> 860 <reg32 offset="0x034" name="RESETSM_CNTRL3"/> 861 <reg32 offset="0x038" name="RESETSM_CNTRL4"/> 862 <reg32 offset="0x03c" name="RESETSM_CNTRL5"/> 863 <reg32 offset="0x040" name="KVCO_DIV_REF1"/> 864 <reg32 offset="0x044" name="KVCO_DIV_REF2"/> 865 <reg32 offset="0x048" name="KVCO_COUNT1"/> 866 <reg32 offset="0x04c" name="KVCO_COUNT2"/> 867 <reg32 offset="0x05c" name="VREF_CFG1"/> 868 <reg32 offset="0x058" name="KVCO_CODE"/> 869 <reg32 offset="0x06c" name="VCO_DIV_REF1"/> 870 <reg32 offset="0x070" name="VCO_DIV_REF2"/> 871 <reg32 offset="0x074" name="VCO_COUNT1"/> 872 <reg32 offset="0x078" name="VCO_COUNT2"/> 873 <reg32 offset="0x07c" name="PLLLOCK_CMP1"/> 874 <reg32 offset="0x080" name="PLLLOCK_CMP2"/> 875 <reg32 offset="0x084" name="PLLLOCK_CMP3"/> 876 <reg32 offset="0x088" name="PLLLOCK_CMP_EN"/> 877 <reg32 offset="0x08c" name="PLL_VCO_TUNE"/> 878 <reg32 offset="0x090" name="DEC_START"/> 879 <reg32 offset="0x094" name="SSC_EN_CENTER"/> 880 <reg32 offset="0x098" name="SSC_ADJ_PER1"/> 881 <reg32 offset="0x09c" name="SSC_ADJ_PER2"/> 882 <reg32 offset="0x0a0" name="SSC_PER1"/> 883 <reg32 offset="0x0a4" name="SSC_PER2"/> 884 <reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/> 885 <reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/> 886 <reg32 offset="0x0b4" name="DIV_FRAC_START1"/> 887 <reg32 offset="0x0b8" name="DIV_FRAC_START2"/> 888 <reg32 offset="0x0bc" name="DIV_FRAC_START3"/> 889 <reg32 offset="0x0c0" name="TXCLK_EN"/> 890 <reg32 offset="0x0c4" name="PLL_CRCTRL"/> 891 <reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/> 892 <reg32 offset="0x0e8" name="PLL_MISC1"/> 893 <reg32 offset="0x0f0" name="CP_SET_CUR"/> 894 <reg32 offset="0x0f4" name="PLL_ICPMSET"/> 895 <reg32 offset="0x0f8" name="PLL_ICPCSET"/> 896 <reg32 offset="0x0fc" name="PLL_ICP_SET"/> 897 <reg32 offset="0x100" name="PLL_LPF1"/> 898 <reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/> 899 <reg32 offset="0x108" name="PLL_BANDGAP"/> 900</domain> 901 902<domain name="DSI_10nm_PHY_CMN" width="32"> 903 <reg32 offset="0x00000" name="REVISION_ID0"/> 904 <reg32 offset="0x00004" name="REVISION_ID1"/> 905 <reg32 offset="0x00008" name="REVISION_ID2"/> 906 <reg32 offset="0x0000c" name="REVISION_ID3"/> 907 <reg32 offset="0x00010" name="CLK_CFG0"/> 908 <reg32 offset="0x00014" name="CLK_CFG1"/> 909 <reg32 offset="0x00018" name="GLBL_CTRL"/> 910 <reg32 offset="0x0001c" name="RBUF_CTRL"/> 911 <reg32 offset="0x00020" name="VREG_CTRL"/> 912 <reg32 offset="0x00024" name="CTRL_0"/> 913 <reg32 offset="0x00028" name="CTRL_1"/> 914 <reg32 offset="0x0002c" name="CTRL_2"/> 915 <reg32 offset="0x00030" name="LANE_CFG0"/> 916 <reg32 offset="0x00034" name="LANE_CFG1"/> 917 <reg32 offset="0x00038" name="PLL_CNTRL"/> 918 <reg32 offset="0x00098" name="LANE_CTRL0"/> 919 <reg32 offset="0x0009c" name="LANE_CTRL1"/> 920 <reg32 offset="0x000a0" name="LANE_CTRL2"/> 921 <reg32 offset="0x000a4" name="LANE_CTRL3"/> 922 <reg32 offset="0x000a8" name="LANE_CTRL4"/> 923 <reg32 offset="0x000ac" name="TIMING_CTRL_0"/> 924 <reg32 offset="0x000b0" name="TIMING_CTRL_1"/> 925 <reg32 offset="0x000b4" name="TIMING_CTRL_2"/> 926 <reg32 offset="0x000b8" name="TIMING_CTRL_3"/> 927 <reg32 offset="0x000bc" name="TIMING_CTRL_4"/> 928 <reg32 offset="0x000c0" name="TIMING_CTRL_5"/> 929 <reg32 offset="0x000c4" name="TIMING_CTRL_6"/> 930 <reg32 offset="0x000c8" name="TIMING_CTRL_7"/> 931 <reg32 offset="0x000cc" name="TIMING_CTRL_8"/> 932 <reg32 offset="0x000d0" name="TIMING_CTRL_9"/> 933 <reg32 offset="0x000d4" name="TIMING_CTRL_10"/> 934 <reg32 offset="0x000d8" name="TIMING_CTRL_11"/> 935 <reg32 offset="0x000ec" name="PHY_STATUS"/> 936 <reg32 offset="0x000f4" name="LANE_STATUS0"/> 937 <reg32 offset="0x000f8" name="LANE_STATUS1"/> 938</domain> 939 940<domain name="DSI_10nm_PHY" width="32"> 941 <array offset="0x00000" name="LN" length="5" stride="0x80"> 942 <reg32 offset="0x00" name="CFG0"/> 943 <reg32 offset="0x04" name="CFG1"/> 944 <reg32 offset="0x08" name="CFG2"/> 945 <reg32 offset="0x0c" name="CFG3"/> 946 <reg32 offset="0x10" name="TEST_DATAPATH"/> 947 <reg32 offset="0x14" name="PIN_SWAP"/> 948 <reg32 offset="0x18" name="HSTX_STR_CTRL"/> 949 <reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/> 950 <reg32 offset="0x20" name="OFFSET_BOT_CTRL"/> 951 <reg32 offset="0x24" name="LPTX_STR_CTRL"/> 952 <reg32 offset="0x28" name="LPRX_CTRL"/> 953 <reg32 offset="0x2c" name="TX_DCTRL"/> 954 </array> 955</domain> 956 957<domain name="DSI_10nm_PHY_PLL" width="32"> 958 <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/> 959 <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/> 960 <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/> 961 <reg32 offset="0x001c" name="DSM_DIVIDER"/> 962 <reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/> 963 <reg32 offset="0x0024" name="SYSTEM_MUXES"/> 964 <reg32 offset="0x002c" name="CMODE"/> 965 <reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/> 966 <reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/> 967 <reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/> 968 <reg32 offset="0x007c" name="PFILT"/> 969 <reg32 offset="0x0080" name="IFILT"/> 970 <reg32 offset="0x0094" name="OUTDIV"/> 971 <reg32 offset="0x00a4" name="CORE_OVERRIDE"/> 972 <reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/> 973 <reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/> 974 <reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/> 975 <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/> 976 <reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/> 977 <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/> 978 <reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/> 979 <reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/> 980 <reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/> 981 <reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/> 982 <reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/> 983 <reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/> 984 <reg32 offset="0x013c" name="SSC_CONTROL"/> 985 <reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/> 986 <reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/> 987 <reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/> 988 <reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/> 989 <reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/> 990 <reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/> 991 <reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/> 992 <reg32 offset="0x0184" name="PLL_LOCK_DELAY"/> 993 <reg32 offset="0x018c" name="CLOCK_INVERTERS"/> 994 <reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/> 995</domain> 996 997<domain name="DSI_7nm_PHY_CMN" width="32"> 998 <reg32 offset="0x00000" name="REVISION_ID0"/> 999 <reg32 offset="0x00004" name="REVISION_ID1"/> 1000 <reg32 offset="0x00008" name="REVISION_ID2"/> 1001 <reg32 offset="0x0000c" name="REVISION_ID3"/> 1002 <reg32 offset="0x00010" name="CLK_CFG0"/> 1003 <reg32 offset="0x00014" name="CLK_CFG1"/> 1004 <reg32 offset="0x00018" name="GLBL_CTRL"/> 1005 <reg32 offset="0x0001c" name="RBUF_CTRL"/> 1006 <reg32 offset="0x00020" name="VREG_CTRL_0"/> 1007 <reg32 offset="0x00024" name="CTRL_0"/> 1008 <reg32 offset="0x00028" name="CTRL_1"/> 1009 <reg32 offset="0x0002c" name="CTRL_2"/> 1010 <reg32 offset="0x00030" name="CTRL_3"/> 1011 <reg32 offset="0x00034" name="LANE_CFG0"/> 1012 <reg32 offset="0x00038" name="LANE_CFG1"/> 1013 <reg32 offset="0x0003c" name="PLL_CNTRL"/> 1014 <reg32 offset="0x00040" name="DPHY_SOT"/> 1015 <reg32 offset="0x000a0" name="LANE_CTRL0"/> 1016 <reg32 offset="0x000a4" name="LANE_CTRL1"/> 1017 <reg32 offset="0x000a8" name="LANE_CTRL2"/> 1018 <reg32 offset="0x000ac" name="LANE_CTRL3"/> 1019 <reg32 offset="0x000b0" name="LANE_CTRL4"/> 1020 <reg32 offset="0x000b4" name="TIMING_CTRL_0"/> 1021 <reg32 offset="0x000b8" name="TIMING_CTRL_1"/> 1022 <reg32 offset="0x000bc" name="TIMING_CTRL_2"/> 1023 <reg32 offset="0x000c0" name="TIMING_CTRL_3"/> 1024 <reg32 offset="0x000c4" name="TIMING_CTRL_4"/> 1025 <reg32 offset="0x000c8" name="TIMING_CTRL_5"/> 1026 <reg32 offset="0x000cc" name="TIMING_CTRL_6"/> 1027 <reg32 offset="0x000d0" name="TIMING_CTRL_7"/> 1028 <reg32 offset="0x000d4" name="TIMING_CTRL_8"/> 1029 <reg32 offset="0x000d8" name="TIMING_CTRL_9"/> 1030 <reg32 offset="0x000dc" name="TIMING_CTRL_10"/> 1031 <reg32 offset="0x000e0" name="TIMING_CTRL_11"/> 1032 <reg32 offset="0x000e4" name="TIMING_CTRL_12"/> 1033 <reg32 offset="0x000e8" name="TIMING_CTRL_13"/> 1034 <reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/> 1035 <reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/> 1036 <reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/> 1037 <reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/> 1038 <reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/> 1039 <reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/> 1040 <reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/> 1041 <reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/> 1042 <reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/> 1043 <reg32 offset="0x00110" name="VREG_CTRL_1"/> 1044 <reg32 offset="0x00114" name="CTRL_4"/> 1045 <reg32 offset="0x00128" name="GLBL_DIGTOP_SPARE4"/> 1046 <reg32 offset="0x00140" name="PHY_STATUS"/> 1047 <reg32 offset="0x00148" name="LANE_STATUS0"/> 1048 <reg32 offset="0x0014c" name="LANE_STATUS1"/> 1049</domain> 1050 1051<domain name="DSI_7nm_PHY" width="32"> 1052 <array offset="0x00000" name="LN" length="5" stride="0x80"> 1053 <reg32 offset="0x00" name="CFG0"/> 1054 <reg32 offset="0x04" name="CFG1"/> 1055 <reg32 offset="0x08" name="CFG2"/> 1056 <reg32 offset="0x0c" name="TEST_DATAPATH"/> 1057 <reg32 offset="0x10" name="PIN_SWAP"/> 1058 <reg32 offset="0x14" name="LPRX_CTRL"/> 1059 <reg32 offset="0x18" name="TX_DCTRL"/> 1060 </array> 1061</domain> 1062 1063<domain name="DSI_7nm_PHY_PLL" width="32"> 1064 <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/> 1065 <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/> 1066 <reg32 offset="0x0008" name="INT_LOOP_SETTINGS"/> 1067 <reg32 offset="0x000c" name="INT_LOOP_SETTINGS_TWO"/> 1068 <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/> 1069 <reg32 offset="0x0014" name="ANALOG_CONTROLS_FOUR"/> 1070 <reg32 offset="0x0018" name="ANALOG_CONTROLS_FIVE"/> 1071 <reg32 offset="0x001c" name="INT_LOOP_CONTROLS"/> 1072 <reg32 offset="0x0020" name="DSM_DIVIDER"/> 1073 <reg32 offset="0x0024" name="FEEDBACK_DIVIDER"/> 1074 <reg32 offset="0x0028" name="SYSTEM_MUXES"/> 1075 <reg32 offset="0x002c" name="FREQ_UPDATE_CONTROL_OVERRIDES"/> 1076 <reg32 offset="0x0030" name="CMODE"/> 1077 <reg32 offset="0x0034" name="PSM_CTRL"/> 1078 <reg32 offset="0x0038" name="RSM_CTRL"/> 1079 <reg32 offset="0x003c" name="VCO_TUNE_MAP"/> 1080 <reg32 offset="0x0040" name="PLL_CNTRL"/> 1081 <reg32 offset="0x0044" name="CALIBRATION_SETTINGS"/> 1082 <reg32 offset="0x0048" name="BAND_SEL_CAL_TIMER_LOW"/> 1083 <reg32 offset="0x004c" name="BAND_SEL_CAL_TIMER_HIGH"/> 1084 <reg32 offset="0x0050" name="BAND_SEL_CAL_SETTINGS"/> 1085 <reg32 offset="0x0054" name="BAND_SEL_MIN"/> 1086 <reg32 offset="0x0058" name="BAND_SEL_MAX"/> 1087 <reg32 offset="0x005c" name="BAND_SEL_PFILT"/> 1088 <reg32 offset="0x0060" name="BAND_SEL_IFILT"/> 1089 <reg32 offset="0x0064" name="BAND_SEL_CAL_SETTINGS_TWO"/> 1090 <reg32 offset="0x0068" name="BAND_SEL_CAL_SETTINGS_THREE"/> 1091 <reg32 offset="0x006c" name="BAND_SEL_CAL_SETTINGS_FOUR"/> 1092 <reg32 offset="0x0070" name="BAND_SEL_ICODE_HIGH"/> 1093 <reg32 offset="0x0074" name="BAND_SEL_ICODE_LOW"/> 1094 <reg32 offset="0x0078" name="FREQ_DETECT_SETTINGS_ONE"/> 1095 <reg32 offset="0x007c" name="FREQ_DETECT_THRESH"/> 1096 <reg32 offset="0x0080" name="FREQ_DET_REFCLK_HIGH"/> 1097 <reg32 offset="0x0084" name="FREQ_DET_REFCLK_LOW"/> 1098 <reg32 offset="0x0088" name="FREQ_DET_PLLCLK_HIGH"/> 1099 <reg32 offset="0x008c" name="FREQ_DET_PLLCLK_LOW"/> 1100 <reg32 offset="0x0090" name="PFILT"/> 1101 <reg32 offset="0x0094" name="IFILT"/> 1102 <reg32 offset="0x0098" name="PLL_GAIN"/> 1103 <reg32 offset="0x009c" name="ICODE_LOW"/> 1104 <reg32 offset="0x00a0" name="ICODE_HIGH"/> 1105 <reg32 offset="0x00a4" name="LOCKDET"/> 1106 <reg32 offset="0x00a8" name="OUTDIV"/> 1107 <reg32 offset="0x00ac" name="FASTLOCK_CONTROL"/> 1108 <reg32 offset="0x00b0" name="PASS_OUT_OVERRIDE_ONE"/> 1109 <reg32 offset="0x00b4" name="PASS_OUT_OVERRIDE_TWO"/> 1110 <reg32 offset="0x00b8" name="CORE_OVERRIDE"/> 1111 <reg32 offset="0x00bc" name="CORE_INPUT_OVERRIDE"/> 1112 <reg32 offset="0x00c0" name="RATE_CHANGE"/> 1113 <reg32 offset="0x00c4" name="PLL_DIGITAL_TIMERS"/> 1114 <reg32 offset="0x00c8" name="PLL_DIGITAL_TIMERS_TWO"/> 1115 <reg32 offset="0x00cc" name="DECIMAL_DIV_START"/> 1116 <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW"/> 1117 <reg32 offset="0x00d4" name="FRAC_DIV_START_MID"/> 1118 <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH"/> 1119 <reg32 offset="0x00dc" name="DEC_FRAC_MUXES"/> 1120 <reg32 offset="0x00e0" name="DECIMAL_DIV_START_1"/> 1121 <reg32 offset="0x00e4" name="FRAC_DIV_START_LOW_1"/> 1122 <reg32 offset="0x00e8" name="FRAC_DIV_START_MID_1"/> 1123 <reg32 offset="0x00ec" name="FRAC_DIV_START_HIGH_1"/> 1124 <reg32 offset="0x00f0" name="DECIMAL_DIV_START_2"/> 1125 <reg32 offset="0x00f4" name="FRAC_DIV_START_LOW_2"/> 1126 <reg32 offset="0x00f8" name="FRAC_DIV_START_MID_2"/> 1127 <reg32 offset="0x00fc" name="FRAC_DIV_START_HIGH_2"/> 1128 <reg32 offset="0x0100" name="MASH_CONTROL"/> 1129 <reg32 offset="0x0104" name="SSC_STEPSIZE_LOW"/> 1130 <reg32 offset="0x0108" name="SSC_STEPSIZE_HIGH"/> 1131 <reg32 offset="0x010c" name="SSC_DIV_PER_LOW"/> 1132 <reg32 offset="0x0110" name="SSC_DIV_PER_HIGH"/> 1133 <reg32 offset="0x0114" name="SSC_ADJPER_LOW"/> 1134 <reg32 offset="0x0118" name="SSC_ADJPER_HIGH"/> 1135 <reg32 offset="0x011c" name="SSC_MUX_CONTROL"/> 1136 <reg32 offset="0x0120" name="SSC_STEPSIZE_LOW_1"/> 1137 <reg32 offset="0x0124" name="SSC_STEPSIZE_HIGH_1"/> 1138 <reg32 offset="0x0128" name="SSC_DIV_PER_LOW_1"/> 1139 <reg32 offset="0x012c" name="SSC_DIV_PER_HIGH_1"/> 1140 <reg32 offset="0x0130" name="SSC_ADJPER_LOW_1"/> 1141 <reg32 offset="0x0134" name="SSC_ADJPER_HIGH_1"/> 1142 <reg32 offset="0x0138" name="SSC_STEPSIZE_LOW_2"/> 1143 <reg32 offset="0x013c" name="SSC_STEPSIZE_HIGH_2"/> 1144 <reg32 offset="0x0140" name="SSC_DIV_PER_LOW_2"/> 1145 <reg32 offset="0x0144" name="SSC_DIV_PER_HIGH_2"/> 1146 <reg32 offset="0x0148" name="SSC_ADJPER_LOW_2"/> 1147 <reg32 offset="0x014c" name="SSC_ADJPER_HIGH_2"/> 1148 <reg32 offset="0x0150" name="SSC_CONTROL"/> 1149 <reg32 offset="0x0154" name="PLL_OUTDIV_RATE"/> 1150 <reg32 offset="0x0158" name="PLL_LOCKDET_RATE_1"/> 1151 <reg32 offset="0x015c" name="PLL_LOCKDET_RATE_2"/> 1152 <reg32 offset="0x0160" name="PLL_PROP_GAIN_RATE_1"/> 1153 <reg32 offset="0x0164" name="PLL_PROP_GAIN_RATE_2"/> 1154 <reg32 offset="0x0168" name="PLL_BAND_SEL_RATE_1"/> 1155 <reg32 offset="0x016c" name="PLL_BAND_SEL_RATE_2"/> 1156 <reg32 offset="0x0170" name="PLL_INT_GAIN_IFILT_BAND_1"/> 1157 <reg32 offset="0x0174" name="PLL_INT_GAIN_IFILT_BAND_2"/> 1158 <reg32 offset="0x0178" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/> 1159 <reg32 offset="0x017c" name="PLL_FL_INT_GAIN_PFILT_BAND_2"/> 1160 <reg32 offset="0x0180" name="PLL_FASTLOCK_EN_BAND"/> 1161 <reg32 offset="0x0184" name="FREQ_TUNE_ACCUM_INIT_MID"/> 1162 <reg32 offset="0x0188" name="FREQ_TUNE_ACCUM_INIT_HIGH"/> 1163 <reg32 offset="0x018c" name="FREQ_TUNE_ACCUM_INIT_MUX"/> 1164 <reg32 offset="0x0190" name="PLL_LOCK_OVERRIDE"/> 1165 <reg32 offset="0x0194" name="PLL_LOCK_DELAY"/> 1166 <reg32 offset="0x0198" name="PLL_LOCK_MIN_DELAY"/> 1167 <reg32 offset="0x019c" name="CLOCK_INVERTERS"/> 1168 <reg32 offset="0x01a0" name="SPARE_AND_JPC_OVERRIDES"/> 1169 <reg32 offset="0x01a4" name="BIAS_CONTROL_1"/> 1170 <reg32 offset="0x01a8" name="BIAS_CONTROL_2"/> 1171 <reg32 offset="0x01ac" name="ALOG_OBSV_BUS_CTRL_1"/> 1172 <reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/> 1173 <reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/> 1174 <reg32 offset="0x01b8" name="BAND_SEL_CAL"/> 1175 <reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/> 1176 <reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/> 1177 <reg32 offset="0x01c4" name="FD_OUT_LOW"/> 1178 <reg32 offset="0x01c8" name="FD_OUT_HIGH"/> 1179 <reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/> 1180 <reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/> 1181 <reg32 offset="0x01d4" name="FLL_CONFIG"/> 1182 <reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/> 1183 <reg32 offset="0x01dc" name="FLL_CODE0"/> 1184 <reg32 offset="0x01e0" name="FLL_CODE1"/> 1185 <reg32 offset="0x01e4" name="FLL_GAIN0"/> 1186 <reg32 offset="0x01e8" name="FLL_GAIN1"/> 1187 <reg32 offset="0x01ec" name="SW_RESET"/> 1188 <reg32 offset="0x01f0" name="FAST_PWRUP"/> 1189 <reg32 offset="0x01f4" name="LOCKTIME0"/> 1190 <reg32 offset="0x01f8" name="LOCKTIME1"/> 1191 <reg32 offset="0x01fc" name="DEBUG_BUS_SEL"/> 1192 <reg32 offset="0x0200" name="DEBUG_BUS0"/> 1193 <reg32 offset="0x0204" name="DEBUG_BUS1"/> 1194 <reg32 offset="0x0208" name="DEBUG_BUS2"/> 1195 <reg32 offset="0x020c" name="DEBUG_BUS3"/> 1196 <reg32 offset="0x0210" name="ANALOG_FLL_CONTROL_OVERRIDES"/> 1197 <reg32 offset="0x0214" name="VCO_CONFIG"/> 1198 <reg32 offset="0x0218" name="VCO_CAL_CODE1_MODE0_STATUS"/> 1199 <reg32 offset="0x021c" name="VCO_CAL_CODE1_MODE1_STATUS"/> 1200 <reg32 offset="0x0220" name="RESET_SM_STATUS"/> 1201 <reg32 offset="0x0224" name="TDC_OFFSET"/> 1202 <reg32 offset="0x0228" name="PS3_PWRDOWN_CONTROLS"/> 1203 <reg32 offset="0x022c" name="PS4_PWRDOWN_CONTROLS"/> 1204 <reg32 offset="0x0230" name="PLL_RST_CONTROLS"/> 1205 <reg32 offset="0x0234" name="GEAR_BAND_SELECT_CONTROLS"/> 1206 <reg32 offset="0x0238" name="PSM_CLK_CONTROLS"/> 1207 <reg32 offset="0x023c" name="SYSTEM_MUXES_2"/> 1208 <reg32 offset="0x0240" name="VCO_CONFIG_1"/> 1209 <reg32 offset="0x0244" name="VCO_CONFIG_2"/> 1210 <reg32 offset="0x0248" name="CLOCK_INVERTERS_1"/> 1211 <reg32 offset="0x024c" name="CLOCK_INVERTERS_2"/> 1212 <reg32 offset="0x0250" name="CMODE_1"/> 1213 <reg32 offset="0x0254" name="CMODE_2"/> 1214 <reg32 offset="0x0258" name="ANALOG_CONTROLS_FIVE_1"/> 1215 <reg32 offset="0x025c" name="ANALOG_CONTROLS_FIVE_2"/> 1216 <reg32 offset="0x0260" name="PERF_OPTIMIZE"/> 1217</domain> 1218 1219</database> 1220