1 //! Implementations for the [RISC-V](https://riscv.org/) architecture. 2 //! 3 //! *Note*: currently only supports integer versions of the ISA. 4 5 use crate::arch::Arch; 6 7 pub mod reg; 8 9 /// Implements `Arch` for 32-bit RISC-V. 10 pub enum Riscv32 {} 11 12 /// Implements `Arch` for 64-bit RISC-V. 13 pub enum Riscv64 {} 14 15 impl Arch for Riscv32 { 16 type Usize = u32; 17 type Registers = reg::RiscvCoreRegs<u32>; 18 type RegId = reg::id::RiscvRegId; 19 target_description_xml() -> Option<&'static str>20 fn target_description_xml() -> Option<&'static str> { 21 Some(r#"<target version="1.0"><architecture>riscv</architecture></target>"#) 22 } 23 } 24 25 impl Arch for Riscv64 { 26 type Usize = u64; 27 type Registers = reg::RiscvCoreRegs<u64>; 28 type RegId = reg::id::RiscvRegId; 29 target_description_xml() -> Option<&'static str>30 fn target_description_xml() -> Option<&'static str> { 31 Some(r#"<target version="1.0"><architecture>riscv64</architecture></target>"#) 32 } 33 } 34