1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This declares the Emit routines for the SelectionDAG class, which creates 10 // MachineInstrs based on the decisions of the SelectionDAG instruction 11 // selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 22 namespace llvm { 23 24 class MachineInstrBuilder; 25 class MCInstrDesc; 26 class SDDbgValue; 27 28 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 29 MachineFunction *MF; 30 MachineRegisterInfo *MRI; 31 const TargetInstrInfo *TII; 32 const TargetRegisterInfo *TRI; 33 const TargetLowering *TLI; 34 35 MachineBasicBlock *MBB; 36 MachineBasicBlock::iterator InsertPos; 37 38 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 39 /// implicit physical register output. 40 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 41 bool IsClone, bool IsCloned, 42 unsigned SrcReg, 43 DenseMap<SDValue, unsigned> &VRBaseMap); 44 45 void CreateVirtualRegisters(SDNode *Node, 46 MachineInstrBuilder &MIB, 47 const MCInstrDesc &II, 48 bool IsClone, bool IsCloned, 49 DenseMap<SDValue, unsigned> &VRBaseMap); 50 51 /// getVR - Return the virtual register corresponding to the specified result 52 /// of the specified node. 53 unsigned getVR(SDValue Op, 54 DenseMap<SDValue, unsigned> &VRBaseMap); 55 56 /// AddRegisterOperand - Add the specified register as an operand to the 57 /// specified machine instr. Insert register copies if the register is 58 /// not in the required register class. 59 void AddRegisterOperand(MachineInstrBuilder &MIB, 60 SDValue Op, 61 unsigned IIOpNum, 62 const MCInstrDesc *II, 63 DenseMap<SDValue, unsigned> &VRBaseMap, 64 bool IsDebug, bool IsClone, bool IsCloned); 65 66 /// AddOperand - Add the specified operand to the specified machine instr. II 67 /// specifies the instruction information for the node, and IIOpNum is the 68 /// operand number (in the II) that we are adding. IIOpNum and II are used for 69 /// assertions only. 70 void AddOperand(MachineInstrBuilder &MIB, 71 SDValue Op, 72 unsigned IIOpNum, 73 const MCInstrDesc *II, 74 DenseMap<SDValue, unsigned> &VRBaseMap, 75 bool IsDebug, bool IsClone, bool IsCloned); 76 77 /// ConstrainForSubReg - Try to constrain VReg to a register class that 78 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 79 /// Return the virtual register to use. 80 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT, 81 bool isDivergent, const DebugLoc &DL); 82 83 /// EmitSubregNode - Generate machine code for subreg nodes. 84 /// 85 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 86 bool IsClone, bool IsCloned); 87 88 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 89 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 90 /// register is constrained to be in a particular register class. 91 /// 92 void EmitCopyToRegClassNode(SDNode *Node, 93 DenseMap<SDValue, unsigned> &VRBaseMap); 94 95 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 96 /// 97 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 98 bool IsClone, bool IsCloned); 99 public: 100 /// CountResults - The results of target nodes have register or immediate 101 /// operands first, then an optional chain, and optional flag operands 102 /// (which do not go into the machine instrs.) 103 static unsigned CountResults(SDNode *Node); 104 105 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 106 /// 107 MachineInstr *EmitDbgValue(SDDbgValue *SD, 108 DenseMap<SDValue, unsigned> &VRBaseMap); 109 110 /// Generate machine instruction for a dbg_label node. 111 MachineInstr *EmitDbgLabel(SDDbgLabel *SD); 112 113 /// EmitNode - Generate machine code for a node and needed dependencies. 114 /// EmitNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,unsigned> & VRBaseMap)115 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 116 DenseMap<SDValue, unsigned> &VRBaseMap) { 117 if (Node->isMachineOpcode()) 118 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 119 else 120 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 121 } 122 123 /// getBlock - Return the current basic block. getBlock()124 MachineBasicBlock *getBlock() { return MBB; } 125 126 /// getInsertPos - Return the current insertion position. getInsertPos()127 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 128 129 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 130 /// at the given position in the given block. 131 InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); 132 133 private: 134 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 135 DenseMap<SDValue, unsigned> &VRBaseMap); 136 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 137 DenseMap<SDValue, unsigned> &VRBaseMap); 138 }; 139 140 } 141 142 #endif 143