1//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach 10// below is to define a generic SchedWriteRes for every combination of 11// latency and microOps. The naming conventions is to use a prefix, one field 12// for latency, and one or more microOp count/type designators. 13// Prefix: A57Write 14// Latency: #cyc 15// MicroOp Count/Types: #(B|I|M|L|S|X|W|V) 16// 17// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are 18// 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes. 19// 20//===----------------------------------------------------------------------===// 21 22//===----------------------------------------------------------------------===// 23// Define Generic 1 micro-op types 24 25def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; } 26def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; } 27def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; } 28def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 29def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; } 30def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17; 31 let ResourceCycles = [17]; } 32def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; 33 let ResourceCycles = [19]; } 34def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } 35def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } 36def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } 37def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } 38def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32; 39 let ResourceCycles = [32]; } 40def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; 41 let ResourceCycles = [35]; } 42def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; } 43def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; } 44def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; } 45def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; } 46def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; } 47def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 48def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 49def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } 50def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; } 51 52 53//===----------------------------------------------------------------------===// 54// Define Generic 2 micro-op types 55 56def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 57 let Latency = 64; 58 let NumMicroOps = 2; 59 let ResourceCycles = [32, 32]; 60} 61def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI, 62 A57UnitL]> { 63 let Latency = 6; 64 let NumMicroOps = 2; 65} 66def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV, 67 A57UnitX]> { 68 let Latency = 7; 69 let NumMicroOps = 2; 70} 71def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL, 72 A57UnitV]> { 73 let Latency = 8; 74 let NumMicroOps = 2; 75} 76def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 77 let Latency = 9; 78 let NumMicroOps = 2; 79} 80def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 81 let Latency = 8; 82 let NumMicroOps = 2; 83} 84def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> { 85 let Latency = 6; 86 let NumMicroOps = 2; 87} 88def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 89 let Latency = 6; 90 let NumMicroOps = 2; 91} 92def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 93 let Latency = 6; 94 let NumMicroOps = 2; 95} 96def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI, 97 A57UnitL]> { 98 let Latency = 5; 99 let NumMicroOps = 2; 100} 101def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 102 let Latency = 5; 103 let NumMicroOps = 2; 104} 105def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 106 let Latency = 5; 107 let NumMicroOps = 2; 108} 109def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL, 110 A57UnitV]> { 111 let Latency = 10; 112 let NumMicroOps = 2; 113} 114def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 115 let Latency = 10; 116 let NumMicroOps = 2; 117} 118def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB, 119 A57UnitI]> { 120 let Latency = 1; 121 let NumMicroOps = 2; 122} 123def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI, 124 A57UnitS]> { 125 let Latency = 1; 126 let NumMicroOps = 2; 127} 128def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB, 129 A57UnitI]> { 130 let Latency = 2; 131 let NumMicroOps = 2; 132} 133def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> { 134 let Latency = 2; 135 let NumMicroOps = 2; 136} 137def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 138 let Latency = 2; 139 let NumMicroOps = 2; 140} 141def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { 142 let Latency = 34; 143 let NumMicroOps = 2; 144 let ResourceCycles = [17, 17]; 145} 146def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI, 147 A57UnitM]> { 148 let Latency = 3; 149 let NumMicroOps = 2; 150} 151def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI, 152 A57UnitS]> { 153 let Latency = 3; 154 let NumMicroOps = 2; 155} 156def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS, 157 A57UnitV]> { 158 let Latency = 3; 159 let NumMicroOps = 2; 160} 161def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { 162 let Latency = 3; 163 let NumMicroOps = 2; 164} 165def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI, 166 A57UnitL]> { 167 let Latency = 4; 168 let NumMicroOps = 2; 169} 170def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { 171 let Latency = 4; 172 let NumMicroOps = 2; 173} 174 175 176//===----------------------------------------------------------------------===// 177// Define Generic 3 micro-op types 178 179def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 180 let Latency = 10; 181 let NumMicroOps = 3; 182} 183def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI, 184 A57UnitS, A57UnitS]> { 185 let Latency = 2; 186 let NumMicroOps = 3; 187} 188def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI, 189 A57UnitS, 190 A57UnitV]> { 191 let Latency = 3; 192 let NumMicroOps = 3; 193} 194def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM, 195 A57UnitS, A57UnitS]> { 196 let Latency = 3; 197 let NumMicroOps = 3; 198} 199def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> { 200 let Latency = 3; 201 let NumMicroOps = 3; 202} 203def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS, 204 A57UnitV]> { 205 let Latency = 3; 206 let NumMicroOps = 3; 207} 208def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI, 209 A57UnitL, A57UnitL]> { 210 let Latency = 5; 211 let NumMicroOps = 3; 212} 213def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI, 214 A57UnitL, A57UnitL]> { 215 let Latency = 6; 216 let NumMicroOps = 3; 217} 218def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 219 let Latency = 6; 220 let NumMicroOps = 3; 221} 222def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> { 223 let Latency = 7; 224 let NumMicroOps = 3; 225} 226def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI, 227 A57UnitL, 228 A57UnitV]> { 229 let Latency = 8; 230 let NumMicroOps = 3; 231} 232def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL, 233 A57UnitV, A57UnitV]> { 234 let Latency = 8; 235 let NumMicroOps = 3; 236} 237def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 238 let Latency = 8; 239 let NumMicroOps = 3; 240} 241def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { 242 let Latency = 9; 243 let NumMicroOps = 3; 244} 245 246 247//===----------------------------------------------------------------------===// 248// Define Generic 4 micro-op types 249 250def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 251 A57UnitS, A57UnitS]> { 252 let Latency = 2; 253 let NumMicroOps = 4; 254} 255def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, 256 A57UnitS, A57UnitS]> { 257 let Latency = 3; 258 let NumMicroOps = 4; 259} 260def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI, 261 A57UnitS, A57UnitS, A57UnitS]> { 262 let Latency = 3; 263 let NumMicroOps = 4; 264} 265def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI, 266 A57UnitS, A57UnitS, 267 A57UnitV]> { 268 let Latency = 3; 269 let NumMicroOps = 4; 270} 271def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS, 272 A57UnitS, A57UnitS]> { 273 let Latency = 4; 274 let NumMicroOps = 4; 275} 276def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI, 277 A57UnitL, A57UnitL, A57UnitL]> { 278 let Latency = 7; 279 let NumMicroOps = 4; 280} 281def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI, 282 A57UnitL, A57UnitL]> { 283 let Latency = 5; 284 let NumMicroOps = 4; 285} 286def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI, 287 A57UnitL, 288 A57UnitV, A57UnitV]> { 289 let Latency = 8; 290 let NumMicroOps = 4; 291} 292def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL, 293 A57UnitL, A57UnitL]> { 294 let Latency = 8; 295 let NumMicroOps = 4; 296} 297def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL, 298 A57UnitV, A57UnitV]> { 299 let Latency = 9; 300 let NumMicroOps = 4; 301} 302def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL, 303 A57UnitV, A57UnitV, A57UnitV]> { 304 let Latency = 9; 305 let NumMicroOps = 4; 306} 307def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV, 308 A57UnitV, A57UnitV]> { 309 let Latency = 12; 310 let NumMicroOps = 4; 311} 312 313 314//===----------------------------------------------------------------------===// 315// Define Generic 5 micro-op types 316 317def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 318 A57UnitV, A57UnitV]> { 319 let Latency = 3; 320 let NumMicroOps = 5; 321} 322def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI, 323 A57UnitL, A57UnitL, 324 A57UnitL, A57UnitL]> { 325 let Latency = 8; 326 let NumMicroOps = 5; 327} 328def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI, 329 A57UnitS, A57UnitS, 330 A57UnitS, A57UnitS]> { 331 let Latency = 4; 332 let NumMicroOps = 5; 333} 334def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI, 335 A57UnitL, A57UnitL, 336 A57UnitV, A57UnitV]> { 337 let Latency = 9; 338 let NumMicroOps = 5; 339} 340def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI, 341 A57UnitL, 342 A57UnitV, A57UnitV, A57UnitV]> { 343 let Latency = 9; 344 let NumMicroOps = 5; 345} 346def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL, 347 A57UnitV, A57UnitV, A57UnitV]> { 348 let Latency = 9; 349 let NumMicroOps = 5; 350} 351def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 352 A57UnitV, A57UnitV]> { 353 let Latency = 9; 354 let NumMicroOps = 5; 355} 356 357 358//===----------------------------------------------------------------------===// 359// Define Generic 6 micro-op types 360 361def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI, 362 A57UnitS, A57UnitS, A57UnitS, 363 A57UnitV, A57UnitV]> { 364 let Latency = 3; 365 let NumMicroOps = 6; 366} 367def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI, 368 A57UnitS, A57UnitS, 369 A57UnitS, A57UnitS]> { 370 let Latency = 4; 371 let NumMicroOps = 6; 372} 373def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS, 374 A57UnitS, A57UnitS, 375 A57UnitV, A57UnitV]> { 376 let Latency = 4; 377 let NumMicroOps = 6; 378} 379def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 380 A57UnitS, A57UnitS, A57UnitS]> { 381 let Latency = 6; 382 let NumMicroOps = 6; 383} 384def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI, 385 A57UnitL, A57UnitL, 386 A57UnitV, A57UnitV, A57UnitV]> { 387 let Latency = 9; 388 let NumMicroOps = 6; 389} 390def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI, 391 A57UnitL, 392 A57UnitV, A57UnitV, 393 A57UnitV, A57UnitV]> { 394 let Latency = 9; 395 let NumMicroOps = 6; 396} 397def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 398 A57UnitV, A57UnitV, 399 A57UnitV, A57UnitV]> { 400 let Latency = 9; 401 let NumMicroOps = 6; 402} 403 404 405//===----------------------------------------------------------------------===// 406// Define Generic 7 micro-op types 407 408def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, 409 A57UnitV, A57UnitV, 410 A57UnitV, A57UnitV]> { 411 let Latency = 10; 412 let NumMicroOps = 7; 413} 414def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI, 415 A57UnitS, A57UnitS, 416 A57UnitS, A57UnitS, 417 A57UnitV, A57UnitV]> { 418 let Latency = 4; 419 let NumMicroOps = 7; 420} 421def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI, 422 A57UnitS, A57UnitS, A57UnitS, 423 A57UnitS, A57UnitS, A57UnitS]> { 424 let Latency = 6; 425 let NumMicroOps = 7; 426} 427def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI, 428 A57UnitL, A57UnitL, 429 A57UnitV, A57UnitV, 430 A57UnitV, A57UnitV]> { 431 let Latency = 9; 432 let NumMicroOps = 7; 433} 434def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 435 A57UnitV, A57UnitV, 436 A57UnitV, A57UnitV]> { 437 let Latency = 12; 438 let NumMicroOps = 7; 439} 440 441 442//===----------------------------------------------------------------------===// 443// Define Generic 8 micro-op types 444 445def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI, 446 A57UnitL, A57UnitL, A57UnitL, 447 A57UnitV, A57UnitV, 448 A57UnitV, A57UnitV]> { 449 let Latency = 10; 450 let NumMicroOps = 8; 451} 452def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL, 453 A57UnitL, A57UnitL, 454 A57UnitV, A57UnitV, 455 A57UnitV, A57UnitV]> { 456 let Latency = 11; 457 let NumMicroOps = 8; 458} 459def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS, 460 A57UnitS, A57UnitS, 461 A57UnitS, A57UnitS, 462 A57UnitS, A57UnitS]> { 463 let Latency = 8; 464 let NumMicroOps = 8; 465} 466 467 468//===----------------------------------------------------------------------===// 469// Define Generic 9 micro-op types 470 471def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI, 472 A57UnitS, A57UnitS, 473 A57UnitS, A57UnitS, 474 A57UnitS, A57UnitS, 475 A57UnitS, A57UnitS]> { 476 let Latency = 8; 477 let NumMicroOps = 9; 478} 479def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI, 480 A57UnitL, A57UnitL, 481 A57UnitL, A57UnitL, 482 A57UnitV, A57UnitV, 483 A57UnitV, A57UnitV]> { 484 let Latency = 11; 485 let NumMicroOps = 9; 486} 487def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, 488 A57UnitV, A57UnitV, A57UnitV, 489 A57UnitV, A57UnitV, A57UnitV]> { 490 let Latency = 15; 491 let NumMicroOps = 9; 492} 493 494 495//===----------------------------------------------------------------------===// 496// Define Generic 10 micro-op types 497 498def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, 499 A57UnitS, A57UnitS, A57UnitS, 500 A57UnitV, A57UnitV, 501 A57UnitV, A57UnitV]> { 502 let Latency = 6; 503 let NumMicroOps = 10; 504} 505 506 507//===----------------------------------------------------------------------===// 508// Define Generic 11 micro-op types 509 510def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI, 511 A57UnitS, A57UnitS, A57UnitS, 512 A57UnitS, A57UnitS, A57UnitS, 513 A57UnitV, A57UnitV, 514 A57UnitV, A57UnitV]> { 515 let Latency = 6; 516 let NumMicroOps = 11; 517} 518 519 520//===----------------------------------------------------------------------===// 521// Define Generic 12 micro-op types 522 523def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, 524 A57UnitS, A57UnitS, A57UnitS, A57UnitS, 525 A57UnitV, A57UnitV, 526 A57UnitV, A57UnitV]> { 527 let Latency = 8; 528 let NumMicroOps = 12; 529} 530 531//===----------------------------------------------------------------------===// 532// Define Generic 13 micro-op types 533 534def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI, 535 A57UnitS, A57UnitS, A57UnitS, 536 A57UnitS, A57UnitS, A57UnitS, 537 A57UnitS, A57UnitS, 538 A57UnitV, A57UnitV, 539 A57UnitV, A57UnitV]> { 540 let Latency = 8; 541 let NumMicroOps = 13; 542} 543 544