1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-simulator-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35
36
37 #include "test-runner.h"
38
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/disasm-aarch32.h"
44 #include "aarch32/macro-assembler-aarch32.h"
45
46 #define __ masm.
47 #define BUF_SIZE (4096)
48
49 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
50 // Run tests with the simulator.
51
52 #define SETUP() MacroAssembler masm(BUF_SIZE)
53
54 #define START() masm.GetBuffer()->Reset()
55
56 #define END() \
57 __ Hlt(0); \
58 __ FinalizeCode();
59
60 // TODO: Run the tests in the simulator.
61 #define RUN()
62
63 #else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
64
65 #define SETUP() \
66 MacroAssembler masm(BUF_SIZE); \
67 UseScratchRegisterScope harness_scratch;
68
69 #define START() \
70 harness_scratch.Open(&masm); \
71 harness_scratch.ExcludeAll(); \
72 masm.GetBuffer()->Reset(); \
73 __ Push(r4); \
74 __ Push(r5); \
75 __ Push(r6); \
76 __ Push(r7); \
77 __ Push(r8); \
78 __ Push(r9); \
79 __ Push(r10); \
80 __ Push(r11); \
81 __ Push(lr); \
82 harness_scratch.Include(ip);
83
84 #define END() \
85 harness_scratch.Exclude(ip); \
86 __ Pop(lr); \
87 __ Pop(r11); \
88 __ Pop(r10); \
89 __ Pop(r9); \
90 __ Pop(r8); \
91 __ Pop(r7); \
92 __ Pop(r6); \
93 __ Pop(r5); \
94 __ Pop(r4); \
95 __ Bx(lr); \
96 __ FinalizeCode(); \
97 harness_scratch.Close();
98
99 #define RUN() \
100 { \
101 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \
102 masm.GetBuffer()->SetExecutable(); \
103 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \
104 masm.GetSizeOfCodeGenerated(), \
105 pcs_offset); \
106 masm.GetBuffer()->SetWritable(); \
107 }
108
109 #endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
110
111 namespace vixl {
112 namespace aarch32 {
113
114 // List of instruction encodings:
115 #define FOREACH_INSTRUCTION(M) \
116 M(Cmn) \
117 M(Cmp) \
118 M(Mov) \
119 M(Movs) \
120 M(Mvn) \
121 M(Mvns) \
122 M(Teq) \
123 M(Tst)
124
125
126 // The following definitions are defined again in each generated test, therefore
127 // we need to place them in an anomymous namespace. It expresses that they are
128 // local to this file only, and the compiler is not allowed to share these types
129 // across test files during template instantiation. Specifically, `Operands` and
130 // `Inputs` have various layouts across generated tests so they absolutely
131 // cannot be shared.
132
133 #ifdef VIXL_INCLUDE_TARGET_A32
134 namespace {
135
136 // Values to be passed to the assembler to produce the instruction under test.
137 struct Operands {
138 Condition cond;
139 Register rd;
140 Register rn;
141 ShiftType shift;
142 uint32_t amount;
143 };
144
145 // Input data to feed to the instruction.
146 struct Inputs {
147 uint32_t apsr;
148 uint32_t rd;
149 uint32_t rn;
150 };
151
152 // This structure contains all input data needed to test one specific encoding.
153 // It used to generate a loop over an instruction.
154 struct TestLoopData {
155 // The `operands` fields represents the values to pass to the assembler to
156 // produce the instruction.
157 Operands operands;
158 // Description of the operands, used for error reporting.
159 const char* operands_description;
160 // Unique identifier, used for generating traces.
161 const char* identifier;
162 // Array of values to be fed to the instruction.
163 size_t input_size;
164 const Inputs* inputs;
165 };
166
167 static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab},
168 {ZFlag, 0xabababab, 0xabababab},
169 {CFlag, 0xabababab, 0xabababab},
170 {VFlag, 0xabababab, 0xabababab},
171 {NZFlag, 0xabababab, 0xabababab},
172 {NCFlag, 0xabababab, 0xabababab},
173 {NVFlag, 0xabababab, 0xabababab},
174 {ZCFlag, 0xabababab, 0xabababab},
175 {ZVFlag, 0xabababab, 0xabababab},
176 {CVFlag, 0xabababab, 0xabababab},
177 {NZCFlag, 0xabababab, 0xabababab},
178 {NZVFlag, 0xabababab, 0xabababab},
179 {NCVFlag, 0xabababab, 0xabababab},
180 {ZCVFlag, 0xabababab, 0xabababab},
181 {NZCVFlag, 0xabababab, 0xabababab}};
182
183 static const Inputs kRdIsRn[] =
184 {{NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x00000001, 0x00000001},
185 {NoFlag, 0x00000002, 0x00000002}, {NoFlag, 0x00000020, 0x00000020},
186 {NoFlag, 0x0000007d, 0x0000007d}, {NoFlag, 0x0000007e, 0x0000007e},
187 {NoFlag, 0x0000007f, 0x0000007f}, {NoFlag, 0x00007ffd, 0x00007ffd},
188 {NoFlag, 0x00007ffe, 0x00007ffe}, {NoFlag, 0x00007fff, 0x00007fff},
189 {NoFlag, 0x33333333, 0x33333333}, {NoFlag, 0x55555555, 0x55555555},
190 {NoFlag, 0x7ffffffd, 0x7ffffffd}, {NoFlag, 0x7ffffffe, 0x7ffffffe},
191 {NoFlag, 0x7fffffff, 0x7fffffff}, {NoFlag, 0x80000000, 0x80000000},
192 {NoFlag, 0x80000001, 0x80000001}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
193 {NoFlag, 0xcccccccc, 0xcccccccc}, {NoFlag, 0xffff8000, 0xffff8000},
194 {NoFlag, 0xffff8001, 0xffff8001}, {NoFlag, 0xffff8002, 0xffff8002},
195 {NoFlag, 0xffff8003, 0xffff8003}, {NoFlag, 0xffffff80, 0xffffff80},
196 {NoFlag, 0xffffff81, 0xffffff81}, {NoFlag, 0xffffff82, 0xffffff82},
197 {NoFlag, 0xffffff83, 0xffffff83}, {NoFlag, 0xffffffe0, 0xffffffe0},
198 {NoFlag, 0xfffffffd, 0xfffffffd}, {NoFlag, 0xfffffffe, 0xfffffffe},
199 {NoFlag, 0xffffffff, 0xffffffff}};
200
201 static const Inputs kRdIsNotRn[] =
202 {{NoFlag, 0x00000002, 0xcccccccc}, {NoFlag, 0x7ffffffd, 0x00007ffe},
203 {NoFlag, 0xffffff80, 0x00000020}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
204 {NoFlag, 0x33333333, 0xffffff82}, {NoFlag, 0xffff8001, 0x7ffffffe},
205 {NoFlag, 0xfffffffd, 0x00007ffe}, {NoFlag, 0xffffff80, 0x80000000},
206 {NoFlag, 0x00000001, 0x33333333}, {NoFlag, 0xcccccccc, 0x7ffffffe},
207 {NoFlag, 0x00000000, 0xcccccccc}, {NoFlag, 0x00000000, 0x55555555},
208 {NoFlag, 0xffffffff, 0xffffffff}, {NoFlag, 0x0000007e, 0xffff8002},
209 {NoFlag, 0x80000000, 0x7ffffffd}, {NoFlag, 0xffffff81, 0x0000007e},
210 {NoFlag, 0x0000007f, 0xffff8001}, {NoFlag, 0xffffffe0, 0x00007ffd},
211 {NoFlag, 0xffff8003, 0x00000002}, {NoFlag, 0xffffff83, 0x55555555},
212 {NoFlag, 0xffffff83, 0xffffff80}, {NoFlag, 0xffffff81, 0xffff8000},
213 {NoFlag, 0x00000020, 0x7ffffffe}, {NoFlag, 0xffffffe0, 0x00000000},
214 {NoFlag, 0x7fffffff, 0x0000007e}, {NoFlag, 0x80000001, 0xffffffff},
215 {NoFlag, 0x00000001, 0x80000001}, {NoFlag, 0x00000002, 0x0000007f},
216 {NoFlag, 0x7fffffff, 0xcccccccc}, {NoFlag, 0x80000001, 0x00007ffe},
217 {NoFlag, 0xffff8002, 0x0000007e}, {NoFlag, 0x00007ffe, 0xcccccccc},
218 {NoFlag, 0x80000000, 0xffff8002}, {NoFlag, 0xffffff83, 0x7ffffffe},
219 {NoFlag, 0xffff8001, 0x00000001}, {NoFlag, 0xffffff81, 0x00000020},
220 {NoFlag, 0xfffffffe, 0xffff8001}, {NoFlag, 0xffffffff, 0xfffffffe},
221 {NoFlag, 0xcccccccc, 0x55555555}, {NoFlag, 0x00000020, 0xffffff83},
222 {NoFlag, 0xffffff83, 0xffff8001}, {NoFlag, 0xffffff83, 0xffff8000},
223 {NoFlag, 0x00007fff, 0x00000002}, {NoFlag, 0x55555555, 0xffff8000},
224 {NoFlag, 0x80000001, 0xffffff81}, {NoFlag, 0x00000002, 0x00000000},
225 {NoFlag, 0x33333333, 0xffffff81}, {NoFlag, 0xffff8001, 0xffffff82},
226 {NoFlag, 0xcccccccc, 0xffff8003}, {NoFlag, 0xffff8003, 0x7ffffffd},
227 {NoFlag, 0x0000007d, 0x00007ffe}, {NoFlag, 0xffffff80, 0x0000007d},
228 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, {NoFlag, 0x80000000, 0xffffff82},
229 {NoFlag, 0x00000002, 0x7ffffffe}, {NoFlag, 0x00000002, 0xffffff83},
230 {NoFlag, 0x55555555, 0x00000002}, {NoFlag, 0xffffffff, 0xffffff82},
231 {NoFlag, 0xaaaaaaaa, 0x00000020}, {NoFlag, 0x00000001, 0xffffff82},
232 {NoFlag, 0x0000007f, 0xffffff82}, {NoFlag, 0x7ffffffd, 0xaaaaaaaa},
233 {NoFlag, 0x00007ffe, 0x00000001}, {NoFlag, 0xfffffffd, 0xffffffe0},
234 {NoFlag, 0xffffff81, 0xffffff83}, {NoFlag, 0x0000007d, 0x00000000},
235 {NoFlag, 0x0000007d, 0xffff8000}, {NoFlag, 0xffffff81, 0x7fffffff},
236 {NoFlag, 0xffffffff, 0x80000000}, {NoFlag, 0x00000000, 0x00000001},
237 {NoFlag, 0x55555555, 0xffffff82}, {NoFlag, 0x00007ffe, 0x00007ffe},
238 {NoFlag, 0x80000001, 0xfffffffd}, {NoFlag, 0x00007fff, 0x33333333},
239 {NoFlag, 0x00007fff, 0x80000000}, {NoFlag, 0xcccccccc, 0x00007fff},
240 {NoFlag, 0xfffffffe, 0xffffffe0}, {NoFlag, 0x7ffffffe, 0x0000007f},
241 {NoFlag, 0x00007ffd, 0xffff8001}, {NoFlag, 0x00000002, 0x00000001},
242 {NoFlag, 0x80000000, 0xffffffff}, {NoFlag, 0xffffff83, 0xcccccccc},
243 {NoFlag, 0xffff8002, 0x7ffffffe}, {NoFlag, 0xaaaaaaaa, 0x00000000},
244 {NoFlag, 0xffffff80, 0xcccccccc}, {NoFlag, 0x33333333, 0xffffff83},
245 {NoFlag, 0x0000007e, 0xffffffe0}, {NoFlag, 0x0000007e, 0x00007fff},
246 {NoFlag, 0x0000007f, 0x00000002}, {NoFlag, 0x7ffffffe, 0xcccccccc},
247 {NoFlag, 0x0000007d, 0xffffff80}, {NoFlag, 0x00007fff, 0x00000020},
248 {NoFlag, 0x7ffffffe, 0xfffffffe}, {NoFlag, 0xfffffffe, 0xffffff81},
249 {NoFlag, 0xffffffff, 0x0000007f}, {NoFlag, 0xffff8002, 0x7ffffffd},
250 {NoFlag, 0xffff8001, 0xfffffffe}, {NoFlag, 0x33333333, 0xffff8002},
251 {NoFlag, 0x00000000, 0xffffffff}, {NoFlag, 0x33333333, 0xffffff80},
252 {NoFlag, 0x0000007f, 0x00007fff}, {NoFlag, 0xffffffff, 0xffff8001},
253 {NoFlag, 0x7fffffff, 0xffff8002}, {NoFlag, 0x7ffffffd, 0xffffff83},
254 {NoFlag, 0x7fffffff, 0x0000007f}, {NoFlag, 0xffffff83, 0xfffffffe},
255 {NoFlag, 0x7ffffffe, 0xffff8003}, {NoFlag, 0xffff8002, 0xffff8002},
256 {NoFlag, 0x80000001, 0x0000007f}, {NoFlag, 0x00000020, 0x00000002},
257 {NoFlag, 0xffffff82, 0xffff8001}, {NoFlag, 0xffffffff, 0x00000001},
258 {NoFlag, 0xffffff80, 0xffff8002}, {NoFlag, 0xffff8003, 0x7fffffff},
259 {NoFlag, 0xffffffff, 0xffff8000}, {NoFlag, 0xffff8002, 0x00007ffd},
260 {NoFlag, 0x00000020, 0xffffff81}, {NoFlag, 0x00000001, 0x55555555},
261 {NoFlag, 0x7ffffffe, 0x00000020}, {NoFlag, 0x80000000, 0x00000001},
262 {NoFlag, 0x00007ffd, 0xffff8002}, {NoFlag, 0x7fffffff, 0xfffffffe},
263 {NoFlag, 0xcccccccc, 0x00007ffd}, {NoFlag, 0x00000000, 0xfffffffd},
264 {NoFlag, 0xffff8003, 0xffffff80}, {NoFlag, 0x80000001, 0xffffff80},
265 {NoFlag, 0xffffffff, 0xffff8002}, {NoFlag, 0x00007ffe, 0xffff8002},
266 {NoFlag, 0xffffff80, 0x00007ffe}, {NoFlag, 0x80000001, 0xffff8001},
267 {NoFlag, 0x0000007f, 0xffffff80}, {NoFlag, 0xffffff81, 0x80000000},
268 {NoFlag, 0x00007fff, 0x00007ffe}, {NoFlag, 0x33333333, 0xffff8000},
269 {NoFlag, 0x33333333, 0x00007fff}, {NoFlag, 0x00000000, 0x0000007d},
270 {NoFlag, 0x80000001, 0x00000000}, {NoFlag, 0xffffffff, 0x55555555},
271 {NoFlag, 0x80000001, 0x80000000}, {NoFlag, 0xffffffff, 0xffffff80},
272 {NoFlag, 0xffffff81, 0xffff8003}, {NoFlag, 0x55555555, 0x80000001},
273 {NoFlag, 0x7fffffff, 0xffff8001}, {NoFlag, 0xffffff83, 0x00000002},
274 {NoFlag, 0x0000007e, 0xffffff81}, {NoFlag, 0x80000000, 0xffff8001},
275 {NoFlag, 0xffffff80, 0xfffffffe}, {NoFlag, 0x0000007e, 0xfffffffd},
276 {NoFlag, 0xffffffe0, 0xffffffff}, {NoFlag, 0x55555555, 0x80000000},
277 {NoFlag, 0x0000007d, 0x80000001}, {NoFlag, 0xffffffe0, 0x7ffffffd},
278 {NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x55555555, 0x00000001},
279 {NoFlag, 0x00007ffd, 0x7fffffff}, {NoFlag, 0x55555555, 0xffffffff},
280 {NoFlag, 0xffff8003, 0x00007fff}, {NoFlag, 0xffffff82, 0x00007fff},
281 {NoFlag, 0x33333333, 0x55555555}, {NoFlag, 0x00000020, 0x33333333},
282 {NoFlag, 0x7ffffffe, 0xfffffffd}, {NoFlag, 0x7ffffffe, 0x00000001},
283 {NoFlag, 0xffffff83, 0xffffffe0}, {NoFlag, 0xfffffffe, 0xaaaaaaaa},
284 {NoFlag, 0xffff8002, 0x33333333}, {NoFlag, 0xffff8002, 0xffff8003},
285 {NoFlag, 0x33333333, 0x7fffffff}, {NoFlag, 0xfffffffd, 0xffffff83},
286 {NoFlag, 0x00000000, 0xffff8000}, {NoFlag, 0xffffff82, 0x55555555},
287 {NoFlag, 0xffffff82, 0xffffff81}, {NoFlag, 0xcccccccc, 0xfffffffe},
288 {NoFlag, 0xfffffffd, 0x7fffffff}, {NoFlag, 0x00007fff, 0x7fffffff},
289 {NoFlag, 0xffffff83, 0xffff8003}, {NoFlag, 0xfffffffe, 0xffffffff},
290 {NoFlag, 0x7ffffffd, 0x00007ffd}, {NoFlag, 0x7ffffffd, 0x00007fff},
291 {NoFlag, 0x00007ffd, 0xffffffff}, {NoFlag, 0x00000001, 0xffff8003},
292 {NoFlag, 0xffffff80, 0xfffffffd}, {NoFlag, 0x33333333, 0x80000000},
293 {NoFlag, 0xffff8001, 0x00000020}, {NoFlag, 0xcccccccc, 0x00000002},
294 {NoFlag, 0x00000000, 0x00000002}, {NoFlag, 0x0000007d, 0x00007fff},
295 {NoFlag, 0xcccccccc, 0x00000001}, {NoFlag, 0xffffff83, 0x00007fff},
296 {NoFlag, 0x80000001, 0x00000020}, {NoFlag, 0xffff8003, 0xffffffe0},
297 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, {NoFlag, 0x33333333, 0xffff8001},
298 {NoFlag, 0xffffff83, 0x80000001}, {NoFlag, 0xffff8000, 0xffff8000},
299 {NoFlag, 0x00007ffe, 0xffff8001}, {NoFlag, 0x7ffffffd, 0x00000000},
300 {NoFlag, 0x00007ffe, 0x33333333}, {NoFlag, 0xffff8001, 0xffffff80},
301 {NoFlag, 0xfffffffe, 0x55555555}, {NoFlag, 0xffffff82, 0xffffffff}};
302
303 static const Inputs kShiftTypes[] =
304 {{NoFlag, 0xabababab, 0x00000000}, {NoFlag, 0xabababab, 0x00000001},
305 {NoFlag, 0xabababab, 0x00000002}, {NoFlag, 0xabababab, 0x00000020},
306 {NoFlag, 0xabababab, 0x0000007d}, {NoFlag, 0xabababab, 0x0000007e},
307 {NoFlag, 0xabababab, 0x0000007f}, {NoFlag, 0xabababab, 0x00007ffd},
308 {NoFlag, 0xabababab, 0x00007ffe}, {NoFlag, 0xabababab, 0x00007fff},
309 {NoFlag, 0xabababab, 0x33333333}, {NoFlag, 0xabababab, 0x55555555},
310 {NoFlag, 0xabababab, 0x7ffffffd}, {NoFlag, 0xabababab, 0x7ffffffe},
311 {NoFlag, 0xabababab, 0x7fffffff}, {NoFlag, 0xabababab, 0x80000000},
312 {NoFlag, 0xabababab, 0x80000001}, {NoFlag, 0xabababab, 0xaaaaaaaa},
313 {NoFlag, 0xabababab, 0xcccccccc}, {NoFlag, 0xabababab, 0xffff8000},
314 {NoFlag, 0xabababab, 0xffff8001}, {NoFlag, 0xabababab, 0xffff8002},
315 {NoFlag, 0xabababab, 0xffff8003}, {NoFlag, 0xabababab, 0xffffff80},
316 {NoFlag, 0xabababab, 0xffffff81}, {NoFlag, 0xabababab, 0xffffff82},
317 {NoFlag, 0xabababab, 0xffffff83}, {NoFlag, 0xabababab, 0xffffffe0},
318 {NoFlag, 0xabababab, 0xfffffffd}, {NoFlag, 0xabababab, 0xfffffffe},
319 {NoFlag, 0xabababab, 0xffffffff}};
320
321
322 // A loop will be generated for each element of this array.
323 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1},
324 "eq r0 r0 LSL 1",
325 "Condition_eq_r0_r0_LSL_1",
326 ARRAY_SIZE(kCondition),
327 kCondition},
328 {{ne, r0, r0, LSL, 1},
329 "ne r0 r0 LSL 1",
330 "Condition_ne_r0_r0_LSL_1",
331 ARRAY_SIZE(kCondition),
332 kCondition},
333 {{cs, r0, r0, LSL, 1},
334 "cs r0 r0 LSL 1",
335 "Condition_cs_r0_r0_LSL_1",
336 ARRAY_SIZE(kCondition),
337 kCondition},
338 {{cc, r0, r0, LSL, 1},
339 "cc r0 r0 LSL 1",
340 "Condition_cc_r0_r0_LSL_1",
341 ARRAY_SIZE(kCondition),
342 kCondition},
343 {{mi, r0, r0, LSL, 1},
344 "mi r0 r0 LSL 1",
345 "Condition_mi_r0_r0_LSL_1",
346 ARRAY_SIZE(kCondition),
347 kCondition},
348 {{pl, r0, r0, LSL, 1},
349 "pl r0 r0 LSL 1",
350 "Condition_pl_r0_r0_LSL_1",
351 ARRAY_SIZE(kCondition),
352 kCondition},
353 {{vs, r0, r0, LSL, 1},
354 "vs r0 r0 LSL 1",
355 "Condition_vs_r0_r0_LSL_1",
356 ARRAY_SIZE(kCondition),
357 kCondition},
358 {{vc, r0, r0, LSL, 1},
359 "vc r0 r0 LSL 1",
360 "Condition_vc_r0_r0_LSL_1",
361 ARRAY_SIZE(kCondition),
362 kCondition},
363 {{hi, r0, r0, LSL, 1},
364 "hi r0 r0 LSL 1",
365 "Condition_hi_r0_r0_LSL_1",
366 ARRAY_SIZE(kCondition),
367 kCondition},
368 {{ls, r0, r0, LSL, 1},
369 "ls r0 r0 LSL 1",
370 "Condition_ls_r0_r0_LSL_1",
371 ARRAY_SIZE(kCondition),
372 kCondition},
373 {{ge, r0, r0, LSL, 1},
374 "ge r0 r0 LSL 1",
375 "Condition_ge_r0_r0_LSL_1",
376 ARRAY_SIZE(kCondition),
377 kCondition},
378 {{lt, r0, r0, LSL, 1},
379 "lt r0 r0 LSL 1",
380 "Condition_lt_r0_r0_LSL_1",
381 ARRAY_SIZE(kCondition),
382 kCondition},
383 {{gt, r0, r0, LSL, 1},
384 "gt r0 r0 LSL 1",
385 "Condition_gt_r0_r0_LSL_1",
386 ARRAY_SIZE(kCondition),
387 kCondition},
388 {{le, r0, r0, LSL, 1},
389 "le r0 r0 LSL 1",
390 "Condition_le_r0_r0_LSL_1",
391 ARRAY_SIZE(kCondition),
392 kCondition},
393 {{al, r0, r0, LSL, 1},
394 "al r0 r0 LSL 1",
395 "Condition_al_r0_r0_LSL_1",
396 ARRAY_SIZE(kCondition),
397 kCondition},
398 {{al, r0, r0, LSL, 1},
399 "al r0 r0 LSL 1",
400 "RdIsRn_al_r0_r0_LSL_1",
401 ARRAY_SIZE(kRdIsRn),
402 kRdIsRn},
403 {{al, r1, r1, LSL, 1},
404 "al r1 r1 LSL 1",
405 "RdIsRn_al_r1_r1_LSL_1",
406 ARRAY_SIZE(kRdIsRn),
407 kRdIsRn},
408 {{al, r2, r2, LSL, 1},
409 "al r2 r2 LSL 1",
410 "RdIsRn_al_r2_r2_LSL_1",
411 ARRAY_SIZE(kRdIsRn),
412 kRdIsRn},
413 {{al, r3, r3, LSL, 1},
414 "al r3 r3 LSL 1",
415 "RdIsRn_al_r3_r3_LSL_1",
416 ARRAY_SIZE(kRdIsRn),
417 kRdIsRn},
418 {{al, r4, r4, LSL, 1},
419 "al r4 r4 LSL 1",
420 "RdIsRn_al_r4_r4_LSL_1",
421 ARRAY_SIZE(kRdIsRn),
422 kRdIsRn},
423 {{al, r5, r5, LSL, 1},
424 "al r5 r5 LSL 1",
425 "RdIsRn_al_r5_r5_LSL_1",
426 ARRAY_SIZE(kRdIsRn),
427 kRdIsRn},
428 {{al, r6, r6, LSL, 1},
429 "al r6 r6 LSL 1",
430 "RdIsRn_al_r6_r6_LSL_1",
431 ARRAY_SIZE(kRdIsRn),
432 kRdIsRn},
433 {{al, r7, r7, LSL, 1},
434 "al r7 r7 LSL 1",
435 "RdIsRn_al_r7_r7_LSL_1",
436 ARRAY_SIZE(kRdIsRn),
437 kRdIsRn},
438 {{al, r8, r8, LSL, 1},
439 "al r8 r8 LSL 1",
440 "RdIsRn_al_r8_r8_LSL_1",
441 ARRAY_SIZE(kRdIsRn),
442 kRdIsRn},
443 {{al, r9, r9, LSL, 1},
444 "al r9 r9 LSL 1",
445 "RdIsRn_al_r9_r9_LSL_1",
446 ARRAY_SIZE(kRdIsRn),
447 kRdIsRn},
448 {{al, r10, r10, LSL, 1},
449 "al r10 r10 LSL 1",
450 "RdIsRn_al_r10_r10_LSL_1",
451 ARRAY_SIZE(kRdIsRn),
452 kRdIsRn},
453 {{al, r11, r11, LSL, 1},
454 "al r11 r11 LSL 1",
455 "RdIsRn_al_r11_r11_LSL_1",
456 ARRAY_SIZE(kRdIsRn),
457 kRdIsRn},
458 {{al, r12, r12, LSL, 1},
459 "al r12 r12 LSL 1",
460 "RdIsRn_al_r12_r12_LSL_1",
461 ARRAY_SIZE(kRdIsRn),
462 kRdIsRn},
463 {{al, r14, r14, LSL, 1},
464 "al r14 r14 LSL 1",
465 "RdIsRn_al_r14_r14_LSL_1",
466 ARRAY_SIZE(kRdIsRn),
467 kRdIsRn},
468 {{al, r1, r8, LSL, 1},
469 "al r1 r8 LSL 1",
470 "RdIsNotRn_al_r1_r8_LSL_1",
471 ARRAY_SIZE(kRdIsNotRn),
472 kRdIsNotRn},
473 {{al, r7, r4, LSL, 1},
474 "al r7 r4 LSL 1",
475 "RdIsNotRn_al_r7_r4_LSL_1",
476 ARRAY_SIZE(kRdIsNotRn),
477 kRdIsNotRn},
478 {{al, r14, r10, LSL, 1},
479 "al r14 r10 LSL 1",
480 "RdIsNotRn_al_r14_r10_LSL_1",
481 ARRAY_SIZE(kRdIsNotRn),
482 kRdIsNotRn},
483 {{al, r10, r6, LSL, 1},
484 "al r10 r6 LSL 1",
485 "RdIsNotRn_al_r10_r6_LSL_1",
486 ARRAY_SIZE(kRdIsNotRn),
487 kRdIsNotRn},
488 {{al, r6, r5, LSL, 1},
489 "al r6 r5 LSL 1",
490 "RdIsNotRn_al_r6_r5_LSL_1",
491 ARRAY_SIZE(kRdIsNotRn),
492 kRdIsNotRn},
493 {{al, r12, r2, LSL, 1},
494 "al r12 r2 LSL 1",
495 "RdIsNotRn_al_r12_r2_LSL_1",
496 ARRAY_SIZE(kRdIsNotRn),
497 kRdIsNotRn},
498 {{al, r0, r11, LSL, 1},
499 "al r0 r11 LSL 1",
500 "RdIsNotRn_al_r0_r11_LSL_1",
501 ARRAY_SIZE(kRdIsNotRn),
502 kRdIsNotRn},
503 {{al, r10, r14, LSL, 1},
504 "al r10 r14 LSL 1",
505 "RdIsNotRn_al_r10_r14_LSL_1",
506 ARRAY_SIZE(kRdIsNotRn),
507 kRdIsNotRn},
508 {{al, r0, r5, LSL, 1},
509 "al r0 r5 LSL 1",
510 "RdIsNotRn_al_r0_r5_LSL_1",
511 ARRAY_SIZE(kRdIsNotRn),
512 kRdIsNotRn},
513 {{al, r0, r3, LSL, 1},
514 "al r0 r3 LSL 1",
515 "RdIsNotRn_al_r0_r3_LSL_1",
516 ARRAY_SIZE(kRdIsNotRn),
517 kRdIsNotRn},
518 {{al, r0, r0, LSL, 1},
519 "al r0 r0 LSL 1",
520 "ShiftTypes_al_r0_r0_LSL_1",
521 ARRAY_SIZE(kShiftTypes),
522 kShiftTypes},
523 {{al, r0, r0, LSL, 2},
524 "al r0 r0 LSL 2",
525 "ShiftTypes_al_r0_r0_LSL_2",
526 ARRAY_SIZE(kShiftTypes),
527 kShiftTypes},
528 {{al, r0, r0, LSL, 3},
529 "al r0 r0 LSL 3",
530 "ShiftTypes_al_r0_r0_LSL_3",
531 ARRAY_SIZE(kShiftTypes),
532 kShiftTypes},
533 {{al, r0, r0, LSL, 4},
534 "al r0 r0 LSL 4",
535 "ShiftTypes_al_r0_r0_LSL_4",
536 ARRAY_SIZE(kShiftTypes),
537 kShiftTypes},
538 {{al, r0, r0, LSL, 5},
539 "al r0 r0 LSL 5",
540 "ShiftTypes_al_r0_r0_LSL_5",
541 ARRAY_SIZE(kShiftTypes),
542 kShiftTypes},
543 {{al, r0, r0, LSL, 6},
544 "al r0 r0 LSL 6",
545 "ShiftTypes_al_r0_r0_LSL_6",
546 ARRAY_SIZE(kShiftTypes),
547 kShiftTypes},
548 {{al, r0, r0, LSL, 7},
549 "al r0 r0 LSL 7",
550 "ShiftTypes_al_r0_r0_LSL_7",
551 ARRAY_SIZE(kShiftTypes),
552 kShiftTypes},
553 {{al, r0, r0, LSL, 8},
554 "al r0 r0 LSL 8",
555 "ShiftTypes_al_r0_r0_LSL_8",
556 ARRAY_SIZE(kShiftTypes),
557 kShiftTypes},
558 {{al, r0, r0, LSL, 9},
559 "al r0 r0 LSL 9",
560 "ShiftTypes_al_r0_r0_LSL_9",
561 ARRAY_SIZE(kShiftTypes),
562 kShiftTypes},
563 {{al, r0, r0, LSL, 10},
564 "al r0 r0 LSL 10",
565 "ShiftTypes_al_r0_r0_LSL_10",
566 ARRAY_SIZE(kShiftTypes),
567 kShiftTypes},
568 {{al, r0, r0, LSL, 11},
569 "al r0 r0 LSL 11",
570 "ShiftTypes_al_r0_r0_LSL_11",
571 ARRAY_SIZE(kShiftTypes),
572 kShiftTypes},
573 {{al, r0, r0, LSL, 12},
574 "al r0 r0 LSL 12",
575 "ShiftTypes_al_r0_r0_LSL_12",
576 ARRAY_SIZE(kShiftTypes),
577 kShiftTypes},
578 {{al, r0, r0, LSL, 13},
579 "al r0 r0 LSL 13",
580 "ShiftTypes_al_r0_r0_LSL_13",
581 ARRAY_SIZE(kShiftTypes),
582 kShiftTypes},
583 {{al, r0, r0, LSL, 14},
584 "al r0 r0 LSL 14",
585 "ShiftTypes_al_r0_r0_LSL_14",
586 ARRAY_SIZE(kShiftTypes),
587 kShiftTypes},
588 {{al, r0, r0, LSL, 15},
589 "al r0 r0 LSL 15",
590 "ShiftTypes_al_r0_r0_LSL_15",
591 ARRAY_SIZE(kShiftTypes),
592 kShiftTypes},
593 {{al, r0, r0, LSL, 16},
594 "al r0 r0 LSL 16",
595 "ShiftTypes_al_r0_r0_LSL_16",
596 ARRAY_SIZE(kShiftTypes),
597 kShiftTypes},
598 {{al, r0, r0, LSL, 17},
599 "al r0 r0 LSL 17",
600 "ShiftTypes_al_r0_r0_LSL_17",
601 ARRAY_SIZE(kShiftTypes),
602 kShiftTypes},
603 {{al, r0, r0, LSL, 18},
604 "al r0 r0 LSL 18",
605 "ShiftTypes_al_r0_r0_LSL_18",
606 ARRAY_SIZE(kShiftTypes),
607 kShiftTypes},
608 {{al, r0, r0, LSL, 19},
609 "al r0 r0 LSL 19",
610 "ShiftTypes_al_r0_r0_LSL_19",
611 ARRAY_SIZE(kShiftTypes),
612 kShiftTypes},
613 {{al, r0, r0, LSL, 20},
614 "al r0 r0 LSL 20",
615 "ShiftTypes_al_r0_r0_LSL_20",
616 ARRAY_SIZE(kShiftTypes),
617 kShiftTypes},
618 {{al, r0, r0, LSL, 21},
619 "al r0 r0 LSL 21",
620 "ShiftTypes_al_r0_r0_LSL_21",
621 ARRAY_SIZE(kShiftTypes),
622 kShiftTypes},
623 {{al, r0, r0, LSL, 22},
624 "al r0 r0 LSL 22",
625 "ShiftTypes_al_r0_r0_LSL_22",
626 ARRAY_SIZE(kShiftTypes),
627 kShiftTypes},
628 {{al, r0, r0, LSL, 23},
629 "al r0 r0 LSL 23",
630 "ShiftTypes_al_r0_r0_LSL_23",
631 ARRAY_SIZE(kShiftTypes),
632 kShiftTypes},
633 {{al, r0, r0, LSL, 24},
634 "al r0 r0 LSL 24",
635 "ShiftTypes_al_r0_r0_LSL_24",
636 ARRAY_SIZE(kShiftTypes),
637 kShiftTypes},
638 {{al, r0, r0, LSL, 25},
639 "al r0 r0 LSL 25",
640 "ShiftTypes_al_r0_r0_LSL_25",
641 ARRAY_SIZE(kShiftTypes),
642 kShiftTypes},
643 {{al, r0, r0, LSL, 26},
644 "al r0 r0 LSL 26",
645 "ShiftTypes_al_r0_r0_LSL_26",
646 ARRAY_SIZE(kShiftTypes),
647 kShiftTypes},
648 {{al, r0, r0, LSL, 27},
649 "al r0 r0 LSL 27",
650 "ShiftTypes_al_r0_r0_LSL_27",
651 ARRAY_SIZE(kShiftTypes),
652 kShiftTypes},
653 {{al, r0, r0, LSL, 28},
654 "al r0 r0 LSL 28",
655 "ShiftTypes_al_r0_r0_LSL_28",
656 ARRAY_SIZE(kShiftTypes),
657 kShiftTypes},
658 {{al, r0, r0, LSL, 29},
659 "al r0 r0 LSL 29",
660 "ShiftTypes_al_r0_r0_LSL_29",
661 ARRAY_SIZE(kShiftTypes),
662 kShiftTypes},
663 {{al, r0, r0, LSL, 30},
664 "al r0 r0 LSL 30",
665 "ShiftTypes_al_r0_r0_LSL_30",
666 ARRAY_SIZE(kShiftTypes),
667 kShiftTypes},
668 {{al, r0, r0, LSL, 31},
669 "al r0 r0 LSL 31",
670 "ShiftTypes_al_r0_r0_LSL_31",
671 ARRAY_SIZE(kShiftTypes),
672 kShiftTypes},
673 {{al, r0, r0, ROR, 1},
674 "al r0 r0 ROR 1",
675 "ShiftTypes_al_r0_r0_ROR_1",
676 ARRAY_SIZE(kShiftTypes),
677 kShiftTypes},
678 {{al, r0, r0, ROR, 2},
679 "al r0 r0 ROR 2",
680 "ShiftTypes_al_r0_r0_ROR_2",
681 ARRAY_SIZE(kShiftTypes),
682 kShiftTypes},
683 {{al, r0, r0, ROR, 3},
684 "al r0 r0 ROR 3",
685 "ShiftTypes_al_r0_r0_ROR_3",
686 ARRAY_SIZE(kShiftTypes),
687 kShiftTypes},
688 {{al, r0, r0, ROR, 4},
689 "al r0 r0 ROR 4",
690 "ShiftTypes_al_r0_r0_ROR_4",
691 ARRAY_SIZE(kShiftTypes),
692 kShiftTypes},
693 {{al, r0, r0, ROR, 5},
694 "al r0 r0 ROR 5",
695 "ShiftTypes_al_r0_r0_ROR_5",
696 ARRAY_SIZE(kShiftTypes),
697 kShiftTypes},
698 {{al, r0, r0, ROR, 6},
699 "al r0 r0 ROR 6",
700 "ShiftTypes_al_r0_r0_ROR_6",
701 ARRAY_SIZE(kShiftTypes),
702 kShiftTypes},
703 {{al, r0, r0, ROR, 7},
704 "al r0 r0 ROR 7",
705 "ShiftTypes_al_r0_r0_ROR_7",
706 ARRAY_SIZE(kShiftTypes),
707 kShiftTypes},
708 {{al, r0, r0, ROR, 8},
709 "al r0 r0 ROR 8",
710 "ShiftTypes_al_r0_r0_ROR_8",
711 ARRAY_SIZE(kShiftTypes),
712 kShiftTypes},
713 {{al, r0, r0, ROR, 9},
714 "al r0 r0 ROR 9",
715 "ShiftTypes_al_r0_r0_ROR_9",
716 ARRAY_SIZE(kShiftTypes),
717 kShiftTypes},
718 {{al, r0, r0, ROR, 10},
719 "al r0 r0 ROR 10",
720 "ShiftTypes_al_r0_r0_ROR_10",
721 ARRAY_SIZE(kShiftTypes),
722 kShiftTypes},
723 {{al, r0, r0, ROR, 11},
724 "al r0 r0 ROR 11",
725 "ShiftTypes_al_r0_r0_ROR_11",
726 ARRAY_SIZE(kShiftTypes),
727 kShiftTypes},
728 {{al, r0, r0, ROR, 12},
729 "al r0 r0 ROR 12",
730 "ShiftTypes_al_r0_r0_ROR_12",
731 ARRAY_SIZE(kShiftTypes),
732 kShiftTypes},
733 {{al, r0, r0, ROR, 13},
734 "al r0 r0 ROR 13",
735 "ShiftTypes_al_r0_r0_ROR_13",
736 ARRAY_SIZE(kShiftTypes),
737 kShiftTypes},
738 {{al, r0, r0, ROR, 14},
739 "al r0 r0 ROR 14",
740 "ShiftTypes_al_r0_r0_ROR_14",
741 ARRAY_SIZE(kShiftTypes),
742 kShiftTypes},
743 {{al, r0, r0, ROR, 15},
744 "al r0 r0 ROR 15",
745 "ShiftTypes_al_r0_r0_ROR_15",
746 ARRAY_SIZE(kShiftTypes),
747 kShiftTypes},
748 {{al, r0, r0, ROR, 16},
749 "al r0 r0 ROR 16",
750 "ShiftTypes_al_r0_r0_ROR_16",
751 ARRAY_SIZE(kShiftTypes),
752 kShiftTypes},
753 {{al, r0, r0, ROR, 17},
754 "al r0 r0 ROR 17",
755 "ShiftTypes_al_r0_r0_ROR_17",
756 ARRAY_SIZE(kShiftTypes),
757 kShiftTypes},
758 {{al, r0, r0, ROR, 18},
759 "al r0 r0 ROR 18",
760 "ShiftTypes_al_r0_r0_ROR_18",
761 ARRAY_SIZE(kShiftTypes),
762 kShiftTypes},
763 {{al, r0, r0, ROR, 19},
764 "al r0 r0 ROR 19",
765 "ShiftTypes_al_r0_r0_ROR_19",
766 ARRAY_SIZE(kShiftTypes),
767 kShiftTypes},
768 {{al, r0, r0, ROR, 20},
769 "al r0 r0 ROR 20",
770 "ShiftTypes_al_r0_r0_ROR_20",
771 ARRAY_SIZE(kShiftTypes),
772 kShiftTypes},
773 {{al, r0, r0, ROR, 21},
774 "al r0 r0 ROR 21",
775 "ShiftTypes_al_r0_r0_ROR_21",
776 ARRAY_SIZE(kShiftTypes),
777 kShiftTypes},
778 {{al, r0, r0, ROR, 22},
779 "al r0 r0 ROR 22",
780 "ShiftTypes_al_r0_r0_ROR_22",
781 ARRAY_SIZE(kShiftTypes),
782 kShiftTypes},
783 {{al, r0, r0, ROR, 23},
784 "al r0 r0 ROR 23",
785 "ShiftTypes_al_r0_r0_ROR_23",
786 ARRAY_SIZE(kShiftTypes),
787 kShiftTypes},
788 {{al, r0, r0, ROR, 24},
789 "al r0 r0 ROR 24",
790 "ShiftTypes_al_r0_r0_ROR_24",
791 ARRAY_SIZE(kShiftTypes),
792 kShiftTypes},
793 {{al, r0, r0, ROR, 25},
794 "al r0 r0 ROR 25",
795 "ShiftTypes_al_r0_r0_ROR_25",
796 ARRAY_SIZE(kShiftTypes),
797 kShiftTypes},
798 {{al, r0, r0, ROR, 26},
799 "al r0 r0 ROR 26",
800 "ShiftTypes_al_r0_r0_ROR_26",
801 ARRAY_SIZE(kShiftTypes),
802 kShiftTypes},
803 {{al, r0, r0, ROR, 27},
804 "al r0 r0 ROR 27",
805 "ShiftTypes_al_r0_r0_ROR_27",
806 ARRAY_SIZE(kShiftTypes),
807 kShiftTypes},
808 {{al, r0, r0, ROR, 28},
809 "al r0 r0 ROR 28",
810 "ShiftTypes_al_r0_r0_ROR_28",
811 ARRAY_SIZE(kShiftTypes),
812 kShiftTypes},
813 {{al, r0, r0, ROR, 29},
814 "al r0 r0 ROR 29",
815 "ShiftTypes_al_r0_r0_ROR_29",
816 ARRAY_SIZE(kShiftTypes),
817 kShiftTypes},
818 {{al, r0, r0, ROR, 30},
819 "al r0 r0 ROR 30",
820 "ShiftTypes_al_r0_r0_ROR_30",
821 ARRAY_SIZE(kShiftTypes),
822 kShiftTypes},
823 {{al, r0, r0, ROR, 31},
824 "al r0 r0 ROR 31",
825 "ShiftTypes_al_r0_r0_ROR_31",
826 ARRAY_SIZE(kShiftTypes),
827 kShiftTypes}};
828
829 // We record all inputs to the instructions as outputs. This way, we also check
830 // that what shouldn't change didn't change.
831 struct TestResult {
832 size_t output_size;
833 const Inputs* outputs;
834 };
835
836 // These headers each contain an array of `TestResult` with the reference output
837 // values. The reference arrays are names `kReference{mnemonic}`.
838 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-cmn-a32.h"
839 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-cmp-a32.h"
840 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-mov-a32.h"
841 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-movs-a32.h"
842 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-mvn-a32.h"
843 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-mvns-a32.h"
844 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-teq-a32.h"
845 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to31-tst-a32.h"
846
847
848 // The maximum number of errors to report in detail for each test.
849 const unsigned kErrorReportLimit = 8;
850
851 typedef void (MacroAssembler::*Fn)(Condition cond,
852 Register rd,
853 const Operand& op);
854
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])855 void TestHelper(Fn instruction,
856 const char* mnemonic,
857 const TestResult reference[]) {
858 SETUP();
859 masm.UseA32();
860 START();
861
862 // Data to compare to `reference`.
863 TestResult* results[ARRAY_SIZE(kTests)];
864
865 // Test cases for memory bound instructions may allocate a buffer and save its
866 // address in this array.
867 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)];
868
869 // Generate a loop for each element in `kTests`. Each loop tests one specific
870 // instruction.
871 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
872 // Allocate results on the heap for this test.
873 results[i] = new TestResult;
874 results[i]->outputs = new Inputs[kTests[i].input_size];
875 results[i]->output_size = kTests[i].input_size;
876
877 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size;
878 VIXL_ASSERT(IsUint32(input_stride));
879
880 scratch_memory_buffers[i] = NULL;
881
882 Label loop;
883 UseScratchRegisterScope scratch_registers(&masm);
884 // Include all registers from r0 ro r12.
885 scratch_registers.Include(RegisterList(0x1fff));
886
887 // Values to pass to the macro-assembler.
888 Condition cond = kTests[i].operands.cond;
889 Register rd = kTests[i].operands.rd;
890 Register rn = kTests[i].operands.rn;
891 ShiftType shift = kTests[i].operands.shift;
892 uint32_t amount = kTests[i].operands.amount;
893 Operand op(rn, shift, amount);
894 scratch_registers.Exclude(rd);
895 scratch_registers.Exclude(rn);
896
897 // Allocate reserved registers for our own use.
898 Register input_ptr = scratch_registers.Acquire();
899 Register input_end = scratch_registers.Acquire();
900 Register result_ptr = scratch_registers.Acquire();
901
902 // Initialize `input_ptr` to the first element and `input_end` the address
903 // after the array.
904 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
905 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride));
906 __ Mov(result_ptr, Operand::From(results[i]->outputs));
907 __ Bind(&loop);
908
909 {
910 UseScratchRegisterScope temp_registers(&masm);
911 Register nzcv_bits = temp_registers.Acquire();
912 Register saved_q_bit = temp_registers.Acquire();
913 // Save the `Q` bit flag.
914 __ Mrs(saved_q_bit, APSR);
915 __ And(saved_q_bit, saved_q_bit, QFlag);
916 // Set the `NZCV` and `Q` flags together.
917 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
918 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
919 __ Msr(APSR_nzcvq, nzcv_bits);
920 }
921 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
922 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
923
924 (masm.*instruction)(cond, rd, op);
925
926 {
927 UseScratchRegisterScope temp_registers(&masm);
928 Register nzcv_bits = temp_registers.Acquire();
929 __ Mrs(nzcv_bits, APSR);
930 // Only record the NZCV bits.
931 __ And(nzcv_bits, nzcv_bits, NZCVFlag);
932 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr)));
933 }
934 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd)));
935 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn)));
936
937 // Advance the result pointer.
938 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
939 // Loop back until `input_ptr` is lower than `input_base`.
940 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
941 __ Cmp(input_ptr, input_end);
942 __ B(ne, &loop);
943 }
944
945 END();
946
947 RUN();
948
949 if (Test::generate_test_trace()) {
950 // Print the results.
951 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
952 printf("const Inputs kOutputs_%s_%s[] = {\n",
953 mnemonic,
954 kTests[i].identifier);
955 for (size_t j = 0; j < results[i]->output_size; j++) {
956 printf(" { ");
957 printf("0x%08" PRIx32, results[i]->outputs[j].apsr);
958 printf(", ");
959 printf("0x%08" PRIx32, results[i]->outputs[j].rd);
960 printf(", ");
961 printf("0x%08" PRIx32, results[i]->outputs[j].rn);
962 printf(" },\n");
963 }
964 printf("};\n");
965 }
966 printf("const TestResult kReference%s[] = {\n", mnemonic);
967 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
968 printf(" {\n");
969 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n",
970 mnemonic,
971 kTests[i].identifier);
972 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier);
973 printf(" },\n");
974 }
975 printf("};\n");
976 } else if (kCheckSimulatorTestResults) {
977 // Check the results.
978 unsigned total_error_count = 0;
979 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
980 bool instruction_has_errors = false;
981 for (size_t j = 0; j < kTests[i].input_size; j++) {
982 uint32_t apsr = results[i]->outputs[j].apsr;
983 uint32_t rd = results[i]->outputs[j].rd;
984 uint32_t rn = results[i]->outputs[j].rn;
985 uint32_t apsr_input = kTests[i].inputs[j].apsr;
986 uint32_t rd_input = kTests[i].inputs[j].rd;
987 uint32_t rn_input = kTests[i].inputs[j].rn;
988 uint32_t apsr_ref = reference[i].outputs[j].apsr;
989 uint32_t rd_ref = reference[i].outputs[j].rd;
990 uint32_t rn_ref = reference[i].outputs[j].rn;
991
992 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) &&
993 (++total_error_count <= kErrorReportLimit)) {
994 // Print the instruction once even if it triggered multiple failures.
995 if (!instruction_has_errors) {
996 printf("Error(s) when testing \"%s %s\":\n",
997 mnemonic,
998 kTests[i].operands_description);
999 instruction_has_errors = true;
1000 }
1001 // Print subsequent errors.
1002 printf(" Input: ");
1003 printf("0x%08" PRIx32, apsr_input);
1004 printf(", ");
1005 printf("0x%08" PRIx32, rd_input);
1006 printf(", ");
1007 printf("0x%08" PRIx32, rn_input);
1008 printf("\n");
1009 printf(" Expected: ");
1010 printf("0x%08" PRIx32, apsr_ref);
1011 printf(", ");
1012 printf("0x%08" PRIx32, rd_ref);
1013 printf(", ");
1014 printf("0x%08" PRIx32, rn_ref);
1015 printf("\n");
1016 printf(" Found: ");
1017 printf("0x%08" PRIx32, apsr);
1018 printf(", ");
1019 printf("0x%08" PRIx32, rd);
1020 printf(", ");
1021 printf("0x%08" PRIx32, rn);
1022 printf("\n\n");
1023 }
1024 }
1025 }
1026
1027 if (total_error_count > kErrorReportLimit) {
1028 printf("%u other errors follow.\n",
1029 total_error_count - kErrorReportLimit);
1030 }
1031 VIXL_CHECK(total_error_count == 0);
1032 } else {
1033 VIXL_WARNING("Assembled the code, but did not run anything.\n");
1034 }
1035
1036 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1037 delete[] results[i]->outputs;
1038 delete results[i];
1039 delete[] scratch_memory_buffers[i];
1040 }
1041 }
1042
1043 // Instantiate tests for each instruction in the list.
1044 // TODO: Remove this limitation by having a sandboxing mechanism.
1045 #if defined(VIXL_HOST_POINTER_32)
1046 #define TEST(mnemonic) \
1047 void Test_##mnemonic() { \
1048 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
1049 } \
1050 Test test_##mnemonic( \
1051 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO31_" #mnemonic \
1052 "_A32", \
1053 &Test_##mnemonic);
1054 #else
1055 #define TEST(mnemonic) \
1056 void Test_##mnemonic() { \
1057 VIXL_WARNING("This test can only run on a 32-bit host.\n"); \
1058 USE(TestHelper); \
1059 } \
1060 Test test_##mnemonic( \
1061 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO31_" #mnemonic \
1062 "_A32", \
1063 &Test_##mnemonic);
1064 #endif
1065
1066 FOREACH_INSTRUCTION(TEST)
1067 #undef TEST
1068
1069 } // namespace
1070 #endif
1071
1072 } // namespace aarch32
1073 } // namespace vixl
1074