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Searched defs:PredReg (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp69 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
117 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
234 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
494 unsigned PredReg; in rewriteT2FrameIndex() local
709 unsigned &PredReg) { in getITInstrPredicate()
730 unsigned &PredReg) { in getVPTInstrPredicate()
DARMLoadStoreOptimizer.cpp486 unsigned PredReg) { in UpdateBaseRegUses()
626 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
833 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
903 unsigned PredReg = 0; in MergeOpsUpdate() local
1187 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1219 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1239 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
1273 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1415 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1528 unsigned PredReg; in MergeBaseUpdateLSDouble() local
[all …]
DThumb2SizeReduction.cpp471 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
679 unsigned PredReg = 0; in ReduceSpecial() local
721 unsigned PredReg = 0; in ReduceSpecial() local
792 unsigned PredReg = 0; in ReduceTo2Addr() local
885 unsigned PredReg = 0; in ReduceToNarrow() local
DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
DMVEVPTBlockPass.cpp103 unsigned PredReg = 0; in InsertVPTBlocks() local
DThumb2ITBlockPass.cpp202 unsigned PredReg = 0; in InsertITInstructions() local
DARMBaseRegisterInfo.cpp461 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
811 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
DARMConstantIslandPass.cpp1368 PredReg = 0; in createNewWater() local
1413 unsigned PredReg = 0; in createNewWater() local
1437 unsigned PredReg; in createNewWater() local
1871 unsigned PredReg = 0; in optimizeThumb2Branches() local
DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
DARMFrameLowering.cpp170 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
184 unsigned PredReg = 0) { in emitSPUpdate()
2174 unsigned PredReg = TII.getFramePred(Old); in eliminateCallFramePseudoInstr() local
/external/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
225 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
468 unsigned PredReg; in rewriteT2FrameIndex() local
638 unsigned &PredReg) { in getITInstrPredicate()
DARMLoadStoreOptimizer.cpp460 unsigned PredReg) { in UpdateBaseRegUses()
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
793 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
860 unsigned PredReg = 0; in MergeOpsUpdate() local
1127 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1157 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1177 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
1211 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1353 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1450 unsigned PredReg; in MergeBaseUpdateLSDouble() local
[all …]
DThumb2SizeReduction.cpp441 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
647 unsigned PredReg = 0; in ReduceSpecial() local
752 unsigned PredReg = 0; in ReduceTo2Addr() local
848 unsigned PredReg = 0; in ReduceToNarrow() local
DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
DARMFrameLowering.cpp126 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
140 unsigned PredReg = 0) { in emitSPUpdate()
1772 unsigned PredReg = Old.getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1777 unsigned PredReg = Old.getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
DThumb2ITBlockPass.cpp189 unsigned PredReg = 0; in InsertITInstructions() local
DARMBaseRegisterInfo.cpp414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
88 unsigned PredReg = Hexagon::NoRegister; in init() local
DHexagonMCCompound.cpp176 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
DHexagonMCCompound.cpp182 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
DHexagonMCChecker.cpp58 unsigned PredReg = Hexagon::NoRegister; in init() local
DHexagonMCChecker.h98 unsigned PredReg; member

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