1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_AMDGPU_GEM_CREATE 0x00 26 #define DRM_AMDGPU_GEM_MMAP 0x01 27 #define DRM_AMDGPU_CTX 0x02 28 #define DRM_AMDGPU_BO_LIST 0x03 29 #define DRM_AMDGPU_CS 0x04 30 #define DRM_AMDGPU_INFO 0x05 31 #define DRM_AMDGPU_GEM_METADATA 0x06 32 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 33 #define DRM_AMDGPU_GEM_VA 0x08 34 #define DRM_AMDGPU_WAIT_CS 0x09 35 #define DRM_AMDGPU_GEM_OP 0x10 36 #define DRM_AMDGPU_GEM_USERPTR 0x11 37 #define DRM_AMDGPU_WAIT_FENCES 0x12 38 #define DRM_AMDGPU_VM 0x13 39 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 40 #define DRM_AMDGPU_SCHED 0x15 41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 43 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 44 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 49 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 50 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 51 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 52 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 53 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 54 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 55 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 56 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 57 #define AMDGPU_GEM_DOMAIN_CPU 0x1 58 #define AMDGPU_GEM_DOMAIN_GTT 0x2 59 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 60 #define AMDGPU_GEM_DOMAIN_GDS 0x8 61 #define AMDGPU_GEM_DOMAIN_GWS 0x10 62 #define AMDGPU_GEM_DOMAIN_OA 0x20 63 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA) 64 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 65 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 66 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 67 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 68 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 69 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 70 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 71 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 72 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 73 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 74 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 75 struct drm_amdgpu_gem_create_in { 76 __u64 bo_size; 77 __u64 alignment; 78 __u64 domains; 79 __u64 domain_flags; 80 }; 81 struct drm_amdgpu_gem_create_out { 82 __u32 handle; 83 __u32 _pad; 84 }; 85 union drm_amdgpu_gem_create { 86 struct drm_amdgpu_gem_create_in in; 87 struct drm_amdgpu_gem_create_out out; 88 }; 89 #define AMDGPU_BO_LIST_OP_CREATE 0 90 #define AMDGPU_BO_LIST_OP_DESTROY 1 91 #define AMDGPU_BO_LIST_OP_UPDATE 2 92 struct drm_amdgpu_bo_list_in { 93 __u32 operation; 94 __u32 list_handle; 95 __u32 bo_number; 96 __u32 bo_info_size; 97 __u64 bo_info_ptr; 98 }; 99 struct drm_amdgpu_bo_list_entry { 100 __u32 bo_handle; 101 __u32 bo_priority; 102 }; 103 struct drm_amdgpu_bo_list_out { 104 __u32 list_handle; 105 __u32 _pad; 106 }; 107 union drm_amdgpu_bo_list { 108 struct drm_amdgpu_bo_list_in in; 109 struct drm_amdgpu_bo_list_out out; 110 }; 111 #define AMDGPU_CTX_OP_ALLOC_CTX 1 112 #define AMDGPU_CTX_OP_FREE_CTX 2 113 #define AMDGPU_CTX_OP_QUERY_STATE 3 114 #define AMDGPU_CTX_OP_QUERY_STATE2 4 115 #define AMDGPU_CTX_NO_RESET 0 116 #define AMDGPU_CTX_GUILTY_RESET 1 117 #define AMDGPU_CTX_INNOCENT_RESET 2 118 #define AMDGPU_CTX_UNKNOWN_RESET 3 119 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 120 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 121 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 122 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) 123 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) 124 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 125 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 126 #define AMDGPU_CTX_PRIORITY_LOW - 512 127 #define AMDGPU_CTX_PRIORITY_NORMAL 0 128 #define AMDGPU_CTX_PRIORITY_HIGH 512 129 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 130 struct drm_amdgpu_ctx_in { 131 __u32 op; 132 __u32 flags; 133 __u32 ctx_id; 134 __s32 priority; 135 }; 136 union drm_amdgpu_ctx_out { 137 struct { 138 __u32 ctx_id; 139 __u32 _pad; 140 } alloc; 141 struct { 142 __u64 flags; 143 __u32 hangs; 144 __u32 reset_status; 145 } state; 146 }; 147 union drm_amdgpu_ctx { 148 struct drm_amdgpu_ctx_in in; 149 union drm_amdgpu_ctx_out out; 150 }; 151 #define AMDGPU_VM_OP_RESERVE_VMID 1 152 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 153 struct drm_amdgpu_vm_in { 154 __u32 op; 155 __u32 flags; 156 }; 157 struct drm_amdgpu_vm_out { 158 __u64 flags; 159 }; 160 union drm_amdgpu_vm { 161 struct drm_amdgpu_vm_in in; 162 struct drm_amdgpu_vm_out out; 163 }; 164 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 165 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 166 struct drm_amdgpu_sched_in { 167 __u32 op; 168 __u32 fd; 169 __s32 priority; 170 __u32 ctx_id; 171 }; 172 union drm_amdgpu_sched { 173 struct drm_amdgpu_sched_in in; 174 }; 175 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 176 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 177 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 178 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 179 struct drm_amdgpu_gem_userptr { 180 __u64 addr; 181 __u64 size; 182 __u32 flags; 183 __u32 handle; 184 }; 185 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 186 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 187 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 188 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 189 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 190 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 191 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 192 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 193 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 194 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 195 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 196 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 197 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 198 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 199 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 200 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 201 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 202 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 203 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 204 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 205 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 206 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 207 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 208 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 209 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 210 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 211 #define AMDGPU_TILING_SCANOUT_SHIFT 63 212 #define AMDGPU_TILING_SCANOUT_MASK 0x1 213 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 214 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 215 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 216 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 217 struct drm_amdgpu_gem_metadata { 218 __u32 handle; 219 __u32 op; 220 struct { 221 __u64 flags; 222 __u64 tiling_info; 223 __u32 data_size_bytes; 224 __u32 data[64]; 225 } data; 226 }; 227 struct drm_amdgpu_gem_mmap_in { 228 __u32 handle; 229 __u32 _pad; 230 }; 231 struct drm_amdgpu_gem_mmap_out { 232 __u64 addr_ptr; 233 }; 234 union drm_amdgpu_gem_mmap { 235 struct drm_amdgpu_gem_mmap_in in; 236 struct drm_amdgpu_gem_mmap_out out; 237 }; 238 struct drm_amdgpu_gem_wait_idle_in { 239 __u32 handle; 240 __u32 flags; 241 __u64 timeout; 242 }; 243 struct drm_amdgpu_gem_wait_idle_out { 244 __u32 status; 245 __u32 domain; 246 }; 247 union drm_amdgpu_gem_wait_idle { 248 struct drm_amdgpu_gem_wait_idle_in in; 249 struct drm_amdgpu_gem_wait_idle_out out; 250 }; 251 struct drm_amdgpu_wait_cs_in { 252 __u64 handle; 253 __u64 timeout; 254 __u32 ip_type; 255 __u32 ip_instance; 256 __u32 ring; 257 __u32 ctx_id; 258 }; 259 struct drm_amdgpu_wait_cs_out { 260 __u64 status; 261 }; 262 union drm_amdgpu_wait_cs { 263 struct drm_amdgpu_wait_cs_in in; 264 struct drm_amdgpu_wait_cs_out out; 265 }; 266 struct drm_amdgpu_fence { 267 __u32 ctx_id; 268 __u32 ip_type; 269 __u32 ip_instance; 270 __u32 ring; 271 __u64 seq_no; 272 }; 273 struct drm_amdgpu_wait_fences_in { 274 __u64 fences; 275 __u32 fence_count; 276 __u32 wait_all; 277 __u64 timeout_ns; 278 }; 279 struct drm_amdgpu_wait_fences_out { 280 __u32 status; 281 __u32 first_signaled; 282 }; 283 union drm_amdgpu_wait_fences { 284 struct drm_amdgpu_wait_fences_in in; 285 struct drm_amdgpu_wait_fences_out out; 286 }; 287 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 288 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 289 struct drm_amdgpu_gem_op { 290 __u32 handle; 291 __u32 op; 292 __u64 value; 293 }; 294 #define AMDGPU_VA_OP_MAP 1 295 #define AMDGPU_VA_OP_UNMAP 2 296 #define AMDGPU_VA_OP_CLEAR 3 297 #define AMDGPU_VA_OP_REPLACE 4 298 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 299 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 300 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 301 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 302 #define AMDGPU_VM_PAGE_PRT (1 << 4) 303 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 304 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 305 #define AMDGPU_VM_MTYPE_NC (1 << 5) 306 #define AMDGPU_VM_MTYPE_WC (2 << 5) 307 #define AMDGPU_VM_MTYPE_CC (3 << 5) 308 #define AMDGPU_VM_MTYPE_UC (4 << 5) 309 #define AMDGPU_VM_MTYPE_RW (5 << 5) 310 struct drm_amdgpu_gem_va { 311 __u32 handle; 312 __u32 _pad; 313 __u32 operation; 314 __u32 flags; 315 __u64 va_address; 316 __u64 offset_in_bo; 317 __u64 map_size; 318 }; 319 #define AMDGPU_HW_IP_GFX 0 320 #define AMDGPU_HW_IP_COMPUTE 1 321 #define AMDGPU_HW_IP_DMA 2 322 #define AMDGPU_HW_IP_UVD 3 323 #define AMDGPU_HW_IP_VCE 4 324 #define AMDGPU_HW_IP_UVD_ENC 5 325 #define AMDGPU_HW_IP_VCN_DEC 6 326 #define AMDGPU_HW_IP_VCN_ENC 7 327 #define AMDGPU_HW_IP_VCN_JPEG 8 328 #define AMDGPU_HW_IP_NUM 9 329 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 330 #define AMDGPU_CHUNK_ID_IB 0x01 331 #define AMDGPU_CHUNK_ID_FENCE 0x02 332 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 333 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 334 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 335 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 336 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 337 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 338 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 339 struct drm_amdgpu_cs_chunk { 340 __u32 chunk_id; 341 __u32 length_dw; 342 __u64 chunk_data; 343 }; 344 struct drm_amdgpu_cs_in { 345 __u32 ctx_id; 346 __u32 bo_list_handle; 347 __u32 num_chunks; 348 __u32 flags; 349 __u64 chunks; 350 }; 351 struct drm_amdgpu_cs_out { 352 __u64 handle; 353 }; 354 union drm_amdgpu_cs { 355 struct drm_amdgpu_cs_in in; 356 struct drm_amdgpu_cs_out out; 357 }; 358 #define AMDGPU_IB_FLAG_CE (1 << 0) 359 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 360 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 361 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 362 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 363 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 364 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 365 struct drm_amdgpu_cs_chunk_ib { 366 __u32 _pad; 367 __u32 flags; 368 __u64 va_start; 369 __u32 ib_bytes; 370 __u32 ip_type; 371 __u32 ip_instance; 372 __u32 ring; 373 }; 374 struct drm_amdgpu_cs_chunk_dep { 375 __u32 ip_type; 376 __u32 ip_instance; 377 __u32 ring; 378 __u32 ctx_id; 379 __u64 handle; 380 }; 381 struct drm_amdgpu_cs_chunk_fence { 382 __u32 handle; 383 __u32 offset; 384 }; 385 struct drm_amdgpu_cs_chunk_sem { 386 __u32 handle; 387 }; 388 struct drm_amdgpu_cs_chunk_syncobj { 389 __u32 handle; 390 __u32 flags; 391 __u64 point; 392 }; 393 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 394 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 395 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 396 union drm_amdgpu_fence_to_handle { 397 struct { 398 struct drm_amdgpu_fence fence; 399 __u32 what; 400 __u32 pad; 401 } in; 402 struct { 403 __u32 handle; 404 } out; 405 }; 406 struct drm_amdgpu_cs_chunk_data { 407 union { 408 struct drm_amdgpu_cs_chunk_ib ib_data; 409 struct drm_amdgpu_cs_chunk_fence fence_data; 410 }; 411 }; 412 #define AMDGPU_IDS_FLAGS_FUSION 0x1 413 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 414 #define AMDGPU_IDS_FLAGS_TMZ 0x4 415 #define AMDGPU_INFO_ACCEL_WORKING 0x00 416 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 417 #define AMDGPU_INFO_HW_IP_INFO 0x02 418 #define AMDGPU_INFO_HW_IP_COUNT 0x03 419 #define AMDGPU_INFO_TIMESTAMP 0x05 420 #define AMDGPU_INFO_FW_VERSION 0x0e 421 #define AMDGPU_INFO_FW_VCE 0x1 422 #define AMDGPU_INFO_FW_UVD 0x2 423 #define AMDGPU_INFO_FW_GMC 0x03 424 #define AMDGPU_INFO_FW_GFX_ME 0x04 425 #define AMDGPU_INFO_FW_GFX_PFP 0x05 426 #define AMDGPU_INFO_FW_GFX_CE 0x06 427 #define AMDGPU_INFO_FW_GFX_RLC 0x07 428 #define AMDGPU_INFO_FW_GFX_MEC 0x08 429 #define AMDGPU_INFO_FW_SMC 0x0a 430 #define AMDGPU_INFO_FW_SDMA 0x0b 431 #define AMDGPU_INFO_FW_SOS 0x0c 432 #define AMDGPU_INFO_FW_ASD 0x0d 433 #define AMDGPU_INFO_FW_VCN 0x0e 434 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 435 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 436 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 437 #define AMDGPU_INFO_FW_DMCU 0x12 438 #define AMDGPU_INFO_FW_TA 0x13 439 #define AMDGPU_INFO_FW_DMCUB 0x14 440 #define AMDGPU_INFO_FW_TOC 0x15 441 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 442 #define AMDGPU_INFO_VRAM_USAGE 0x10 443 #define AMDGPU_INFO_GTT_USAGE 0x11 444 #define AMDGPU_INFO_GDS_CONFIG 0x13 445 #define AMDGPU_INFO_VRAM_GTT 0x14 446 #define AMDGPU_INFO_READ_MMR_REG 0x15 447 #define AMDGPU_INFO_DEV_INFO 0x16 448 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 449 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 450 #define AMDGPU_INFO_MEMORY 0x19 451 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 452 #define AMDGPU_INFO_VBIOS 0x1B 453 #define AMDGPU_INFO_VBIOS_SIZE 0x1 454 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 455 #define AMDGPU_INFO_VBIOS_INFO 0x3 456 #define AMDGPU_INFO_NUM_HANDLES 0x1C 457 #define AMDGPU_INFO_SENSOR 0x1D 458 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 459 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 460 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 461 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 462 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 463 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 464 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 465 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 466 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 467 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 468 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 469 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 470 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 471 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 472 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 473 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 474 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 475 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 476 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 477 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 478 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 479 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 480 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 481 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 482 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 483 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 484 #define AMDGPU_INFO_VIDEO_CAPS 0x21 485 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 486 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 487 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 488 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 489 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 490 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 491 struct drm_amdgpu_query_fw { 492 __u32 fw_type; 493 __u32 ip_instance; 494 __u32 index; 495 __u32 _pad; 496 }; 497 struct drm_amdgpu_info { 498 __u64 return_pointer; 499 __u32 return_size; 500 __u32 query; 501 union { 502 struct { 503 __u32 id; 504 __u32 _pad; 505 } mode_crtc; 506 struct { 507 __u32 type; 508 __u32 ip_instance; 509 } query_hw_ip; 510 struct { 511 __u32 dword_offset; 512 __u32 count; 513 __u32 instance; 514 __u32 flags; 515 } read_mmr_reg; 516 struct drm_amdgpu_query_fw query_fw; 517 struct { 518 __u32 type; 519 __u32 offset; 520 } vbios_info; 521 struct { 522 __u32 type; 523 } sensor_info; 524 struct { 525 __u32 type; 526 } video_cap; 527 }; 528 }; 529 struct drm_amdgpu_info_gds { 530 __u32 gds_gfx_partition_size; 531 __u32 compute_partition_size; 532 __u32 gds_total_size; 533 __u32 gws_per_gfx_partition; 534 __u32 gws_per_compute_partition; 535 __u32 oa_per_gfx_partition; 536 __u32 oa_per_compute_partition; 537 __u32 _pad; 538 }; 539 struct drm_amdgpu_info_vram_gtt { 540 __u64 vram_size; 541 __u64 vram_cpu_accessible_size; 542 __u64 gtt_size; 543 }; 544 struct drm_amdgpu_heap_info { 545 __u64 total_heap_size; 546 __u64 usable_heap_size; 547 __u64 heap_usage; 548 __u64 max_allocation; 549 }; 550 struct drm_amdgpu_memory_info { 551 struct drm_amdgpu_heap_info vram; 552 struct drm_amdgpu_heap_info cpu_accessible_vram; 553 struct drm_amdgpu_heap_info gtt; 554 }; 555 struct drm_amdgpu_info_firmware { 556 __u32 ver; 557 __u32 feature; 558 }; 559 struct drm_amdgpu_info_vbios { 560 __u8 name[64]; 561 __u8 vbios_pn[64]; 562 __u32 version; 563 __u32 pad; 564 __u8 vbios_ver_str[32]; 565 __u8 date[32]; 566 }; 567 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 568 #define AMDGPU_VRAM_TYPE_GDDR1 1 569 #define AMDGPU_VRAM_TYPE_DDR2 2 570 #define AMDGPU_VRAM_TYPE_GDDR3 3 571 #define AMDGPU_VRAM_TYPE_GDDR4 4 572 #define AMDGPU_VRAM_TYPE_GDDR5 5 573 #define AMDGPU_VRAM_TYPE_HBM 6 574 #define AMDGPU_VRAM_TYPE_DDR3 7 575 #define AMDGPU_VRAM_TYPE_DDR4 8 576 #define AMDGPU_VRAM_TYPE_GDDR6 9 577 #define AMDGPU_VRAM_TYPE_DDR5 10 578 struct drm_amdgpu_info_device { 579 __u32 device_id; 580 __u32 chip_rev; 581 __u32 external_rev; 582 __u32 pci_rev; 583 __u32 family; 584 __u32 num_shader_engines; 585 __u32 num_shader_arrays_per_engine; 586 __u32 gpu_counter_freq; 587 __u64 max_engine_clock; 588 __u64 max_memory_clock; 589 __u32 cu_active_number; 590 __u32 cu_ao_mask; 591 __u32 cu_bitmap[4][4]; 592 __u32 enabled_rb_pipes_mask; 593 __u32 num_rb_pipes; 594 __u32 num_hw_gfx_contexts; 595 __u32 _pad; 596 __u64 ids_flags; 597 __u64 virtual_address_offset; 598 __u64 virtual_address_max; 599 __u32 virtual_address_alignment; 600 __u32 pte_fragment_size; 601 __u32 gart_page_size; 602 __u32 ce_ram_size; 603 __u32 vram_type; 604 __u32 vram_bit_width; 605 __u32 vce_harvest_config; 606 __u32 gc_double_offchip_lds_buf; 607 __u64 prim_buf_gpu_addr; 608 __u64 pos_buf_gpu_addr; 609 __u64 cntl_sb_buf_gpu_addr; 610 __u64 param_buf_gpu_addr; 611 __u32 prim_buf_size; 612 __u32 pos_buf_size; 613 __u32 cntl_sb_buf_size; 614 __u32 param_buf_size; 615 __u32 wave_front_size; 616 __u32 num_shader_visible_vgprs; 617 __u32 num_cu_per_sh; 618 __u32 num_tcc_blocks; 619 __u32 gs_vgt_table_depth; 620 __u32 gs_prim_buffer_depth; 621 __u32 max_gs_waves_per_vgt; 622 __u32 _pad1; 623 __u32 cu_ao_bitmap[4][4]; 624 __u64 high_va_offset; 625 __u64 high_va_max; 626 __u32 pa_sc_tile_steering_override; 627 __u64 tcc_disabled_mask; 628 }; 629 struct drm_amdgpu_info_hw_ip { 630 __u32 hw_ip_version_major; 631 __u32 hw_ip_version_minor; 632 __u64 capabilities_flags; 633 __u32 ib_start_alignment; 634 __u32 ib_size_alignment; 635 __u32 available_rings; 636 __u32 _pad; 637 }; 638 struct drm_amdgpu_info_num_handles { 639 __u32 uvd_max_handles; 640 __u32 uvd_used_handles; 641 }; 642 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 643 struct drm_amdgpu_info_vce_clock_table_entry { 644 __u32 sclk; 645 __u32 mclk; 646 __u32 eclk; 647 __u32 pad; 648 }; 649 struct drm_amdgpu_info_vce_clock_table { 650 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 651 __u32 num_valid_entries; 652 __u32 pad; 653 }; 654 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 655 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 656 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 657 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 658 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 659 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 660 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 661 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 662 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 663 struct drm_amdgpu_info_video_codec_info { 664 __u32 valid; 665 __u32 max_width; 666 __u32 max_height; 667 __u32 max_pixels_per_frame; 668 __u32 max_level; 669 __u32 pad; 670 }; 671 struct drm_amdgpu_info_video_caps { 672 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 673 }; 674 #define AMDGPU_FAMILY_UNKNOWN 0 675 #define AMDGPU_FAMILY_SI 110 676 #define AMDGPU_FAMILY_CI 120 677 #define AMDGPU_FAMILY_KV 125 678 #define AMDGPU_FAMILY_VI 130 679 #define AMDGPU_FAMILY_CZ 135 680 #define AMDGPU_FAMILY_AI 141 681 #define AMDGPU_FAMILY_RV 142 682 #define AMDGPU_FAMILY_NV 143 683 #define AMDGPU_FAMILY_VGH 144 684 #define AMDGPU_FAMILY_YC 146 685 #ifdef __cplusplus 686 } 687 #endif 688 #endif 689