1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _COMEDI_H 20 #define _COMEDI_H 21 #define COMEDI_MAJORVERSION 0 22 #define COMEDI_MINORVERSION 7 23 #define COMEDI_MICROVERSION 76 24 #define VERSION "0.7.76" 25 #define COMEDI_MAJOR 98 26 #define COMEDI_NDEVICES 16 27 #define COMEDI_NDEVCONFOPTS 32 28 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 29 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 30 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 31 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 32 #define COMEDI_DEVCONF_AUX_DATA_HI 29 33 #define COMEDI_DEVCONF_AUX_DATA_LO 30 34 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 35 #define COMEDI_NAMELEN 20 36 #define CR_PACK(chan,rng,aref) ((((aref) & 0x3) << 24) | (((rng) & 0xff) << 16) | (chan)) 37 #define CR_PACK_FLAGS(chan,range,aref,flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 38 #define CR_CHAN(a) ((a) & 0xffff) 39 #define CR_RANGE(a) (((a) >> 16) & 0xff) 40 #define CR_AREF(a) (((a) >> 24) & 0x03) 41 #define CR_FLAGS_MASK 0xfc000000 42 #define CR_ALT_FILTER 0x04000000 43 #define CR_DITHER CR_ALT_FILTER 44 #define CR_DEGLITCH CR_ALT_FILTER 45 #define CR_ALT_SOURCE 0x08000000 46 #define CR_EDGE 0x40000000 47 #define CR_INVERT 0x80000000 48 #define AREF_GROUND 0x00 49 #define AREF_COMMON 0x01 50 #define AREF_DIFF 0x02 51 #define AREF_OTHER 0x03 52 #define GPCT_RESET 0x0001 53 #define GPCT_SET_SOURCE 0x0002 54 #define GPCT_SET_GATE 0x0004 55 #define GPCT_SET_DIRECTION 0x0008 56 #define GPCT_SET_OPERATION 0x0010 57 #define GPCT_ARM 0x0020 58 #define GPCT_DISARM 0x0040 59 #define GPCT_GET_INT_CLK_FRQ 0x0080 60 #define GPCT_INT_CLOCK 0x0001 61 #define GPCT_EXT_PIN 0x0002 62 #define GPCT_NO_GATE 0x0004 63 #define GPCT_UP 0x0008 64 #define GPCT_DOWN 0x0010 65 #define GPCT_HWUD 0x0020 66 #define GPCT_SIMPLE_EVENT 0x0040 67 #define GPCT_SINGLE_PERIOD 0x0080 68 #define GPCT_SINGLE_PW 0x0100 69 #define GPCT_CONT_PULSE_OUT 0x0200 70 #define GPCT_SINGLE_PULSE_OUT 0x0400 71 #define INSN_MASK_WRITE 0x8000000 72 #define INSN_MASK_READ 0x4000000 73 #define INSN_MASK_SPECIAL 0x2000000 74 #define INSN_READ (0 | INSN_MASK_READ) 75 #define INSN_WRITE (1 | INSN_MASK_WRITE) 76 #define INSN_BITS (2 | INSN_MASK_READ | INSN_MASK_WRITE) 77 #define INSN_CONFIG (3 | INSN_MASK_READ | INSN_MASK_WRITE) 78 #define INSN_DEVICE_CONFIG (INSN_CONFIG | INSN_MASK_SPECIAL) 79 #define INSN_GTOD (4 | INSN_MASK_READ | INSN_MASK_SPECIAL) 80 #define INSN_WAIT (5 | INSN_MASK_WRITE | INSN_MASK_SPECIAL) 81 #define INSN_INTTRIG (6 | INSN_MASK_WRITE | INSN_MASK_SPECIAL) 82 #define CMDF_BOGUS 0x00000001 83 #define CMDF_PRIORITY 0x00000008 84 #define CMDF_WAKE_EOS 0x00000020 85 #define CMDF_WRITE 0x00000040 86 #define CMDF_RAWDATA 0x00000080 87 #define CMDF_ROUND_MASK 0x00030000 88 #define CMDF_ROUND_NEAREST 0x00000000 89 #define CMDF_ROUND_DOWN 0x00010000 90 #define CMDF_ROUND_UP 0x00020000 91 #define CMDF_ROUND_UP_NEXT 0x00030000 92 #define COMEDI_EV_START 0x00040000 93 #define COMEDI_EV_SCAN_BEGIN 0x00080000 94 #define COMEDI_EV_CONVERT 0x00100000 95 #define COMEDI_EV_SCAN_END 0x00200000 96 #define COMEDI_EV_STOP 0x00400000 97 #define TRIG_BOGUS CMDF_BOGUS 98 #define TRIG_RT CMDF_PRIORITY 99 #define TRIG_WAKE_EOS CMDF_WAKE_EOS 100 #define TRIG_WRITE CMDF_WRITE 101 #define TRIG_ROUND_MASK CMDF_ROUND_MASK 102 #define TRIG_ROUND_NEAREST CMDF_ROUND_NEAREST 103 #define TRIG_ROUND_DOWN CMDF_ROUND_DOWN 104 #define TRIG_ROUND_UP CMDF_ROUND_UP 105 #define TRIG_ROUND_UP_NEXT CMDF_ROUND_UP_NEXT 106 #define TRIG_ANY 0xffffffff 107 #define TRIG_INVALID 0x00000000 108 #define TRIG_NONE 0x00000001 109 #define TRIG_NOW 0x00000002 110 #define TRIG_FOLLOW 0x00000004 111 #define TRIG_TIME 0x00000008 112 #define TRIG_TIMER 0x00000010 113 #define TRIG_COUNT 0x00000020 114 #define TRIG_EXT 0x00000040 115 #define TRIG_INT 0x00000080 116 #define TRIG_OTHER 0x00000100 117 #define SDF_BUSY 0x0001 118 #define SDF_BUSY_OWNER 0x0002 119 #define SDF_LOCKED 0x0004 120 #define SDF_LOCK_OWNER 0x0008 121 #define SDF_MAXDATA 0x0010 122 #define SDF_FLAGS 0x0020 123 #define SDF_RANGETYPE 0x0040 124 #define SDF_PWM_COUNTER 0x0080 125 #define SDF_PWM_HBRIDGE 0x0100 126 #define SDF_CMD 0x1000 127 #define SDF_SOFT_CALIBRATED 0x2000 128 #define SDF_CMD_WRITE 0x4000 129 #define SDF_CMD_READ 0x8000 130 #define SDF_READABLE 0x00010000 131 #define SDF_WRITABLE 0x00020000 132 #define SDF_WRITEABLE SDF_WRITABLE 133 #define SDF_INTERNAL 0x00040000 134 #define SDF_GROUND 0x00100000 135 #define SDF_COMMON 0x00200000 136 #define SDF_DIFF 0x00400000 137 #define SDF_OTHER 0x00800000 138 #define SDF_DITHER 0x01000000 139 #define SDF_DEGLITCH 0x02000000 140 #define SDF_MMAP 0x04000000 141 #define SDF_RUNNING 0x08000000 142 #define SDF_LSAMPL 0x10000000 143 #define SDF_PACKED 0x20000000 144 enum comedi_subdevice_type { 145 COMEDI_SUBD_UNUSED, 146 COMEDI_SUBD_AI, 147 COMEDI_SUBD_AO, 148 COMEDI_SUBD_DI, 149 COMEDI_SUBD_DO, 150 COMEDI_SUBD_DIO, 151 COMEDI_SUBD_COUNTER, 152 COMEDI_SUBD_TIMER, 153 COMEDI_SUBD_MEMORY, 154 COMEDI_SUBD_CALIB, 155 COMEDI_SUBD_PROC, 156 COMEDI_SUBD_SERIAL, 157 COMEDI_SUBD_PWM 158 }; 159 enum comedi_io_direction { 160 COMEDI_INPUT = 0, 161 COMEDI_OUTPUT = 1, 162 COMEDI_OPENDRAIN = 2 163 }; 164 enum configuration_ids { 165 INSN_CONFIG_DIO_INPUT = COMEDI_INPUT, 166 INSN_CONFIG_DIO_OUTPUT = COMEDI_OUTPUT, 167 INSN_CONFIG_DIO_OPENDRAIN = COMEDI_OPENDRAIN, 168 INSN_CONFIG_ANALOG_TRIG = 16, 169 INSN_CONFIG_ALT_SOURCE = 20, 170 INSN_CONFIG_DIGITAL_TRIG = 21, 171 INSN_CONFIG_BLOCK_SIZE = 22, 172 INSN_CONFIG_TIMER_1 = 23, 173 INSN_CONFIG_FILTER = 24, 174 INSN_CONFIG_CHANGE_NOTIFY = 25, 175 INSN_CONFIG_SERIAL_CLOCK = 26, 176 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 177 INSN_CONFIG_DIO_QUERY = 28, 178 INSN_CONFIG_PWM_OUTPUT = 29, 179 INSN_CONFIG_GET_PWM_OUTPUT = 30, 180 INSN_CONFIG_ARM = 31, 181 INSN_CONFIG_DISARM = 32, 182 INSN_CONFIG_GET_COUNTER_STATUS = 33, 183 INSN_CONFIG_RESET = 34, 184 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, 185 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, 186 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, 187 INSN_CONFIG_SET_GATE_SRC = 2001, 188 INSN_CONFIG_GET_GATE_SRC = 2002, 189 INSN_CONFIG_SET_CLOCK_SRC = 2003, 190 INSN_CONFIG_GET_CLOCK_SRC = 2004, 191 INSN_CONFIG_SET_OTHER_SRC = 2005, 192 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, 193 INSN_CONFIG_SET_COUNTER_MODE = 4097, 194 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, 195 INSN_CONFIG_8254_READ_STATUS = 4098, 196 INSN_CONFIG_SET_ROUTING = 4099, 197 INSN_CONFIG_GET_ROUTING = 4109, 198 INSN_CONFIG_PWM_SET_PERIOD = 5000, 199 INSN_CONFIG_PWM_GET_PERIOD = 5001, 200 INSN_CONFIG_GET_PWM_STATUS = 5002, 201 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, 202 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004, 203 INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS = 5005, 204 }; 205 enum device_config_route_ids { 206 INSN_DEVICE_CONFIG_TEST_ROUTE = 0, 207 INSN_DEVICE_CONFIG_CONNECT_ROUTE = 1, 208 INSN_DEVICE_CONFIG_DISCONNECT_ROUTE = 2, 209 INSN_DEVICE_CONFIG_GET_ROUTES = 3, 210 }; 211 enum comedi_digital_trig_op { 212 COMEDI_DIGITAL_TRIG_DISABLE = 0, 213 COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1, 214 COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2 215 }; 216 enum comedi_support_level { 217 COMEDI_UNKNOWN_SUPPORT = 0, 218 COMEDI_SUPPORTED, 219 COMEDI_UNSUPPORTED 220 }; 221 enum comedi_counter_status_flags { 222 COMEDI_COUNTER_ARMED = 0x1, 223 COMEDI_COUNTER_COUNTING = 0x2, 224 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 225 }; 226 #define CIO 'd' 227 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig) 228 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo) 229 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo) 230 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo) 231 #define COMEDI_LOCK _IO(CIO, 5) 232 #define COMEDI_UNLOCK _IO(CIO, 6) 233 #define COMEDI_CANCEL _IO(CIO, 7) 234 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo) 235 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd) 236 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd) 237 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist) 238 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn) 239 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig) 240 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo) 241 #define COMEDI_POLL _IO(CIO, 15) 242 #define COMEDI_SETRSUBD _IO(CIO, 16) 243 #define COMEDI_SETWSUBD _IO(CIO, 17) 244 struct comedi_insn { 245 unsigned int insn; 246 unsigned int n; 247 unsigned int __user * data; 248 unsigned int subdev; 249 unsigned int chanspec; 250 unsigned int unused[3]; 251 }; 252 struct comedi_insnlist { 253 unsigned int n_insns; 254 struct comedi_insn __user * insns; 255 }; 256 struct comedi_cmd { 257 unsigned int subdev; 258 unsigned int flags; 259 unsigned int start_src; 260 unsigned int start_arg; 261 unsigned int scan_begin_src; 262 unsigned int scan_begin_arg; 263 unsigned int convert_src; 264 unsigned int convert_arg; 265 unsigned int scan_end_src; 266 unsigned int scan_end_arg; 267 unsigned int stop_src; 268 unsigned int stop_arg; 269 unsigned int * chanlist; 270 unsigned int chanlist_len; 271 short __user * data; 272 unsigned int data_len; 273 }; 274 struct comedi_chaninfo { 275 unsigned int subdev; 276 unsigned int __user * maxdata_list; 277 unsigned int __user * flaglist; 278 unsigned int __user * rangelist; 279 unsigned int unused[4]; 280 }; 281 struct comedi_rangeinfo { 282 unsigned int range_type; 283 void __user * range_ptr; 284 }; 285 struct comedi_krange { 286 int min; 287 int max; 288 unsigned int flags; 289 }; 290 struct comedi_subdinfo { 291 unsigned int type; 292 unsigned int n_chan; 293 unsigned int subd_flags; 294 unsigned int timer_type; 295 unsigned int len_chanlist; 296 unsigned int maxdata; 297 unsigned int flags; 298 unsigned int range_type; 299 unsigned int settling_time_0; 300 unsigned int insn_bits_support; 301 unsigned int unused[8]; 302 }; 303 struct comedi_devinfo { 304 unsigned int version_code; 305 unsigned int n_subdevs; 306 char driver_name[COMEDI_NAMELEN]; 307 char board_name[COMEDI_NAMELEN]; 308 int read_subdevice; 309 int write_subdevice; 310 int unused[30]; 311 }; 312 struct comedi_devconfig { 313 char board_name[COMEDI_NAMELEN]; 314 int options[COMEDI_NDEVCONFOPTS]; 315 }; 316 struct comedi_bufconfig { 317 unsigned int subdevice; 318 unsigned int flags; 319 unsigned int maximum_size; 320 unsigned int size; 321 unsigned int unused[4]; 322 }; 323 struct comedi_bufinfo { 324 unsigned int subdevice; 325 unsigned int bytes_read; 326 unsigned int buf_write_ptr; 327 unsigned int buf_read_ptr; 328 unsigned int buf_write_count; 329 unsigned int buf_read_count; 330 unsigned int bytes_written; 331 unsigned int unused[4]; 332 }; 333 #define __RANGE(a,b) ((((a) & 0xffff) << 16) | ((b) & 0xffff)) 334 #define RANGE_OFFSET(a) (((a) >> 16) & 0xffff) 335 #define RANGE_LENGTH(b) ((b) & 0xffff) 336 #define RF_UNIT(flags) ((flags) & 0xff) 337 #define RF_EXTERNAL 0x100 338 #define UNIT_volt 0 339 #define UNIT_mA 1 340 #define UNIT_none 2 341 #define COMEDI_MIN_SPEED 0xffffffffu 342 enum i8254_mode { 343 I8254_MODE0 = (0 << 1), 344 I8254_MODE1 = (1 << 1), 345 I8254_MODE2 = (2 << 1), 346 I8254_MODE3 = (3 << 1), 347 I8254_MODE4 = (4 << 1), 348 I8254_MODE5 = (5 << 1), 349 I8254_BCD = 1, 350 I8254_BINARY = 0 351 }; 352 #define NI_NAMES_BASE 0x8000u 353 #define _TERM_N(base,n,x) ((base) + ((x) & ((n) - 1))) 354 #define NI_PFI(x) _TERM_N(NI_NAMES_BASE, 64, x) 355 #define TRIGGER_LINE(x) _TERM_N(NI_PFI(- 1) + 1, 8, x) 356 #define NI_RTSI_BRD(x) _TERM_N(TRIGGER_LINE(- 1) + 1, 4, x) 357 #define NI_MAX_COUNTERS 8 358 #define NI_COUNTER_NAMES_BASE (NI_RTSI_BRD(- 1) + 1) 359 #define NI_CtrSource(x) _TERM_N(NI_COUNTER_NAMES_BASE, NI_MAX_COUNTERS, x) 360 #define NI_GATES_NAMES_BASE (NI_CtrSource(- 1) + 1) 361 #define NI_CtrGate(x) _TERM_N(NI_GATES_NAMES_BASE, NI_MAX_COUNTERS, x) 362 #define NI_CtrAux(x) _TERM_N(NI_CtrGate(- 1) + 1, NI_MAX_COUNTERS, x) 363 #define NI_CtrA(x) _TERM_N(NI_CtrAux(- 1) + 1, NI_MAX_COUNTERS, x) 364 #define NI_CtrB(x) _TERM_N(NI_CtrA(- 1) + 1, NI_MAX_COUNTERS, x) 365 #define NI_CtrZ(x) _TERM_N(NI_CtrB(- 1) + 1, NI_MAX_COUNTERS, x) 366 #define NI_GATES_NAMES_MAX NI_CtrZ(- 1) 367 #define NI_CtrArmStartTrigger(x) _TERM_N(NI_CtrZ(- 1) + 1, NI_MAX_COUNTERS, x) 368 #define NI_CtrInternalOutput(x) _TERM_N(NI_CtrArmStartTrigger(- 1) + 1, NI_MAX_COUNTERS, x) 369 #define NI_CtrOut(x) _TERM_N(NI_CtrInternalOutput(- 1) + 1, NI_MAX_COUNTERS, x) 370 #define NI_CtrSampleClock(x) _TERM_N(NI_CtrOut(- 1) + 1, NI_MAX_COUNTERS, x) 371 #define NI_COUNTER_NAMES_MAX NI_CtrSampleClock(- 1) 372 enum ni_common_signal_names { 373 PXI_Star = NI_COUNTER_NAMES_MAX + 1, 374 PXI_Clk10, 375 PXIe_Clk100, 376 NI_AI_SampleClock, 377 NI_AI_SampleClockTimebase, 378 NI_AI_StartTrigger, 379 NI_AI_ReferenceTrigger, 380 NI_AI_ConvertClock, 381 NI_AI_ConvertClockTimebase, 382 NI_AI_PauseTrigger, 383 NI_AI_HoldCompleteEvent, 384 NI_AI_HoldComplete, 385 NI_AI_ExternalMUXClock, 386 NI_AI_STOP, 387 NI_AO_SampleClock, 388 NI_AO_SampleClockTimebase, 389 NI_AO_StartTrigger, 390 NI_AO_PauseTrigger, 391 NI_DI_SampleClock, 392 NI_DI_SampleClockTimebase, 393 NI_DI_StartTrigger, 394 NI_DI_ReferenceTrigger, 395 NI_DI_PauseTrigger, 396 NI_DI_InputBufferFull, 397 NI_DI_ReadyForStartEvent, 398 NI_DI_ReadyForTransferEventBurst, 399 NI_DI_ReadyForTransferEventPipelined, 400 NI_DO_SampleClock, 401 NI_DO_SampleClockTimebase, 402 NI_DO_StartTrigger, 403 NI_DO_PauseTrigger, 404 NI_DO_OutputBufferFull, 405 NI_DO_DataActiveEvent, 406 NI_DO_ReadyForStartEvent, 407 NI_DO_ReadyForTransferEvent, 408 NI_MasterTimebase, 409 NI_20MHzTimebase, 410 NI_80MHzTimebase, 411 NI_100MHzTimebase, 412 NI_200MHzTimebase, 413 NI_100kHzTimebase, 414 NI_10MHzRefClock, 415 NI_FrequencyOutput, 416 NI_ChangeDetectionEvent, 417 NI_AnalogComparisonEvent, 418 NI_WatchdogExpiredEvent, 419 NI_WatchdogExpirationTrigger, 420 NI_SCXI_Trig1, 421 NI_LogicLow, 422 NI_LogicHigh, 423 NI_ExternalStrobe, 424 NI_PFI_DO, 425 NI_CaseGround, 426 NI_RGOUT0, 427 _NI_NAMES_MAX_PLUS_1, 428 NI_NUM_NAMES = _NI_NAMES_MAX_PLUS_1 - NI_NAMES_BASE, 429 }; 430 #define NI_USUAL_PFI_SELECT(x) (((x) < 10) ? (0x1 + (x)) : (0xb + (x))) 431 #define NI_USUAL_RTSI_SELECT(x) (((x) < 7) ? (0xb + (x)) : 0x1b) 432 #define NI_GPCT_COUNTING_MODE_SHIFT 16 433 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20 434 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 435 enum ni_gpct_mode_bits { 436 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 437 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 438 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 439 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 440 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 441 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 442 NI_GPCT_STOP_MODE_MASK = 0x60, 443 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 444 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 445 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 446 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 447 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 448 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 449 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 450 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 451 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 452 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 453 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 454 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 455 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 456 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 457 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 458 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 459 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 460 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 461 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 462 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 463 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 464 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 465 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 466 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 467 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 468 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 469 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 470 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 471 NI_GPCT_COUNTING_DIRECTION_MASK = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 472 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 473 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 474 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 475 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 476 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 477 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 478 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 479 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 480 NI_GPCT_OR_GATE_BIT = 0x10000000, 481 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 482 }; 483 enum ni_gpct_clock_source_bits { 484 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 485 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 486 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 487 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 488 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 489 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 490 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 491 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, 492 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 493 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 494 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 495 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 496 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 497 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, 498 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, 499 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 500 }; 501 #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + (x)) 502 #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + (x)) 503 #define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + (x)) 504 enum ni_gpct_gate_select { 505 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 506 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 507 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 508 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 509 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 510 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 511 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 512 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 513 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 514 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 515 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 516 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 517 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 518 }; 519 #define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + (x)) 520 #define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x) 521 #define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x) 522 #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + (x)) 523 enum ni_gpct_other_index { 524 NI_GPCT_SOURCE_ENCODER_A, 525 NI_GPCT_SOURCE_ENCODER_B, 526 NI_GPCT_SOURCE_ENCODER_Z 527 }; 528 enum ni_gpct_other_select { 529 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 530 }; 531 #define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x) 532 enum ni_gpct_arm_source { 533 NI_GPCT_ARM_IMMEDIATE = 0x0, 534 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, 535 NI_GPCT_HW_ARM = 0x1000, 536 NI_GPCT_ARM_UNKNOWN = NI_GPCT_HW_ARM, 537 }; 538 enum ni_gpct_filter_select { 539 NI_GPCT_FILTER_OFF = 0x0, 540 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 541 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 542 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 543 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 544 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 545 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 546 }; 547 enum ni_pfi_filter_select { 548 NI_PFI_FILTER_OFF = 0x0, 549 NI_PFI_FILTER_125ns = 0x1, 550 NI_PFI_FILTER_6425ns = 0x2, 551 NI_PFI_FILTER_2550us = 0x3 552 }; 553 enum ni_mio_clock_source { 554 NI_MIO_INTERNAL_CLOCK = 0, 555 NI_MIO_RTSI_CLOCK = 1, 556 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 557 NI_MIO_PLL_PXI10_CLOCK = 3, 558 NI_MIO_PLL_RTSI0_CLOCK = 4 559 }; 560 #define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x)) 561 enum ni_rtsi_routing { 562 NI_RTSI_OUTPUT_ADR_START1 = 0, 563 NI_RTSI_OUTPUT_ADR_START2 = 1, 564 NI_RTSI_OUTPUT_SCLKG = 2, 565 NI_RTSI_OUTPUT_DACUPDN = 3, 566 NI_RTSI_OUTPUT_DA_START1 = 4, 567 NI_RTSI_OUTPUT_G_SRC0 = 5, 568 NI_RTSI_OUTPUT_G_GATE0 = 6, 569 NI_RTSI_OUTPUT_RGOUT0 = 7, 570 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 571 NI_RTSI_OUTPUT_RTSI_OSC = 12 572 }; 573 #define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x)) 574 enum ni_pfi_routing { 575 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 576 NI_PFI_OUTPUT_AI_START1 = 1, 577 NI_PFI_OUTPUT_AI_START2 = 2, 578 NI_PFI_OUTPUT_AI_CONVERT = 3, 579 NI_PFI_OUTPUT_G_SRC1 = 4, 580 NI_PFI_OUTPUT_G_GATE1 = 5, 581 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 582 NI_PFI_OUTPUT_AO_START1 = 7, 583 NI_PFI_OUTPUT_AI_START_PULSE = 8, 584 NI_PFI_OUTPUT_G_SRC0 = 9, 585 NI_PFI_OUTPUT_G_GATE0 = 10, 586 NI_PFI_OUTPUT_EXT_STROBE = 11, 587 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 588 NI_PFI_OUTPUT_GOUT0 = 13, 589 NI_PFI_OUTPUT_GOUT1 = 14, 590 NI_PFI_OUTPUT_FREQ_OUT = 15, 591 NI_PFI_OUTPUT_PFI_DO = 16, 592 NI_PFI_OUTPUT_I_ATRIG = 17, 593 NI_PFI_OUTPUT_RTSI0 = 18, 594 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 595 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 596 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 597 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 598 NI_PFI_OUTPUT_CDO_UPDATE = 30 599 }; 600 #define NI_PFI_OUTPUT_RTSI(x) (NI_PFI_OUTPUT_RTSI0 + (x)) 601 enum ni_660x_pfi_routing { 602 NI_660X_PFI_OUTPUT_COUNTER = 1, 603 NI_660X_PFI_OUTPUT_DIO = 2, 604 }; 605 #define NI_EXT_PFI(x) (NI_USUAL_PFI_SELECT(x) - 1) 606 #define NI_EXT_RTSI(x) (NI_USUAL_RTSI_SELECT(x) - 1) 607 enum ni_m_series_cdio_scan_begin_src { 608 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 609 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 610 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 611 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 612 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 613 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 614 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 615 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 616 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 617 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 618 }; 619 #define NI_CDIO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) 620 #define NI_CDIO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) 621 #define NI_AO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) 622 #define NI_AO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) 623 enum ni_freq_out_clock_source_bits { 624 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, 625 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC 626 }; 627 enum amplc_dio_clock_source { 628 AMPLC_DIO_CLK_CLKN, 629 AMPLC_DIO_CLK_10MHZ, 630 AMPLC_DIO_CLK_1MHZ, 631 AMPLC_DIO_CLK_100KHZ, 632 AMPLC_DIO_CLK_10KHZ, 633 AMPLC_DIO_CLK_1KHZ, 634 AMPLC_DIO_CLK_OUTNM1, 635 AMPLC_DIO_CLK_EXT, 636 AMPLC_DIO_CLK_VCC, 637 AMPLC_DIO_CLK_GND, 638 AMPLC_DIO_CLK_PAT_PRESENT, 639 AMPLC_DIO_CLK_20MHZ 640 }; 641 enum amplc_dio_ts_clock_src { 642 AMPLC_DIO_TS_CLK_1GHZ, 643 AMPLC_DIO_TS_CLK_1MHZ, 644 AMPLC_DIO_TS_CLK_1KHZ 645 }; 646 enum amplc_dio_gate_source { 647 AMPLC_DIO_GAT_VCC, 648 AMPLC_DIO_GAT_GND, 649 AMPLC_DIO_GAT_GATN, 650 AMPLC_DIO_GAT_NOUTNM2, 651 AMPLC_DIO_GAT_RESERVED4, 652 AMPLC_DIO_GAT_RESERVED5, 653 AMPLC_DIO_GAT_RESERVED6, 654 AMPLC_DIO_GAT_RESERVED7, 655 AMPLC_DIO_GAT_NGATN = 6, 656 AMPLC_DIO_GAT_OUTNM2, 657 AMPLC_DIO_GAT_PAT_PRESENT, 658 AMPLC_DIO_GAT_PAT_OCCURRED, 659 AMPLC_DIO_GAT_PAT_GONE, 660 AMPLC_DIO_GAT_NPAT_PRESENT, 661 AMPLC_DIO_GAT_NPAT_OCCURRED, 662 AMPLC_DIO_GAT_NPAT_GONE 663 }; 664 enum ke_counter_clock_source { 665 KE_CLK_20MHZ, 666 KE_CLK_4MHZ, 667 KE_CLK_EXT 668 }; 669 #endif 670