1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _USR_IDXD_H_ 20 #define _USR_IDXD_H_ 21 #include <stdint.h> 22 enum idxd_scmd_stat { 23 IDXD_SCMD_DEV_ENABLED = 0x80000010, 24 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 25 IDXD_SCMD_WQ_ENABLED = 0x80000021, 26 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 27 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 28 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 29 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 30 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 31 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 32 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 33 IDXD_SCMD_PERCPU_ERR = 0x80090000, 34 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 35 IDXD_SCMD_CDEV_ERR = 0x800b0000, 36 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 37 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 38 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 39 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 40 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 41 }; 42 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 43 #define IDXD_SCMD_SOFTERR_SHIFT 16 44 #define IDXD_OP_FLAG_FENCE 0x0001 45 #define IDXD_OP_FLAG_BOF 0x0002 46 #define IDXD_OP_FLAG_CRAV 0x0004 47 #define IDXD_OP_FLAG_RCR 0x0008 48 #define IDXD_OP_FLAG_RCI 0x0010 49 #define IDXD_OP_FLAG_CRSTS 0x0020 50 #define IDXD_OP_FLAG_CR 0x0080 51 #define IDXD_OP_FLAG_CC 0x0100 52 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 53 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 54 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 55 #define IDXD_OP_FLAG_CR_TCS 0x1000 56 #define IDXD_OP_FLAG_STORD 0x2000 57 #define IDXD_OP_FLAG_DRDBK 0x4000 58 #define IDXD_OP_FLAG_DSTS 0x8000 59 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 60 enum dsa_opcode { 61 DSA_OPCODE_NOOP = 0, 62 DSA_OPCODE_BATCH, 63 DSA_OPCODE_DRAIN, 64 DSA_OPCODE_MEMMOVE, 65 DSA_OPCODE_MEMFILL, 66 DSA_OPCODE_COMPARE, 67 DSA_OPCODE_COMPVAL, 68 DSA_OPCODE_CR_DELTA, 69 DSA_OPCODE_AP_DELTA, 70 DSA_OPCODE_DUALCAST, 71 DSA_OPCODE_CRCGEN = 0x10, 72 DSA_OPCODE_COPY_CRC, 73 DSA_OPCODE_DIF_CHECK, 74 DSA_OPCODE_DIF_INS, 75 DSA_OPCODE_DIF_STRP, 76 DSA_OPCODE_DIF_UPDT, 77 DSA_OPCODE_CFLUSH = 0x20, 78 }; 79 enum iax_opcode { 80 IAX_OPCODE_NOOP = 0, 81 IAX_OPCODE_DRAIN = 2, 82 IAX_OPCODE_MEMMOVE, 83 IAX_OPCODE_DECOMPRESS = 0x42, 84 IAX_OPCODE_COMPRESS, 85 }; 86 enum dsa_completion_status { 87 DSA_COMP_NONE = 0, 88 DSA_COMP_SUCCESS, 89 DSA_COMP_SUCCESS_PRED, 90 DSA_COMP_PAGE_FAULT_NOBOF, 91 DSA_COMP_PAGE_FAULT_IR, 92 DSA_COMP_BATCH_FAIL, 93 DSA_COMP_BATCH_PAGE_FAULT, 94 DSA_COMP_DR_OFFSET_NOINC, 95 DSA_COMP_DR_OFFSET_ERANGE, 96 DSA_COMP_DIF_ERR, 97 DSA_COMP_BAD_OPCODE = 0x10, 98 DSA_COMP_INVALID_FLAGS, 99 DSA_COMP_NOZERO_RESERVE, 100 DSA_COMP_XFER_ERANGE, 101 DSA_COMP_DESC_CNT_ERANGE, 102 DSA_COMP_DR_ERANGE, 103 DSA_COMP_OVERLAP_BUFFERS, 104 DSA_COMP_DCAST_ERR, 105 DSA_COMP_DESCLIST_ALIGN, 106 DSA_COMP_INT_HANDLE_INVAL, 107 DSA_COMP_CRA_XLAT, 108 DSA_COMP_CRA_ALIGN, 109 DSA_COMP_ADDR_ALIGN, 110 DSA_COMP_PRIV_BAD, 111 DSA_COMP_TRAFFIC_CLASS_CONF, 112 DSA_COMP_PFAULT_RDBA, 113 DSA_COMP_HW_ERR1, 114 DSA_COMP_HW_ERR_DRB, 115 DSA_COMP_TRANSLATION_FAIL, 116 }; 117 enum iax_completion_status { 118 IAX_COMP_NONE = 0, 119 IAX_COMP_SUCCESS, 120 IAX_COMP_PAGE_FAULT_IR = 0x04, 121 IAX_COMP_OUTBUF_OVERFLOW, 122 IAX_COMP_BAD_OPCODE = 0x10, 123 IAX_COMP_INVALID_FLAGS, 124 IAX_COMP_NOZERO_RESERVE, 125 IAX_COMP_INVALID_SIZE, 126 IAX_COMP_OVERLAP_BUFFERS = 0x16, 127 IAX_COMP_INT_HANDLE_INVAL = 0x19, 128 IAX_COMP_CRA_XLAT, 129 IAX_COMP_CRA_ALIGN, 130 IAX_COMP_ADDR_ALIGN, 131 IAX_COMP_PRIV_BAD, 132 IAX_COMP_TRAFFIC_CLASS_CONF, 133 IAX_COMP_PFAULT_RDBA, 134 IAX_COMP_HW_ERR1, 135 IAX_COMP_HW_ERR_DRB, 136 IAX_COMP_TRANSLATION_FAIL, 137 IAX_COMP_PRS_TIMEOUT, 138 IAX_COMP_WATCHDOG, 139 IAX_COMP_INVALID_COMP_FLAG = 0x30, 140 IAX_COMP_INVALID_FILTER_FLAG, 141 IAX_COMP_INVALID_NUM_ELEMS = 0x33, 142 }; 143 #define DSA_COMP_STATUS_MASK 0x7f 144 #define DSA_COMP_STATUS_WRITE 0x80 145 struct dsa_hw_desc { 146 uint32_t pasid : 20; 147 uint32_t rsvd : 11; 148 uint32_t priv : 1; 149 uint32_t flags : 24; 150 uint32_t opcode : 8; 151 uint64_t completion_addr; 152 union { 153 uint64_t src_addr; 154 uint64_t rdback_addr; 155 uint64_t pattern; 156 uint64_t desc_list_addr; 157 }; 158 union { 159 uint64_t dst_addr; 160 uint64_t rdback_addr2; 161 uint64_t src2_addr; 162 uint64_t comp_pattern; 163 }; 164 union { 165 uint32_t xfer_size; 166 uint32_t desc_count; 167 }; 168 uint16_t int_handle; 169 uint16_t rsvd1; 170 union { 171 uint8_t expected_res; 172 struct { 173 uint64_t delta_addr; 174 uint32_t max_delta_size; 175 uint32_t delt_rsvd; 176 uint8_t expected_res_mask; 177 }; 178 uint32_t delta_rec_size; 179 uint64_t dest2; 180 struct { 181 uint32_t crc_seed; 182 uint32_t crc_rsvd; 183 uint64_t seed_addr; 184 }; 185 struct { 186 uint8_t src_dif_flags; 187 uint8_t dif_chk_res; 188 uint8_t dif_chk_flags; 189 uint8_t dif_chk_res2[5]; 190 uint32_t chk_ref_tag_seed; 191 uint16_t chk_app_tag_mask; 192 uint16_t chk_app_tag_seed; 193 }; 194 struct { 195 uint8_t dif_ins_res; 196 uint8_t dest_dif_flag; 197 uint8_t dif_ins_flags; 198 uint8_t dif_ins_res2[13]; 199 uint32_t ins_ref_tag_seed; 200 uint16_t ins_app_tag_mask; 201 uint16_t ins_app_tag_seed; 202 }; 203 struct { 204 uint8_t src_upd_flags; 205 uint8_t upd_dest_flags; 206 uint8_t dif_upd_flags; 207 uint8_t dif_upd_res[5]; 208 uint32_t src_ref_tag_seed; 209 uint16_t src_app_tag_mask; 210 uint16_t src_app_tag_seed; 211 uint32_t dest_ref_tag_seed; 212 uint16_t dest_app_tag_mask; 213 uint16_t dest_app_tag_seed; 214 }; 215 uint8_t op_specific[24]; 216 }; 217 } __attribute__((packed)); 218 struct iax_hw_desc { 219 uint32_t pasid : 20; 220 uint32_t rsvd : 11; 221 uint32_t priv : 1; 222 uint32_t flags : 24; 223 uint32_t opcode : 8; 224 uint64_t completion_addr; 225 uint64_t src1_addr; 226 uint64_t dst_addr; 227 uint32_t src1_size; 228 uint16_t int_handle; 229 union { 230 uint16_t compr_flags; 231 uint16_t decompr_flags; 232 }; 233 uint64_t src2_addr; 234 uint32_t max_dst_size; 235 uint32_t src2_size; 236 uint32_t filter_flags; 237 uint32_t num_inputs; 238 } __attribute__((packed)); 239 struct dsa_raw_desc { 240 uint64_t field[8]; 241 } __attribute__((packed)); 242 struct dsa_completion_record { 243 volatile uint8_t status; 244 union { 245 uint8_t result; 246 uint8_t dif_status; 247 }; 248 uint16_t rsvd; 249 uint32_t bytes_completed; 250 uint64_t fault_addr; 251 union { 252 struct { 253 uint32_t invalid_flags : 24; 254 uint32_t rsvd2 : 8; 255 }; 256 uint32_t delta_rec_size; 257 uint32_t crc_val; 258 struct { 259 uint32_t dif_chk_ref_tag; 260 uint16_t dif_chk_app_tag_mask; 261 uint16_t dif_chk_app_tag; 262 }; 263 struct { 264 uint64_t dif_ins_res; 265 uint32_t dif_ins_ref_tag; 266 uint16_t dif_ins_app_tag_mask; 267 uint16_t dif_ins_app_tag; 268 }; 269 struct { 270 uint32_t dif_upd_src_ref_tag; 271 uint16_t dif_upd_src_app_tag_mask; 272 uint16_t dif_upd_src_app_tag; 273 uint32_t dif_upd_dest_ref_tag; 274 uint16_t dif_upd_dest_app_tag_mask; 275 uint16_t dif_upd_dest_app_tag; 276 }; 277 uint8_t op_specific[16]; 278 }; 279 } __attribute__((packed)); 280 struct dsa_raw_completion_record { 281 uint64_t field[4]; 282 } __attribute__((packed)); 283 struct iax_completion_record { 284 volatile uint8_t status; 285 uint8_t error_code; 286 uint16_t rsvd; 287 uint32_t bytes_completed; 288 uint64_t fault_addr; 289 uint32_t invalid_flags; 290 uint32_t rsvd2; 291 uint32_t output_size; 292 uint8_t output_bits; 293 uint8_t rsvd3; 294 uint16_t rsvd4; 295 uint64_t rsvd5[4]; 296 } __attribute__((packed)); 297 struct iax_raw_completion_record { 298 uint64_t field[8]; 299 } __attribute__((packed)); 300 #endif 301