1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_LINUX_PERF_EVENT_H 20 #define _UAPI_LINUX_PERF_EVENT_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #include <asm/byteorder.h> 24 enum perf_type_id { 25 PERF_TYPE_HARDWARE = 0, 26 PERF_TYPE_SOFTWARE = 1, 27 PERF_TYPE_TRACEPOINT = 2, 28 PERF_TYPE_HW_CACHE = 3, 29 PERF_TYPE_RAW = 4, 30 PERF_TYPE_BREAKPOINT = 5, 31 PERF_TYPE_MAX, 32 }; 33 #define PERF_PMU_TYPE_SHIFT 32 34 #define PERF_HW_EVENT_MASK 0xffffffff 35 enum perf_hw_id { 36 PERF_COUNT_HW_CPU_CYCLES = 0, 37 PERF_COUNT_HW_INSTRUCTIONS = 1, 38 PERF_COUNT_HW_CACHE_REFERENCES = 2, 39 PERF_COUNT_HW_CACHE_MISSES = 3, 40 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 41 PERF_COUNT_HW_BRANCH_MISSES = 5, 42 PERF_COUNT_HW_BUS_CYCLES = 6, 43 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 44 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 45 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 46 PERF_COUNT_HW_MAX, 47 }; 48 enum perf_hw_cache_id { 49 PERF_COUNT_HW_CACHE_L1D = 0, 50 PERF_COUNT_HW_CACHE_L1I = 1, 51 PERF_COUNT_HW_CACHE_LL = 2, 52 PERF_COUNT_HW_CACHE_DTLB = 3, 53 PERF_COUNT_HW_CACHE_ITLB = 4, 54 PERF_COUNT_HW_CACHE_BPU = 5, 55 PERF_COUNT_HW_CACHE_NODE = 6, 56 PERF_COUNT_HW_CACHE_MAX, 57 }; 58 enum perf_hw_cache_op_id { 59 PERF_COUNT_HW_CACHE_OP_READ = 0, 60 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 61 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 62 PERF_COUNT_HW_CACHE_OP_MAX, 63 }; 64 enum perf_hw_cache_op_result_id { 65 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 66 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 67 PERF_COUNT_HW_CACHE_RESULT_MAX, 68 }; 69 enum perf_sw_ids { 70 PERF_COUNT_SW_CPU_CLOCK = 0, 71 PERF_COUNT_SW_TASK_CLOCK = 1, 72 PERF_COUNT_SW_PAGE_FAULTS = 2, 73 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 74 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 75 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 76 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 77 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 78 PERF_COUNT_SW_EMULATION_FAULTS = 8, 79 PERF_COUNT_SW_DUMMY = 9, 80 PERF_COUNT_SW_BPF_OUTPUT = 10, 81 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 82 PERF_COUNT_SW_MAX, 83 }; 84 enum perf_event_sample_format { 85 PERF_SAMPLE_IP = 1U << 0, 86 PERF_SAMPLE_TID = 1U << 1, 87 PERF_SAMPLE_TIME = 1U << 2, 88 PERF_SAMPLE_ADDR = 1U << 3, 89 PERF_SAMPLE_READ = 1U << 4, 90 PERF_SAMPLE_CALLCHAIN = 1U << 5, 91 PERF_SAMPLE_ID = 1U << 6, 92 PERF_SAMPLE_CPU = 1U << 7, 93 PERF_SAMPLE_PERIOD = 1U << 8, 94 PERF_SAMPLE_STREAM_ID = 1U << 9, 95 PERF_SAMPLE_RAW = 1U << 10, 96 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 97 PERF_SAMPLE_REGS_USER = 1U << 12, 98 PERF_SAMPLE_STACK_USER = 1U << 13, 99 PERF_SAMPLE_WEIGHT = 1U << 14, 100 PERF_SAMPLE_DATA_SRC = 1U << 15, 101 PERF_SAMPLE_IDENTIFIER = 1U << 16, 102 PERF_SAMPLE_TRANSACTION = 1U << 17, 103 PERF_SAMPLE_REGS_INTR = 1U << 18, 104 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 105 PERF_SAMPLE_AUX = 1U << 20, 106 PERF_SAMPLE_CGROUP = 1U << 21, 107 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 108 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 109 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 110 PERF_SAMPLE_MAX = 1U << 25, 111 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, 112 }; 113 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 114 enum perf_branch_sample_type_shift { 115 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, 116 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, 117 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, 118 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, 119 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, 120 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, 121 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, 122 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, 123 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, 124 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, 125 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, 126 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, 127 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, 128 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, 129 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, 130 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, 131 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, 132 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, 133 PERF_SAMPLE_BRANCH_MAX_SHIFT 134 }; 135 enum perf_branch_sample_type { 136 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 137 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 138 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 139 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 140 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 141 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 142 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 143 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 144 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 145 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 146 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 147 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 148 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 149 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 150 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 151 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 152 PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 153 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 154 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 155 }; 156 enum { 157 PERF_BR_UNKNOWN = 0, 158 PERF_BR_COND = 1, 159 PERF_BR_UNCOND = 2, 160 PERF_BR_IND = 3, 161 PERF_BR_CALL = 4, 162 PERF_BR_IND_CALL = 5, 163 PERF_BR_RET = 6, 164 PERF_BR_SYSCALL = 7, 165 PERF_BR_SYSRET = 8, 166 PERF_BR_COND_CALL = 9, 167 PERF_BR_COND_RET = 10, 168 PERF_BR_MAX, 169 }; 170 #define PERF_SAMPLE_BRANCH_PLM_ALL (PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_HV) 171 enum perf_sample_regs_abi { 172 PERF_SAMPLE_REGS_ABI_NONE = 0, 173 PERF_SAMPLE_REGS_ABI_32 = 1, 174 PERF_SAMPLE_REGS_ABI_64 = 2, 175 }; 176 enum { 177 PERF_TXN_ELISION = (1 << 0), 178 PERF_TXN_TRANSACTION = (1 << 1), 179 PERF_TXN_SYNC = (1 << 2), 180 PERF_TXN_ASYNC = (1 << 3), 181 PERF_TXN_RETRY = (1 << 4), 182 PERF_TXN_CONFLICT = (1 << 5), 183 PERF_TXN_CAPACITY_WRITE = (1 << 6), 184 PERF_TXN_CAPACITY_READ = (1 << 7), 185 PERF_TXN_MAX = (1 << 8), 186 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 187 PERF_TXN_ABORT_SHIFT = 32, 188 }; 189 enum perf_event_read_format { 190 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 191 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 192 PERF_FORMAT_ID = 1U << 2, 193 PERF_FORMAT_GROUP = 1U << 3, 194 PERF_FORMAT_MAX = 1U << 4, 195 }; 196 #define PERF_ATTR_SIZE_VER0 64 197 #define PERF_ATTR_SIZE_VER1 72 198 #define PERF_ATTR_SIZE_VER2 80 199 #define PERF_ATTR_SIZE_VER3 96 200 #define PERF_ATTR_SIZE_VER4 104 201 #define PERF_ATTR_SIZE_VER5 112 202 #define PERF_ATTR_SIZE_VER6 120 203 #define PERF_ATTR_SIZE_VER7 128 204 struct perf_event_attr { 205 __u32 type; 206 __u32 size; 207 __u64 config; 208 union { 209 __u64 sample_period; 210 __u64 sample_freq; 211 }; 212 __u64 sample_type; 213 __u64 read_format; 214 __u64 disabled : 1, inherit : 1, pinned : 1, exclusive : 1, exclude_user : 1, exclude_kernel : 1, exclude_hv : 1, exclude_idle : 1, mmap : 1, comm : 1, freq : 1, inherit_stat : 1, enable_on_exec : 1, task : 1, watermark : 1, precise_ip : 2, mmap_data : 1, sample_id_all : 1, exclude_host : 1, exclude_guest : 1, exclude_callchain_kernel : 1, exclude_callchain_user : 1, mmap2 : 1, comm_exec : 1, use_clockid : 1, context_switch : 1, write_backward : 1, namespaces : 1, ksymbol : 1, bpf_event : 1, aux_output : 1, cgroup : 1, text_poke : 1, build_id : 1, inherit_thread : 1, remove_on_exec : 1, sigtrap : 1, __reserved_1 : 26; 215 union { 216 __u32 wakeup_events; 217 __u32 wakeup_watermark; 218 }; 219 __u32 bp_type; 220 union { 221 __u64 bp_addr; 222 __u64 kprobe_func; 223 __u64 uprobe_path; 224 __u64 config1; 225 }; 226 union { 227 __u64 bp_len; 228 __u64 kprobe_addr; 229 __u64 probe_offset; 230 __u64 config2; 231 }; 232 __u64 branch_sample_type; 233 __u64 sample_regs_user; 234 __u32 sample_stack_user; 235 __s32 clockid; 236 __u64 sample_regs_intr; 237 __u32 aux_watermark; 238 __u16 sample_max_stack; 239 __u16 __reserved_2; 240 __u32 aux_sample_size; 241 __u32 __reserved_3; 242 __u64 sig_data; 243 }; 244 struct perf_event_query_bpf { 245 __u32 ids_len; 246 __u32 prog_cnt; 247 __u32 ids[0]; 248 }; 249 #define PERF_EVENT_IOC_ENABLE _IO('$', 0) 250 #define PERF_EVENT_IOC_DISABLE _IO('$', 1) 251 #define PERF_EVENT_IOC_REFRESH _IO('$', 2) 252 #define PERF_EVENT_IOC_RESET _IO('$', 3) 253 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 254 #define PERF_EVENT_IOC_SET_OUTPUT _IO('$', 5) 255 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 256 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 257 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 258 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 259 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 260 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 261 enum perf_event_ioc_flags { 262 PERF_IOC_FLAG_GROUP = 1U << 0, 263 }; 264 struct perf_event_mmap_page { 265 __u32 version; 266 __u32 compat_version; 267 __u32 lock; 268 __u32 index; 269 __s64 offset; 270 __u64 time_enabled; 271 __u64 time_running; 272 union { 273 __u64 capabilities; 274 struct { 275 __u64 cap_bit0 : 1, cap_bit0_is_deprecated : 1, cap_user_rdpmc : 1, cap_user_time : 1, cap_user_time_zero : 1, cap_user_time_short : 1, cap_____res : 58; 276 }; 277 }; 278 __u16 pmc_width; 279 __u16 time_shift; 280 __u32 time_mult; 281 __u64 time_offset; 282 __u64 time_zero; 283 __u32 size; 284 __u32 __reserved_1; 285 __u64 time_cycles; 286 __u64 time_mask; 287 __u8 __reserved[116 * 8]; 288 __u64 data_head; 289 __u64 data_tail; 290 __u64 data_offset; 291 __u64 data_size; 292 __u64 aux_head; 293 __u64 aux_tail; 294 __u64 aux_offset; 295 __u64 aux_size; 296 }; 297 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 298 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 299 #define PERF_RECORD_MISC_KERNEL (1 << 0) 300 #define PERF_RECORD_MISC_USER (2 << 0) 301 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 302 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 303 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 304 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 305 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 306 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 307 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 308 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 309 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 310 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 311 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 312 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 313 struct perf_event_header { 314 __u32 type; 315 __u16 misc; 316 __u16 size; 317 }; 318 struct perf_ns_link_info { 319 __u64 dev; 320 __u64 ino; 321 }; 322 enum { 323 NET_NS_INDEX = 0, 324 UTS_NS_INDEX = 1, 325 IPC_NS_INDEX = 2, 326 PID_NS_INDEX = 3, 327 USER_NS_INDEX = 4, 328 MNT_NS_INDEX = 5, 329 CGROUP_NS_INDEX = 6, 330 NR_NAMESPACES, 331 }; 332 enum perf_event_type { 333 PERF_RECORD_MMAP = 1, 334 PERF_RECORD_LOST = 2, 335 PERF_RECORD_COMM = 3, 336 PERF_RECORD_EXIT = 4, 337 PERF_RECORD_THROTTLE = 5, 338 PERF_RECORD_UNTHROTTLE = 6, 339 PERF_RECORD_FORK = 7, 340 PERF_RECORD_READ = 8, 341 PERF_RECORD_SAMPLE = 9, 342 PERF_RECORD_MMAP2 = 10, 343 PERF_RECORD_AUX = 11, 344 PERF_RECORD_ITRACE_START = 12, 345 PERF_RECORD_LOST_SAMPLES = 13, 346 PERF_RECORD_SWITCH = 14, 347 PERF_RECORD_SWITCH_CPU_WIDE = 15, 348 PERF_RECORD_NAMESPACES = 16, 349 PERF_RECORD_KSYMBOL = 17, 350 PERF_RECORD_BPF_EVENT = 18, 351 PERF_RECORD_CGROUP = 19, 352 PERF_RECORD_TEXT_POKE = 20, 353 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 354 PERF_RECORD_MAX, 355 }; 356 enum perf_record_ksymbol_type { 357 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 358 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 359 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 360 PERF_RECORD_KSYMBOL_TYPE_MAX 361 }; 362 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 363 enum perf_bpf_event_type { 364 PERF_BPF_EVENT_UNKNOWN = 0, 365 PERF_BPF_EVENT_PROG_LOAD = 1, 366 PERF_BPF_EVENT_PROG_UNLOAD = 2, 367 PERF_BPF_EVENT_MAX, 368 }; 369 #define PERF_MAX_STACK_DEPTH 127 370 #define PERF_MAX_CONTEXTS_PER_STACK 8 371 enum perf_callchain_context { 372 PERF_CONTEXT_HV = (__u64) - 32, 373 PERF_CONTEXT_KERNEL = (__u64) - 128, 374 PERF_CONTEXT_USER = (__u64) - 512, 375 PERF_CONTEXT_GUEST = (__u64) - 2048, 376 PERF_CONTEXT_GUEST_KERNEL = (__u64) - 2176, 377 PERF_CONTEXT_GUEST_USER = (__u64) - 2560, 378 PERF_CONTEXT_MAX = (__u64) - 4095, 379 }; 380 #define PERF_AUX_FLAG_TRUNCATED 0x01 381 #define PERF_AUX_FLAG_OVERWRITE 0x02 382 #define PERF_AUX_FLAG_PARTIAL 0x04 383 #define PERF_AUX_FLAG_COLLISION 0x08 384 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 385 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 386 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 387 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 388 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 389 #define PERF_FLAG_PID_CGROUP (1UL << 2) 390 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) 391 #ifdef __LITTLE_ENDIAN_BITFIELD 392 union perf_mem_data_src { 393 __u64 val; 394 struct { 395 __u64 mem_op : 5, mem_lvl : 14, mem_snoop : 5, mem_lock : 2, mem_dtlb : 7, mem_lvl_num : 4, mem_remote : 1, mem_snoopx : 2, mem_blk : 3, mem_hops : 3, mem_rsvd : 18; 396 }; 397 }; 398 #elif defined(__BIG_ENDIAN_BITFIELD) 399 union perf_mem_data_src { 400 __u64 val; 401 struct { 402 __u64 mem_rsvd : 18, mem_hops : 3, mem_blk : 3, mem_snoopx : 2, mem_remote : 1, mem_lvl_num : 4, mem_dtlb : 7, mem_lock : 2, mem_snoop : 5, mem_lvl : 14, mem_op : 5; 403 }; 404 }; 405 #else 406 #error "Unknown endianness" 407 #endif 408 #define PERF_MEM_OP_NA 0x01 409 #define PERF_MEM_OP_LOAD 0x02 410 #define PERF_MEM_OP_STORE 0x04 411 #define PERF_MEM_OP_PFETCH 0x08 412 #define PERF_MEM_OP_EXEC 0x10 413 #define PERF_MEM_OP_SHIFT 0 414 #define PERF_MEM_LVL_NA 0x01 415 #define PERF_MEM_LVL_HIT 0x02 416 #define PERF_MEM_LVL_MISS 0x04 417 #define PERF_MEM_LVL_L1 0x08 418 #define PERF_MEM_LVL_LFB 0x10 419 #define PERF_MEM_LVL_L2 0x20 420 #define PERF_MEM_LVL_L3 0x40 421 #define PERF_MEM_LVL_LOC_RAM 0x80 422 #define PERF_MEM_LVL_REM_RAM1 0x100 423 #define PERF_MEM_LVL_REM_RAM2 0x200 424 #define PERF_MEM_LVL_REM_CCE1 0x400 425 #define PERF_MEM_LVL_REM_CCE2 0x800 426 #define PERF_MEM_LVL_IO 0x1000 427 #define PERF_MEM_LVL_UNC 0x2000 428 #define PERF_MEM_LVL_SHIFT 5 429 #define PERF_MEM_REMOTE_REMOTE 0x01 430 #define PERF_MEM_REMOTE_SHIFT 37 431 #define PERF_MEM_LVLNUM_L1 0x01 432 #define PERF_MEM_LVLNUM_L2 0x02 433 #define PERF_MEM_LVLNUM_L3 0x03 434 #define PERF_MEM_LVLNUM_L4 0x04 435 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b 436 #define PERF_MEM_LVLNUM_LFB 0x0c 437 #define PERF_MEM_LVLNUM_RAM 0x0d 438 #define PERF_MEM_LVLNUM_PMEM 0x0e 439 #define PERF_MEM_LVLNUM_NA 0x0f 440 #define PERF_MEM_LVLNUM_SHIFT 33 441 #define PERF_MEM_SNOOP_NA 0x01 442 #define PERF_MEM_SNOOP_NONE 0x02 443 #define PERF_MEM_SNOOP_HIT 0x04 444 #define PERF_MEM_SNOOP_MISS 0x08 445 #define PERF_MEM_SNOOP_HITM 0x10 446 #define PERF_MEM_SNOOP_SHIFT 19 447 #define PERF_MEM_SNOOPX_FWD 0x01 448 #define PERF_MEM_SNOOPX_SHIFT 38 449 #define PERF_MEM_LOCK_NA 0x01 450 #define PERF_MEM_LOCK_LOCKED 0x02 451 #define PERF_MEM_LOCK_SHIFT 24 452 #define PERF_MEM_TLB_NA 0x01 453 #define PERF_MEM_TLB_HIT 0x02 454 #define PERF_MEM_TLB_MISS 0x04 455 #define PERF_MEM_TLB_L1 0x08 456 #define PERF_MEM_TLB_L2 0x10 457 #define PERF_MEM_TLB_WK 0x20 458 #define PERF_MEM_TLB_OS 0x40 459 #define PERF_MEM_TLB_SHIFT 26 460 #define PERF_MEM_BLK_NA 0x01 461 #define PERF_MEM_BLK_DATA 0x02 462 #define PERF_MEM_BLK_ADDR 0x04 463 #define PERF_MEM_BLK_SHIFT 40 464 #define PERF_MEM_HOPS_0 0x01 465 #define PERF_MEM_HOPS_1 0x02 466 #define PERF_MEM_HOPS_2 0x03 467 #define PERF_MEM_HOPS_3 0x04 468 #define PERF_MEM_HOPS_SHIFT 43 469 #define PERF_MEM_S(a,s) (((__u64) PERF_MEM_ ##a ##_ ##s) << PERF_MEM_ ##a ##_SHIFT) 470 struct perf_branch_entry { 471 __u64 from; 472 __u64 to; 473 __u64 mispred : 1, predicted : 1, in_tx : 1, abort : 1, cycles : 16, type : 4, reserved : 40; 474 }; 475 union perf_sample_weight { 476 __u64 full; 477 #ifdef __LITTLE_ENDIAN_BITFIELD 478 struct { 479 __u32 var1_dw; 480 __u16 var2_w; 481 __u16 var3_w; 482 }; 483 #elif defined(__BIG_ENDIAN_BITFIELD) 484 struct { 485 __u16 var3_w; 486 __u16 var2_w; 487 __u32 var1_dw; 488 }; 489 #else 490 #error "Unknown endianness" 491 #endif 492 }; 493 #endif 494