1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef HABANALABS_H_ 20 #define HABANALABS_H_ 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 24 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 27 enum goya_queue_id { 28 GOYA_QUEUE_ID_DMA_0 = 0, 29 GOYA_QUEUE_ID_DMA_1 = 1, 30 GOYA_QUEUE_ID_DMA_2 = 2, 31 GOYA_QUEUE_ID_DMA_3 = 3, 32 GOYA_QUEUE_ID_DMA_4 = 4, 33 GOYA_QUEUE_ID_CPU_PQ = 5, 34 GOYA_QUEUE_ID_MME = 6, 35 GOYA_QUEUE_ID_TPC0 = 7, 36 GOYA_QUEUE_ID_TPC1 = 8, 37 GOYA_QUEUE_ID_TPC2 = 9, 38 GOYA_QUEUE_ID_TPC3 = 10, 39 GOYA_QUEUE_ID_TPC4 = 11, 40 GOYA_QUEUE_ID_TPC5 = 12, 41 GOYA_QUEUE_ID_TPC6 = 13, 42 GOYA_QUEUE_ID_TPC7 = 14, 43 GOYA_QUEUE_ID_SIZE 44 }; 45 enum gaudi_queue_id { 46 GAUDI_QUEUE_ID_DMA_0_0 = 0, 47 GAUDI_QUEUE_ID_DMA_0_1 = 1, 48 GAUDI_QUEUE_ID_DMA_0_2 = 2, 49 GAUDI_QUEUE_ID_DMA_0_3 = 3, 50 GAUDI_QUEUE_ID_DMA_1_0 = 4, 51 GAUDI_QUEUE_ID_DMA_1_1 = 5, 52 GAUDI_QUEUE_ID_DMA_1_2 = 6, 53 GAUDI_QUEUE_ID_DMA_1_3 = 7, 54 GAUDI_QUEUE_ID_CPU_PQ = 8, 55 GAUDI_QUEUE_ID_DMA_2_0 = 9, 56 GAUDI_QUEUE_ID_DMA_2_1 = 10, 57 GAUDI_QUEUE_ID_DMA_2_2 = 11, 58 GAUDI_QUEUE_ID_DMA_2_3 = 12, 59 GAUDI_QUEUE_ID_DMA_3_0 = 13, 60 GAUDI_QUEUE_ID_DMA_3_1 = 14, 61 GAUDI_QUEUE_ID_DMA_3_2 = 15, 62 GAUDI_QUEUE_ID_DMA_3_3 = 16, 63 GAUDI_QUEUE_ID_DMA_4_0 = 17, 64 GAUDI_QUEUE_ID_DMA_4_1 = 18, 65 GAUDI_QUEUE_ID_DMA_4_2 = 19, 66 GAUDI_QUEUE_ID_DMA_4_3 = 20, 67 GAUDI_QUEUE_ID_DMA_5_0 = 21, 68 GAUDI_QUEUE_ID_DMA_5_1 = 22, 69 GAUDI_QUEUE_ID_DMA_5_2 = 23, 70 GAUDI_QUEUE_ID_DMA_5_3 = 24, 71 GAUDI_QUEUE_ID_DMA_6_0 = 25, 72 GAUDI_QUEUE_ID_DMA_6_1 = 26, 73 GAUDI_QUEUE_ID_DMA_6_2 = 27, 74 GAUDI_QUEUE_ID_DMA_6_3 = 28, 75 GAUDI_QUEUE_ID_DMA_7_0 = 29, 76 GAUDI_QUEUE_ID_DMA_7_1 = 30, 77 GAUDI_QUEUE_ID_DMA_7_2 = 31, 78 GAUDI_QUEUE_ID_DMA_7_3 = 32, 79 GAUDI_QUEUE_ID_MME_0_0 = 33, 80 GAUDI_QUEUE_ID_MME_0_1 = 34, 81 GAUDI_QUEUE_ID_MME_0_2 = 35, 82 GAUDI_QUEUE_ID_MME_0_3 = 36, 83 GAUDI_QUEUE_ID_MME_1_0 = 37, 84 GAUDI_QUEUE_ID_MME_1_1 = 38, 85 GAUDI_QUEUE_ID_MME_1_2 = 39, 86 GAUDI_QUEUE_ID_MME_1_3 = 40, 87 GAUDI_QUEUE_ID_TPC_0_0 = 41, 88 GAUDI_QUEUE_ID_TPC_0_1 = 42, 89 GAUDI_QUEUE_ID_TPC_0_2 = 43, 90 GAUDI_QUEUE_ID_TPC_0_3 = 44, 91 GAUDI_QUEUE_ID_TPC_1_0 = 45, 92 GAUDI_QUEUE_ID_TPC_1_1 = 46, 93 GAUDI_QUEUE_ID_TPC_1_2 = 47, 94 GAUDI_QUEUE_ID_TPC_1_3 = 48, 95 GAUDI_QUEUE_ID_TPC_2_0 = 49, 96 GAUDI_QUEUE_ID_TPC_2_1 = 50, 97 GAUDI_QUEUE_ID_TPC_2_2 = 51, 98 GAUDI_QUEUE_ID_TPC_2_3 = 52, 99 GAUDI_QUEUE_ID_TPC_3_0 = 53, 100 GAUDI_QUEUE_ID_TPC_3_1 = 54, 101 GAUDI_QUEUE_ID_TPC_3_2 = 55, 102 GAUDI_QUEUE_ID_TPC_3_3 = 56, 103 GAUDI_QUEUE_ID_TPC_4_0 = 57, 104 GAUDI_QUEUE_ID_TPC_4_1 = 58, 105 GAUDI_QUEUE_ID_TPC_4_2 = 59, 106 GAUDI_QUEUE_ID_TPC_4_3 = 60, 107 GAUDI_QUEUE_ID_TPC_5_0 = 61, 108 GAUDI_QUEUE_ID_TPC_5_1 = 62, 109 GAUDI_QUEUE_ID_TPC_5_2 = 63, 110 GAUDI_QUEUE_ID_TPC_5_3 = 64, 111 GAUDI_QUEUE_ID_TPC_6_0 = 65, 112 GAUDI_QUEUE_ID_TPC_6_1 = 66, 113 GAUDI_QUEUE_ID_TPC_6_2 = 67, 114 GAUDI_QUEUE_ID_TPC_6_3 = 68, 115 GAUDI_QUEUE_ID_TPC_7_0 = 69, 116 GAUDI_QUEUE_ID_TPC_7_1 = 70, 117 GAUDI_QUEUE_ID_TPC_7_2 = 71, 118 GAUDI_QUEUE_ID_TPC_7_3 = 72, 119 GAUDI_QUEUE_ID_NIC_0_0 = 73, 120 GAUDI_QUEUE_ID_NIC_0_1 = 74, 121 GAUDI_QUEUE_ID_NIC_0_2 = 75, 122 GAUDI_QUEUE_ID_NIC_0_3 = 76, 123 GAUDI_QUEUE_ID_NIC_1_0 = 77, 124 GAUDI_QUEUE_ID_NIC_1_1 = 78, 125 GAUDI_QUEUE_ID_NIC_1_2 = 79, 126 GAUDI_QUEUE_ID_NIC_1_3 = 80, 127 GAUDI_QUEUE_ID_NIC_2_0 = 81, 128 GAUDI_QUEUE_ID_NIC_2_1 = 82, 129 GAUDI_QUEUE_ID_NIC_2_2 = 83, 130 GAUDI_QUEUE_ID_NIC_2_3 = 84, 131 GAUDI_QUEUE_ID_NIC_3_0 = 85, 132 GAUDI_QUEUE_ID_NIC_3_1 = 86, 133 GAUDI_QUEUE_ID_NIC_3_2 = 87, 134 GAUDI_QUEUE_ID_NIC_3_3 = 88, 135 GAUDI_QUEUE_ID_NIC_4_0 = 89, 136 GAUDI_QUEUE_ID_NIC_4_1 = 90, 137 GAUDI_QUEUE_ID_NIC_4_2 = 91, 138 GAUDI_QUEUE_ID_NIC_4_3 = 92, 139 GAUDI_QUEUE_ID_NIC_5_0 = 93, 140 GAUDI_QUEUE_ID_NIC_5_1 = 94, 141 GAUDI_QUEUE_ID_NIC_5_2 = 95, 142 GAUDI_QUEUE_ID_NIC_5_3 = 96, 143 GAUDI_QUEUE_ID_NIC_6_0 = 97, 144 GAUDI_QUEUE_ID_NIC_6_1 = 98, 145 GAUDI_QUEUE_ID_NIC_6_2 = 99, 146 GAUDI_QUEUE_ID_NIC_6_3 = 100, 147 GAUDI_QUEUE_ID_NIC_7_0 = 101, 148 GAUDI_QUEUE_ID_NIC_7_1 = 102, 149 GAUDI_QUEUE_ID_NIC_7_2 = 103, 150 GAUDI_QUEUE_ID_NIC_7_3 = 104, 151 GAUDI_QUEUE_ID_NIC_8_0 = 105, 152 GAUDI_QUEUE_ID_NIC_8_1 = 106, 153 GAUDI_QUEUE_ID_NIC_8_2 = 107, 154 GAUDI_QUEUE_ID_NIC_8_3 = 108, 155 GAUDI_QUEUE_ID_NIC_9_0 = 109, 156 GAUDI_QUEUE_ID_NIC_9_1 = 110, 157 GAUDI_QUEUE_ID_NIC_9_2 = 111, 158 GAUDI_QUEUE_ID_NIC_9_3 = 112, 159 GAUDI_QUEUE_ID_SIZE 160 }; 161 enum goya_engine_id { 162 GOYA_ENGINE_ID_DMA_0 = 0, 163 GOYA_ENGINE_ID_DMA_1, 164 GOYA_ENGINE_ID_DMA_2, 165 GOYA_ENGINE_ID_DMA_3, 166 GOYA_ENGINE_ID_DMA_4, 167 GOYA_ENGINE_ID_MME_0, 168 GOYA_ENGINE_ID_TPC_0, 169 GOYA_ENGINE_ID_TPC_1, 170 GOYA_ENGINE_ID_TPC_2, 171 GOYA_ENGINE_ID_TPC_3, 172 GOYA_ENGINE_ID_TPC_4, 173 GOYA_ENGINE_ID_TPC_5, 174 GOYA_ENGINE_ID_TPC_6, 175 GOYA_ENGINE_ID_TPC_7, 176 GOYA_ENGINE_ID_SIZE 177 }; 178 enum gaudi_engine_id { 179 GAUDI_ENGINE_ID_DMA_0 = 0, 180 GAUDI_ENGINE_ID_DMA_1, 181 GAUDI_ENGINE_ID_DMA_2, 182 GAUDI_ENGINE_ID_DMA_3, 183 GAUDI_ENGINE_ID_DMA_4, 184 GAUDI_ENGINE_ID_DMA_5, 185 GAUDI_ENGINE_ID_DMA_6, 186 GAUDI_ENGINE_ID_DMA_7, 187 GAUDI_ENGINE_ID_MME_0, 188 GAUDI_ENGINE_ID_MME_1, 189 GAUDI_ENGINE_ID_MME_2, 190 GAUDI_ENGINE_ID_MME_3, 191 GAUDI_ENGINE_ID_TPC_0, 192 GAUDI_ENGINE_ID_TPC_1, 193 GAUDI_ENGINE_ID_TPC_2, 194 GAUDI_ENGINE_ID_TPC_3, 195 GAUDI_ENGINE_ID_TPC_4, 196 GAUDI_ENGINE_ID_TPC_5, 197 GAUDI_ENGINE_ID_TPC_6, 198 GAUDI_ENGINE_ID_TPC_7, 199 GAUDI_ENGINE_ID_NIC_0, 200 GAUDI_ENGINE_ID_NIC_1, 201 GAUDI_ENGINE_ID_NIC_2, 202 GAUDI_ENGINE_ID_NIC_3, 203 GAUDI_ENGINE_ID_NIC_4, 204 GAUDI_ENGINE_ID_NIC_5, 205 GAUDI_ENGINE_ID_NIC_6, 206 GAUDI_ENGINE_ID_NIC_7, 207 GAUDI_ENGINE_ID_NIC_8, 208 GAUDI_ENGINE_ID_NIC_9, 209 GAUDI_ENGINE_ID_SIZE 210 }; 211 enum hl_goya_pll_index { 212 HL_GOYA_CPU_PLL = 0, 213 HL_GOYA_IC_PLL, 214 HL_GOYA_MC_PLL, 215 HL_GOYA_MME_PLL, 216 HL_GOYA_PCI_PLL, 217 HL_GOYA_EMMC_PLL, 218 HL_GOYA_TPC_PLL, 219 HL_GOYA_PLL_MAX 220 }; 221 enum hl_gaudi_pll_index { 222 HL_GAUDI_CPU_PLL = 0, 223 HL_GAUDI_PCI_PLL, 224 HL_GAUDI_SRAM_PLL, 225 HL_GAUDI_HBM_PLL, 226 HL_GAUDI_NIC_PLL, 227 HL_GAUDI_DMA_PLL, 228 HL_GAUDI_MESH_PLL, 229 HL_GAUDI_MME_PLL, 230 HL_GAUDI_TPC_PLL, 231 HL_GAUDI_IF_PLL, 232 HL_GAUDI_PLL_MAX 233 }; 234 enum hl_device_status { 235 HL_DEVICE_STATUS_OPERATIONAL, 236 HL_DEVICE_STATUS_IN_RESET, 237 HL_DEVICE_STATUS_MALFUNCTION, 238 HL_DEVICE_STATUS_NEEDS_RESET, 239 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 240 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION 241 }; 242 enum hl_server_type { 243 HL_SERVER_TYPE_UNKNOWN = 0, 244 HL_SERVER_GAUDI_HLS1 = 1, 245 HL_SERVER_GAUDI_HLS1H = 2, 246 HL_SERVER_GAUDI_TYPE1 = 3, 247 HL_SERVER_GAUDI_TYPE2 = 4 248 }; 249 #define HL_INFO_HW_IP_INFO 0 250 #define HL_INFO_HW_EVENTS 1 251 #define HL_INFO_DRAM_USAGE 2 252 #define HL_INFO_HW_IDLE 3 253 #define HL_INFO_DEVICE_STATUS 4 254 #define HL_INFO_DEVICE_UTILIZATION 6 255 #define HL_INFO_HW_EVENTS_AGGREGATE 7 256 #define HL_INFO_CLK_RATE 8 257 #define HL_INFO_RESET_COUNT 9 258 #define HL_INFO_TIME_SYNC 10 259 #define HL_INFO_CS_COUNTERS 11 260 #define HL_INFO_PCI_COUNTERS 12 261 #define HL_INFO_CLK_THROTTLE_REASON 13 262 #define HL_INFO_SYNC_MANAGER 14 263 #define HL_INFO_TOTAL_ENERGY 15 264 #define HL_INFO_PLL_FREQUENCY 16 265 #define HL_INFO_POWER 17 266 #define HL_INFO_OPEN_STATS 18 267 #define HL_INFO_DRAM_REPLACED_ROWS 21 268 #define HL_INFO_DRAM_PENDING_ROWS 22 269 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 270 #define HL_INFO_CS_TIMEOUT_EVENT 24 271 #define HL_INFO_RAZWI_EVENT 25 272 #define HL_INFO_VERSION_MAX_LEN 128 273 #define HL_INFO_CARD_NAME_MAX_LEN 16 274 struct hl_info_hw_ip_info { 275 __u64 sram_base_address; 276 __u64 dram_base_address; 277 __u64 dram_size; 278 __u32 sram_size; 279 __u32 num_of_events; 280 __u32 device_id; 281 __u32 module_id; 282 __u32 reserved; 283 __u16 first_available_interrupt_id; 284 __u16 server_type; 285 __u32 cpld_version; 286 __u32 psoc_pci_pll_nr; 287 __u32 psoc_pci_pll_nf; 288 __u32 psoc_pci_pll_od; 289 __u32 psoc_pci_pll_div_factor; 290 __u8 tpc_enabled_mask; 291 __u8 dram_enabled; 292 __u8 pad[2]; 293 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 294 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 295 __u64 reserved2; 296 __u64 dram_page_size; 297 }; 298 struct hl_info_dram_usage { 299 __u64 dram_free_mem; 300 __u64 ctx_dram_mem; 301 }; 302 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 303 struct hl_info_hw_idle { 304 __u32 is_idle; 305 __u32 busy_engines_mask; 306 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 307 }; 308 struct hl_info_device_status { 309 __u32 status; 310 __u32 pad; 311 }; 312 struct hl_info_device_utilization { 313 __u32 utilization; 314 __u32 pad; 315 }; 316 struct hl_info_clk_rate { 317 __u32 cur_clk_rate_mhz; 318 __u32 max_clk_rate_mhz; 319 }; 320 struct hl_info_reset_count { 321 __u32 hard_reset_cnt; 322 __u32 soft_reset_cnt; 323 }; 324 struct hl_info_time_sync { 325 __u64 device_time; 326 __u64 host_time; 327 }; 328 struct hl_info_pci_counters { 329 __u64 rx_throughput; 330 __u64 tx_throughput; 331 __u64 replay_cnt; 332 }; 333 enum hl_clk_throttling_type { 334 HL_CLK_THROTTLE_TYPE_POWER, 335 HL_CLK_THROTTLE_TYPE_THERMAL, 336 HL_CLK_THROTTLE_TYPE_MAX 337 }; 338 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 339 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 340 struct hl_info_clk_throttle { 341 __u32 clk_throttling_reason; 342 __u32 pad; 343 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 344 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 345 }; 346 struct hl_info_energy { 347 __u64 total_energy_consumption; 348 }; 349 #define HL_PLL_NUM_OUTPUTS 4 350 struct hl_pll_frequency_info { 351 __u16 output[HL_PLL_NUM_OUTPUTS]; 352 }; 353 struct hl_open_stats_info { 354 __u64 open_counter; 355 __u64 last_open_period_ms; 356 }; 357 struct hl_power_info { 358 __u64 power; 359 }; 360 struct hl_info_sync_manager { 361 __u32 first_available_sync_object; 362 __u32 first_available_monitor; 363 __u32 first_available_cq; 364 __u32 reserved; 365 }; 366 struct hl_info_cs_counters { 367 __u64 total_out_of_mem_drop_cnt; 368 __u64 ctx_out_of_mem_drop_cnt; 369 __u64 total_parsing_drop_cnt; 370 __u64 ctx_parsing_drop_cnt; 371 __u64 total_queue_full_drop_cnt; 372 __u64 ctx_queue_full_drop_cnt; 373 __u64 total_device_in_reset_drop_cnt; 374 __u64 ctx_device_in_reset_drop_cnt; 375 __u64 total_max_cs_in_flight_drop_cnt; 376 __u64 ctx_max_cs_in_flight_drop_cnt; 377 __u64 total_validation_drop_cnt; 378 __u64 ctx_validation_drop_cnt; 379 }; 380 struct hl_info_last_err_open_dev_time { 381 __s64 timestamp; 382 }; 383 struct hl_info_cs_timeout_event { 384 __s64 timestamp; 385 __u64 seq; 386 }; 387 #define HL_RAZWI_PAGE_FAULT 0 388 #define HL_RAZWI_MMU_ACCESS_ERROR 1 389 struct hl_info_razwi_event { 390 __s64 timestamp; 391 __u64 addr; 392 __u16 engine_id_1; 393 __u16 engine_id_2; 394 __u8 no_engine_id; 395 __u8 error_type; 396 __u8 pad[2]; 397 }; 398 enum gaudi_dcores { 399 HL_GAUDI_WS_DCORE, 400 HL_GAUDI_WN_DCORE, 401 HL_GAUDI_EN_DCORE, 402 HL_GAUDI_ES_DCORE 403 }; 404 struct hl_info_args { 405 __u64 return_pointer; 406 __u32 return_size; 407 __u32 op; 408 union { 409 __u32 dcore_id; 410 __u32 ctx_id; 411 __u32 period_ms; 412 __u32 pll_index; 413 }; 414 __u32 pad; 415 }; 416 #define HL_CB_OP_CREATE 0 417 #define HL_CB_OP_DESTROY 1 418 #define HL_CB_OP_INFO 2 419 #define HL_MAX_CB_SIZE (0x200000 - 32) 420 #define HL_CB_FLAGS_MAP 0x1 421 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2 422 struct hl_cb_in { 423 __u64 cb_handle; 424 __u32 op; 425 __u32 cb_size; 426 __u32 ctx_id; 427 __u32 flags; 428 }; 429 struct hl_cb_out { 430 union { 431 __u64 cb_handle; 432 union { 433 struct { 434 __u32 usage_cnt; 435 __u32 pad; 436 }; 437 __u64 device_va; 438 }; 439 }; 440 }; 441 union hl_cb_args { 442 struct hl_cb_in in; 443 struct hl_cb_out out; 444 }; 445 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 446 struct hl_cs_chunk { 447 union { 448 __u64 cb_handle; 449 __u64 signal_seq_arr; 450 __u64 encaps_signal_seq; 451 }; 452 __u32 queue_index; 453 union { 454 __u32 cb_size; 455 __u32 num_signal_seq_arr; 456 __u32 encaps_signal_offset; 457 }; 458 __u32 cs_chunk_flags; 459 __u32 collective_engine_id; 460 __u32 pad[10]; 461 }; 462 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 463 #define HL_CS_FLAGS_SIGNAL 0x2 464 #define HL_CS_FLAGS_WAIT 0x4 465 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 466 #define HL_CS_FLAGS_TIMESTAMP 0x20 467 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 468 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 469 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 470 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 471 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 472 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 473 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 474 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 475 #define HL_CS_STATUS_SUCCESS 0 476 #define HL_MAX_JOBS_PER_CS 512 477 struct hl_cs_in { 478 __u64 chunks_restore; 479 __u64 chunks_execute; 480 union { 481 __u64 seq; 482 __u32 encaps_sig_handle_id; 483 struct { 484 __u32 encaps_signals_count; 485 __u32 encaps_signals_q_idx; 486 }; 487 }; 488 __u32 num_chunks_restore; 489 __u32 num_chunks_execute; 490 __u32 timeout; 491 __u32 cs_flags; 492 __u32 ctx_id; 493 }; 494 struct hl_cs_out { 495 union { 496 __u64 seq; 497 struct { 498 __u32 handle_id; 499 __u32 count; 500 }; 501 }; 502 __u32 status; 503 __u32 sob_base_addr_offset; 504 __u16 sob_count_before_submission; 505 __u16 pad[3]; 506 }; 507 union hl_cs_args { 508 struct hl_cs_in in; 509 struct hl_cs_out out; 510 }; 511 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 512 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 513 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 514 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 515 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 516 struct hl_wait_cs_in { 517 union { 518 struct { 519 __u64 seq; 520 __u64 timeout_us; 521 }; 522 struct { 523 union { 524 __u64 addr; 525 __u64 cq_counters_handle; 526 }; 527 __u64 target; 528 }; 529 }; 530 __u32 ctx_id; 531 __u32 flags; 532 union { 533 struct { 534 __u8 seq_arr_len; 535 __u8 pad[7]; 536 }; 537 __u64 interrupt_timeout_us; 538 }; 539 __u64 cq_counters_offset; 540 }; 541 #define HL_WAIT_CS_STATUS_COMPLETED 0 542 #define HL_WAIT_CS_STATUS_BUSY 1 543 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 544 #define HL_WAIT_CS_STATUS_ABORTED 3 545 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 546 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 547 struct hl_wait_cs_out { 548 __u32 status; 549 __u32 flags; 550 __s64 timestamp_nsec; 551 __u32 cs_completion_map; 552 __u32 pad; 553 }; 554 union hl_wait_cs_args { 555 struct hl_wait_cs_in in; 556 struct hl_wait_cs_out out; 557 }; 558 #define HL_MEM_OP_ALLOC 0 559 #define HL_MEM_OP_FREE 1 560 #define HL_MEM_OP_MAP 2 561 #define HL_MEM_OP_UNMAP 3 562 #define HL_MEM_OP_MAP_BLOCK 4 563 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 564 #define HL_MEM_CONTIGUOUS 0x1 565 #define HL_MEM_SHARED 0x2 566 #define HL_MEM_USERPTR 0x4 567 #define HL_MEM_FORCE_HINT 0x8 568 struct hl_mem_in { 569 union { 570 struct { 571 __u64 mem_size; 572 } alloc; 573 struct { 574 __u64 handle; 575 } free; 576 struct { 577 __u64 hint_addr; 578 __u64 handle; 579 } map_device; 580 struct { 581 __u64 host_virt_addr; 582 __u64 hint_addr; 583 __u64 mem_size; 584 } map_host; 585 struct { 586 __u64 block_addr; 587 } map_block; 588 struct { 589 __u64 device_virt_addr; 590 } unmap; 591 struct { 592 __u64 handle; 593 __u64 mem_size; 594 } export_dmabuf_fd; 595 }; 596 __u32 op; 597 __u32 flags; 598 __u32 ctx_id; 599 __u32 pad; 600 }; 601 struct hl_mem_out { 602 union { 603 __u64 device_virt_addr; 604 __u64 handle; 605 struct { 606 __u64 block_handle; 607 __u32 block_size; 608 __u32 pad; 609 }; 610 __s32 fd; 611 }; 612 }; 613 union hl_mem_args { 614 struct hl_mem_in in; 615 struct hl_mem_out out; 616 }; 617 #define HL_DEBUG_MAX_AUX_VALUES 10 618 struct hl_debug_params_etr { 619 __u64 buffer_address; 620 __u64 buffer_size; 621 __u32 sink_mode; 622 __u32 pad; 623 }; 624 struct hl_debug_params_etf { 625 __u64 buffer_address; 626 __u64 buffer_size; 627 __u32 sink_mode; 628 __u32 pad; 629 }; 630 struct hl_debug_params_stm { 631 __u64 he_mask; 632 __u64 sp_mask; 633 __u32 id; 634 __u32 frequency; 635 }; 636 struct hl_debug_params_bmon { 637 __u64 start_addr0; 638 __u64 addr_mask0; 639 __u64 start_addr1; 640 __u64 addr_mask1; 641 __u32 bw_win; 642 __u32 win_capture; 643 __u32 id; 644 __u32 pad; 645 }; 646 struct hl_debug_params_spmu { 647 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 648 __u32 event_types_num; 649 __u32 pad; 650 }; 651 #define HL_DEBUG_OP_ETR 0 652 #define HL_DEBUG_OP_ETF 1 653 #define HL_DEBUG_OP_STM 2 654 #define HL_DEBUG_OP_FUNNEL 3 655 #define HL_DEBUG_OP_BMON 4 656 #define HL_DEBUG_OP_SPMU 5 657 #define HL_DEBUG_OP_TIMESTAMP 6 658 #define HL_DEBUG_OP_SET_MODE 7 659 struct hl_debug_args { 660 __u64 input_ptr; 661 __u64 output_ptr; 662 __u32 input_size; 663 __u32 output_size; 664 __u32 op; 665 __u32 reg_idx; 666 __u32 enable; 667 __u32 ctx_id; 668 }; 669 #define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args) 670 #define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args) 671 #define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args) 672 #define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args) 673 #define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args) 674 #define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args) 675 #define HL_COMMAND_START 0x01 676 #define HL_COMMAND_END 0x07 677 #endif 678