1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef MLX5_USER_IOCTL_VERBS_H 20 #define MLX5_USER_IOCTL_VERBS_H 21 #include <linux/types.h> 22 enum mlx5_ib_uapi_flow_action_flags { 23 MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA = 1 << 0, 24 }; 25 enum mlx5_ib_uapi_flow_table_type { 26 MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX = 0x0, 27 MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1, 28 MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2, 29 MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3, 30 MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX = 0x4, 31 }; 32 enum mlx5_ib_uapi_flow_action_packet_reformat_type { 33 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 = 0x0, 34 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x1, 35 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x2, 36 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x3, 37 }; 38 struct mlx5_ib_uapi_devx_async_cmd_hdr { 39 __aligned_u64 wr_id; 40 __u8 out_data[]; 41 }; 42 enum mlx5_ib_uapi_dm_type { 43 MLX5_IB_UAPI_DM_TYPE_MEMIC, 44 MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM, 45 MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM, 46 }; 47 enum mlx5_ib_uapi_devx_create_event_channel_flags { 48 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0, 49 }; 50 struct mlx5_ib_uapi_devx_async_event_hdr { 51 __aligned_u64 cookie; 52 __u8 out_data[]; 53 }; 54 enum mlx5_ib_uapi_pp_alloc_flags { 55 MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0, 56 }; 57 enum mlx5_ib_uapi_uar_alloc_type { 58 MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF = 0x0, 59 MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1, 60 }; 61 enum mlx5_ib_uapi_query_port_flags { 62 MLX5_IB_UAPI_QUERY_PORT_VPORT = 1 << 0, 63 MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID = 1 << 1, 64 MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX = 1 << 2, 65 MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX = 1 << 3, 66 MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0 = 1 << 4, 67 MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID = 1 << 5, 68 }; 69 struct mlx5_ib_uapi_reg { 70 __u32 value; 71 __u32 mask; 72 }; 73 struct mlx5_ib_uapi_query_port { 74 __aligned_u64 flags; 75 __u16 vport; 76 __u16 vport_vhca_id; 77 __u16 esw_owner_vhca_id; 78 __u16 rsvd0; 79 __aligned_u64 vport_steering_icm_rx; 80 __aligned_u64 vport_steering_icm_tx; 81 struct mlx5_ib_uapi_reg reg_c0; 82 }; 83 #endif 84