1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define MSM_PIPE_NONE 0x00 26 #define MSM_PIPE_2D0 0x01 27 #define MSM_PIPE_2D1 0x02 28 #define MSM_PIPE_3D0 0x10 29 #define MSM_PIPE_ID_MASK 0xffff 30 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 31 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 32 struct drm_msm_timespec { 33 __s64 tv_sec; 34 __s64 tv_nsec; 35 }; 36 #define MSM_PARAM_GPU_ID 0x01 37 #define MSM_PARAM_GMEM_SIZE 0x02 38 #define MSM_PARAM_CHIP_ID 0x03 39 #define MSM_PARAM_MAX_FREQ 0x04 40 #define MSM_PARAM_TIMESTAMP 0x05 41 #define MSM_PARAM_GMEM_BASE 0x06 42 #define MSM_PARAM_PRIORITIES 0x07 43 #define MSM_PARAM_PP_PGTABLE 0x08 44 #define MSM_PARAM_FAULTS 0x09 45 #define MSM_PARAM_SUSPENDS 0x0a 46 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 47 struct drm_msm_param { 48 __u32 pipe; 49 __u32 param; 50 __u64 value; 51 }; 52 #define MSM_BO_SCANOUT 0x00000001 53 #define MSM_BO_GPU_READONLY 0x00000002 54 #define MSM_BO_CACHE_MASK 0x000f0000 55 #define MSM_BO_CACHED 0x00010000 56 #define MSM_BO_WC 0x00020000 57 #define MSM_BO_UNCACHED 0x00040000 58 #define MSM_BO_CACHED_COHERENT 0x080000 59 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHE_MASK) 60 struct drm_msm_gem_new { 61 __u64 size; 62 __u32 flags; 63 __u32 handle; 64 }; 65 #define MSM_INFO_GET_OFFSET 0x00 66 #define MSM_INFO_GET_IOVA 0x01 67 #define MSM_INFO_SET_NAME 0x02 68 #define MSM_INFO_GET_NAME 0x03 69 struct drm_msm_gem_info { 70 __u32 handle; 71 __u32 info; 72 __u64 value; 73 __u32 len; 74 __u32 pad; 75 }; 76 #define MSM_PREP_READ 0x01 77 #define MSM_PREP_WRITE 0x02 78 #define MSM_PREP_NOSYNC 0x04 79 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 80 struct drm_msm_gem_cpu_prep { 81 __u32 handle; 82 __u32 op; 83 struct drm_msm_timespec timeout; 84 }; 85 struct drm_msm_gem_cpu_fini { 86 __u32 handle; 87 }; 88 struct drm_msm_gem_submit_reloc { 89 __u32 submit_offset; 90 __u32 or; 91 __s32 shift; 92 __u32 reloc_idx; 93 __u64 reloc_offset; 94 }; 95 #define MSM_SUBMIT_CMD_BUF 0x0001 96 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 97 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 98 struct drm_msm_gem_submit_cmd { 99 __u32 type; 100 __u32 submit_idx; 101 __u32 submit_offset; 102 __u32 size; 103 __u32 pad; 104 __u32 nr_relocs; 105 __u64 relocs; 106 }; 107 #define MSM_SUBMIT_BO_READ 0x0001 108 #define MSM_SUBMIT_BO_WRITE 0x0002 109 #define MSM_SUBMIT_BO_DUMP 0x0004 110 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP) 111 struct drm_msm_gem_submit_bo { 112 __u32 flags; 113 __u32 handle; 114 __u64 presumed; 115 }; 116 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 117 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 118 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 119 #define MSM_SUBMIT_SUDO 0x10000000 120 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 121 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 122 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | 0) 123 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 124 #define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0) 125 struct drm_msm_gem_submit_syncobj { 126 __u32 handle; 127 __u32 flags; 128 __u64 point; 129 }; 130 struct drm_msm_gem_submit { 131 __u32 flags; 132 __u32 fence; 133 __u32 nr_bos; 134 __u32 nr_cmds; 135 __u64 bos; 136 __u64 cmds; 137 __s32 fence_fd; 138 __u32 queueid; 139 __u64 in_syncobjs; 140 __u64 out_syncobjs; 141 __u32 nr_in_syncobjs; 142 __u32 nr_out_syncobjs; 143 __u32 syncobj_stride; 144 __u32 pad; 145 }; 146 struct drm_msm_wait_fence { 147 __u32 fence; 148 __u32 pad; 149 struct drm_msm_timespec timeout; 150 __u32 queueid; 151 }; 152 #define MSM_MADV_WILLNEED 0 153 #define MSM_MADV_DONTNEED 1 154 #define __MSM_MADV_PURGED 2 155 struct drm_msm_gem_madvise { 156 __u32 handle; 157 __u32 madv; 158 __u32 retained; 159 }; 160 #define MSM_SUBMITQUEUE_FLAGS (0) 161 struct drm_msm_submitqueue { 162 __u32 flags; 163 __u32 prio; 164 __u32 id; 165 }; 166 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 167 struct drm_msm_submitqueue_query { 168 __u64 data; 169 __u32 id; 170 __u32 param; 171 __u32 len; 172 __u32 pad; 173 }; 174 #define DRM_MSM_GET_PARAM 0x00 175 #define DRM_MSM_GEM_NEW 0x02 176 #define DRM_MSM_GEM_INFO 0x03 177 #define DRM_MSM_GEM_CPU_PREP 0x04 178 #define DRM_MSM_GEM_CPU_FINI 0x05 179 #define DRM_MSM_GEM_SUBMIT 0x06 180 #define DRM_MSM_WAIT_FENCE 0x07 181 #define DRM_MSM_GEM_MADVISE 0x08 182 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 183 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 184 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 185 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 186 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 187 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 188 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 189 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 190 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 191 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 192 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 193 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 194 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 195 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 196 #ifdef __cplusplus 197 } 198 #endif 199 #endif 200