1# 2# Copyright (c) 2016-2021, ARM Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# BL2 image is stored in XIP memory, for now, this option is only supported 36# when BL2_AT_EL3 is 1. 37BL2_IN_XIP_MEM := 0 38 39# Do dcache invalidate upon BL2 entry at EL3 40BL2_INV_DCACHE := 1 41 42# Select the branch protection features to use. 43BRANCH_PROTECTION := 0 44 45# By default, consider that the platform may release several CPUs out of reset. 46# The platform Makefile is free to override this value. 47COLD_BOOT_SINGLE_CPU := 0 48 49# Flag to compile in coreboot support code. Exclude by default. The coreboot 50# Makefile system will set this when compiling TF as part of a coreboot image. 51COREBOOT := 0 52 53# For Chain of Trust 54CREATE_KEYS := 1 55 56# Build flag to include AArch32 registers in cpu context save and restore during 57# world switch. This flag must be set to 0 for AArch64-only platforms. 58CTX_INCLUDE_AARCH32_REGS := 1 59 60# Include FP registers in cpu context 61CTX_INCLUDE_FPREGS := 0 62 63# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 64# must be set to 1 if the platform wants to use this feature in the Secure 65# world. It is not needed to use it in the Non-secure world. 66CTX_INCLUDE_PAUTH_REGS := 0 67 68# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 69# This must be set to 1 if architecture implements Nested Virtualization 70# Extension and platform wants to use this feature in the Secure world 71CTX_INCLUDE_NEVE_REGS := 0 72 73# Debug build 74DEBUG := 0 75 76# By default disable authenticated decryption support. 77DECRYPTION_SUPPORT := none 78 79# Build platform 80DEFAULT_PLAT := fvp 81 82# Disable the generation of the binary image (ELF only). 83DISABLE_BIN_GENERATION := 0 84 85# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 86# compatibility. 87DISABLE_MTPMU := 0 88 89# Enable capability to disable authentication dynamically. Only meant for 90# development platforms. 91DYN_DISABLE_AUTH := 0 92 93# Build option to enable MPAM for lower ELs 94ENABLE_MPAM_FOR_LOWER_ELS := 0 95 96# Flag to Enable Position Independant support (PIE) 97ENABLE_PIE := 0 98 99# Flag to enable Performance Measurement Framework 100ENABLE_PMF := 0 101 102# Flag to enable PSCI STATs functionality 103ENABLE_PSCI_STAT := 0 104 105# Flag to enable runtime instrumentation using PMF 106ENABLE_RUNTIME_INSTRUMENTATION := 0 107 108# Flag to enable stack corruption protection 109ENABLE_STACK_PROTECTOR := 0 110 111# Flag to enable exception handling in EL3 112EL3_EXCEPTION_HANDLING := 0 113 114# Flag to enable Branch Target Identification. 115# Internal flag not meant for direct setting. 116# Use BRANCH_PROTECTION to enable BTI. 117ENABLE_BTI := 0 118 119# Flag to enable Pointer Authentication. 120# Internal flag not meant for direct setting. 121# Use BRANCH_PROTECTION to enable PAUTH. 122ENABLE_PAUTH := 0 123 124# By default BL31 encryption disabled 125ENCRYPT_BL31 := 0 126 127# By default BL32 encryption disabled 128ENCRYPT_BL32 := 0 129 130# Default dummy firmware encryption key 131ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 132 133# Default dummy nonce for firmware encryption 134ENC_NONCE := 1234567890abcdef12345678 135 136# Build flag to treat usage of deprecated platform and framework APIs as error. 137ERROR_DEPRECATED := 0 138 139# Fault injection support 140FAULT_INJECTION_SUPPORT := 0 141 142# Byte alignment that each component in FIP is aligned to 143FIP_ALIGN := 0 144 145# Default FIP file name 146FIP_NAME := fip.bin 147 148# Default FWU_FIP file name 149FWU_FIP_NAME := fwu_fip.bin 150 151# By default firmware encryption with SSK 152FW_ENC_STATUS := 0 153 154# For Chain of Trust 155GENERATE_COT := 0 156 157# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 158# default, they are for Secure EL1. 159GICV2_G0_FOR_EL3 := 0 160 161# Route External Aborts to EL3. Disabled by default; External Aborts are handled 162# by lower ELs. 163HANDLE_EA_EL3_FIRST := 0 164 165# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 166# The default value is sha256. 167HASH_ALG := sha256 168 169# Whether system coherency is managed in hardware, without explicit software 170# operations. 171HW_ASSISTED_COHERENCY := 0 172 173# Set the default algorithm for the generation of Trusted Board Boot keys 174KEY_ALG := rsa 175 176# Set the default key size in case KEY_ALG is rsa 177ifeq ($(KEY_ALG),rsa) 178KEY_SIZE := 2048 179endif 180 181# Option to build TF with Measured Boot support 182MEASURED_BOOT := 0 183 184# NS timer register save and restore 185NS_TIMER_SWITCH := 0 186 187# Include lib/libc in the final image 188OVERRIDE_LIBC := 0 189 190# Build PL011 UART driver in minimal generic UART mode 191PL011_GENERIC_UART := 0 192 193# By default, consider that the platform's reset address is not programmable. 194# The platform Makefile is free to override this value. 195PROGRAMMABLE_RESET_ADDRESS := 0 196 197# Flag used to choose the power state format: Extended State-ID or Original 198PSCI_EXTENDED_STATE_ID := 0 199 200# Enable RAS support 201RAS_EXTENSION := 0 202 203# By default, BL1 acts as the reset handler, not BL31 204RESET_TO_BL31 := 0 205 206# For Chain of Trust 207SAVE_KEYS := 0 208 209# Software Delegated Exception support 210SDEI_SUPPORT := 0 211 212# True Random Number firmware Interface 213TRNG_SUPPORT := 0 214 215# SMCCC PCI support 216SMC_PCI_SUPPORT := 0 217 218# Whether code and read-only data should be put on separate memory pages. The 219# platform Makefile is free to override this value. 220SEPARATE_CODE_AND_RODATA := 0 221 222# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 223# separate memory region, which may be discontiguous from the rest of BL31. 224SEPARATE_NOBITS_REGION := 0 225 226# If the BL31 image initialisation code is recalimed after use for the secondary 227# cores stack 228RECLAIM_INIT_CODE := 0 229 230# SPD choice 231SPD := none 232 233# Enable the Management Mode (MM)-based Secure Partition Manager implementation 234SPM_MM := 0 235 236# Use SPM at S-EL2 as a default config for SPMD 237SPMD_SPM_AT_SEL2 := 1 238 239# Flag to introduce an infinite loop in BL1 just before it exits into the next 240# image. This is meant to help debugging the post-BL2 phase. 241SPIN_ON_BL1_EXIT := 0 242 243# Flags to build TF with Trusted Boot support 244TRUSTED_BOARD_BOOT := 0 245 246# Build option to choose whether Trusted Firmware uses Coherent memory or not. 247USE_COHERENT_MEM := 1 248 249# Build option to add debugfs support 250USE_DEBUGFS := 0 251 252# Build option to fconf based io 253ARM_IO_IN_DTB := 0 254 255# Build option to support SDEI through fconf 256SDEI_IN_FCONF := 0 257 258# Build option to support Secure Interrupt descriptors through fconf 259SEC_INT_DESC_IN_FCONF := 0 260 261# Build option to choose whether Trusted Firmware uses library at ROM 262USE_ROMLIB := 0 263 264# Build option to choose whether the xlat tables of BL images can be read-only. 265# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 266# which is the per BL-image option that actually enables the read-only tables 267# API. The reason for having this additional option is to have a common high 268# level makefile where we can check for incompatible features/build options. 269ALLOW_RO_XLAT_TABLES := 0 270 271# Chain of trust. 272COT := tbbr 273 274# Use tbbr_oid.h instead of platform_oid.h 275USE_TBBR_DEFS := 1 276 277# Build verbosity 278V := 0 279 280# Whether to enable D-Cache early during warm boot. This is usually 281# applicable for platforms wherein interconnect programming is not 282# required to enable cache coherency after warm reset (eg: single cluster 283# platforms). 284WARMBOOT_ENABLE_DCACHE_EARLY := 0 285 286# Build option to enable/disable the Statistical Profiling Extensions 287ENABLE_SPE_FOR_LOWER_ELS := 1 288 289# SPE is only supported on AArch64 so disable it on AArch32. 290ifeq (${ARCH},aarch32) 291 override ENABLE_SPE_FOR_LOWER_ELS := 0 292endif 293 294# Include Memory Tagging Extension registers in cpu context. This must be set 295# to 1 if the platform wants to use this feature in the Secure world and MTE is 296# enabled at ELX. 297CTX_INCLUDE_MTE_REGS := 0 298 299ENABLE_AMU := 0 300AMU_RESTRICT_COUNTERS := 0 301 302# By default, enable Scalable Vector Extension if implemented only for Non-secure 303# lower ELs 304# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 305ifneq (${ARCH},aarch32) 306 ENABLE_SVE_FOR_NS := 1 307 ENABLE_SVE_FOR_SWD := 0 308else 309 override ENABLE_SVE_FOR_NS := 0 310 override ENABLE_SVE_FOR_SWD := 0 311endif 312 313SANITIZE_UB := off 314 315# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 316# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 317# Default: disabled 318USE_SPINLOCK_CAS := 0 319 320# Enable Link Time Optimization 321ENABLE_LTO := 0 322 323# Build flag to include EL2 registers in cpu context save and restore during 324# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 325# Default is 0. 326CTX_INCLUDE_EL2_REGS := 0 327 328# Enable Memory tag extension which is supported for architecture greater 329# than Armv8.5-A 330# By default it is set to "no" 331SUPPORT_STACK_MEMTAG := no 332 333# Select workaround for AT speculative behaviour. 334ERRATA_SPECULATIVE_AT := 0 335 336# Trap RAS error record access from lower EL 337RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 338 339# Build option to create cot descriptors using fconf 340COT_DESC_IN_DTB := 0 341 342# Build option to provide openssl directory path 343OPENSSL_DIR := /usr 344 345# Build option to use the SP804 timer instead of the generic one 346USE_SP804_TIMER := 0 347 348# Build option to define number of firmware banks, used in firmware update 349# metadata structure. 350NR_OF_FW_BANKS := 2 351 352# Build option to define number of images in firmware bank, used in firmware 353# update metadata structure. 354NR_OF_IMAGES_IN_FW_BANK := 1 355 356# Disable Firmware update support by default 357PSA_FWU_SUPPORT := 0 358