1# 2# Copyright (c) 2021, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/libfdt/libfdt.mk 8 9RESET_TO_BL31 := 1 10ifeq (${RESET_TO_BL31}, 0) 11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") 12endif 13 14ifeq (${ENABLE_PIE}, 1) 15override SEPARATE_CODE_AND_RODATA := 1 16endif 17 18CTX_INCLUDE_AARCH32_REGS := 0 19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 21endif 22 23ifeq (${TRUSTED_BOARD_BOOT}, 1) 24$(error "TRUSTED_BOARD_BOOT must be disabled") 25endif 26 27PRELOADED_BL33_BASE := 0x80080000 28 29FPGA_PRELOADED_DTB_BASE := 0x80070000 30$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) 31 32FPGA_PRELOADED_CMD_LINE := 0x1000 33$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) 34 35ENABLE_AMU := 1 36 37# Treating this as a memory-constrained port for now 38USE_COHERENT_MEM := 0 39 40# This can be overridden depending on CPU(s) used in the FPGA image 41HW_ASSISTED_COHERENCY := 1 42 43PL011_GENERIC_UART := 1 44 45SUPPORT_UNKNOWN_MPID ?= 1 46 47FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 48 49# select a different set of CPU files, depending on whether we compile for 50# hardware assisted coherency cores or not 51ifeq (${HW_ASSISTED_COHERENCY}, 0) 52# Cores used without DSU 53 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 54 lib/cpus/aarch64/cortex_a53.S \ 55 lib/cpus/aarch64/cortex_a57.S \ 56 lib/cpus/aarch64/cortex_a72.S \ 57 lib/cpus/aarch64/cortex_a73.S 58else 59# AArch64-only cores 60 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 61 lib/cpus/aarch64/cortex_a76ae.S \ 62 lib/cpus/aarch64/cortex_a77.S \ 63 lib/cpus/aarch64/cortex_a78.S \ 64 lib/cpus/aarch64/neoverse_n_common.S \ 65 lib/cpus/aarch64/neoverse_n1.S \ 66 lib/cpus/aarch64/neoverse_n2.S \ 67 lib/cpus/aarch64/neoverse_e1.S \ 68 lib/cpus/aarch64/neoverse_v1.S \ 69 lib/cpus/aarch64/cortex_a78_ae.S \ 70 lib/cpus/aarch64/cortex_a65.S \ 71 lib/cpus/aarch64/cortex_a65ae.S \ 72 lib/cpus/aarch64/cortex_a510.S \ 73 lib/cpus/aarch64/cortex_a710.S \ 74 lib/cpus/aarch64/cortex_makalu.S \ 75 lib/cpus/aarch64/cortex_makalu_elp_arm.S \ 76 lib/cpus/aarch64/cortex_a78c.S 77 78# AArch64/AArch32 cores 79 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 80 lib/cpus/aarch64/cortex_a75.S 81endif 82 83ifeq (${SUPPORT_UNKNOWN_MPID}, 1) 84# Add support for unknown/invalid MPIDs (aarch64 only) 85$(eval $(call add_define,SUPPORT_UNKNOWN_MPID)) 86 FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S 87endif 88 89# Allow detection of GIC-600 90GICV3_SUPPORT_GIC600 := 1 91 92# Include GICv3 driver files 93include drivers/arm/gic/v3/gicv3.mk 94 95FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ 96 plat/common/plat_gicv3.c \ 97 plat/arm/board/arm_fpga/fpga_gicv3.c 98 99FDT_SOURCES := fdts/arm_fpga.dts 100 101PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include 102 103PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S 104 105BL31_SOURCES += common/fdt_wrappers.c \ 106 common/fdt_fixup.c \ 107 drivers/delay_timer/delay_timer.c \ 108 drivers/delay_timer/generic_delay_timer.c \ 109 drivers/arm/pl011/${ARCH}/pl011_console.S \ 110 plat/common/plat_psci_common.c \ 111 plat/arm/board/arm_fpga/fpga_pm.c \ 112 plat/arm/board/arm_fpga/fpga_topology.c \ 113 plat/arm/board/arm_fpga/fpga_console.c \ 114 plat/arm/board/arm_fpga/fpga_bl31_setup.c \ 115 ${FPGA_CPU_LIBS} \ 116 ${FPGA_GIC_SOURCES} 117 118$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31)) 119$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31)) 120 121bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld 122 $(ECHO) " LD $@" 123 $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf 124 125all: bl31.axf 126