1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/desc_image_load.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <drivers/partition/partition.h>
18 #include <lib/fconf/fconf.h>
19 #include <lib/fconf/fconf_dyn_cfg_getter.h>
20 #ifdef SPD_opteed
21 #include <lib/optee_utils.h>
22 #endif
23 #include <lib/utils.h>
24 #include <plat/arm/common/plat_arm.h>
25 #include <plat/common/platform.h>
26
27 /* Data structure which holds the extents of the trusted SRAM for BL2 */
28 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
29
30 /* Base address of fw_config received from BL1 */
31 static uintptr_t config_base;
32
33 /*
34 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
35 * for `meminfo_t` data structure and fw_configs passed from BL1.
36 */
37 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
38
39 /* Weak definitions may be overridden in specific ARM standard platform */
40 #pragma weak bl2_early_platform_setup2
41 #pragma weak bl2_platform_setup
42 #pragma weak bl2_plat_arch_setup
43 #pragma weak bl2_plat_sec_mem_layout
44 #if MEASURED_BOOT
45 #pragma weak bl2_plat_get_hash
46 #endif
47
48 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \
49 bl2_tzram_layout.total_base, \
50 bl2_tzram_layout.total_size, \
51 MT_MEMORY | MT_RW | MT_SECURE)
52
53
54 #pragma weak arm_bl2_plat_handle_post_image_load
55
56 /*******************************************************************************
57 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
58 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
59 * Copy it to a safe location before its reclaimed by later BL2 functionality.
60 ******************************************************************************/
arm_bl2_early_platform_setup(uintptr_t fw_config,struct meminfo * mem_layout)61 void arm_bl2_early_platform_setup(uintptr_t fw_config,
62 struct meminfo *mem_layout)
63 {
64 /* Initialize the console to provide early debug support */
65 arm_console_boot_init();
66
67 /* Setup the BL2 memory layout */
68 bl2_tzram_layout = *mem_layout;
69
70 config_base = fw_config;
71
72 /* Initialise the IO layer and register platform IO devices */
73 plat_arm_io_setup();
74
75 /* Load partition table */
76 #if ARM_GPT_SUPPORT
77 partition_init(GPT_IMAGE_ID);
78 #endif /* ARM_GPT_SUPPORT */
79
80 }
81
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)82 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
83 {
84 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
85
86 generic_delay_timer_init();
87 }
88
89 /*
90 * Perform BL2 preload setup. Currently we initialise the dynamic
91 * configuration here.
92 */
bl2_plat_preload_setup(void)93 void bl2_plat_preload_setup(void)
94 {
95 arm_bl2_dyn_cfg_init();
96
97 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
98 /* Always use the FIP from bank 0 */
99 arm_set_fip_addr(0U);
100 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
101 }
102
103 /*
104 * Perform ARM standard platform setup.
105 */
arm_bl2_platform_setup(void)106 void arm_bl2_platform_setup(void)
107 {
108 /* Initialize the secure environment */
109 plat_arm_security_setup();
110
111 #if defined(PLAT_ARM_MEM_PROT_ADDR)
112 arm_nor_psci_do_static_mem_protect();
113 #endif
114 }
115
bl2_platform_setup(void)116 void bl2_platform_setup(void)
117 {
118 arm_bl2_platform_setup();
119 }
120
121 /*******************************************************************************
122 * Perform the very early platform specific architectural setup here. At the
123 * moment this is only initializes the mmu in a quick and dirty way.
124 ******************************************************************************/
arm_bl2_plat_arch_setup(void)125 void arm_bl2_plat_arch_setup(void)
126 {
127 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
128 /*
129 * Ensure ARM platforms don't use coherent memory in BL2 unless
130 * cryptocell integration is enabled.
131 */
132 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
133 #endif
134
135 const mmap_region_t bl_regions[] = {
136 MAP_BL2_TOTAL,
137 ARM_MAP_BL_RO,
138 #if USE_ROMLIB
139 ARM_MAP_ROMLIB_CODE,
140 ARM_MAP_ROMLIB_DATA,
141 #endif
142 #if ARM_CRYPTOCELL_INTEG
143 ARM_MAP_BL_COHERENT_RAM,
144 #endif
145 ARM_MAP_BL_CONFIG_REGION,
146 {0}
147 };
148
149 setup_page_tables(bl_regions, plat_arm_get_mmap());
150
151 #ifdef __aarch64__
152 enable_mmu_el1(0);
153 #else
154 enable_mmu_svc_mon(0);
155 #endif
156
157 arm_setup_romlib();
158 }
159
bl2_plat_arch_setup(void)160 void bl2_plat_arch_setup(void)
161 {
162 const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
163
164 arm_bl2_plat_arch_setup();
165
166 /* Fill the properties struct with the info from the config dtb */
167 fconf_populate("FW_CONFIG", config_base);
168
169 /* TB_FW_CONFIG was also loaded by BL1 */
170 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
171 assert(tb_fw_config_info != NULL);
172
173 fconf_populate("TB_FW", tb_fw_config_info->config_addr);
174 }
175
arm_bl2_handle_post_image_load(unsigned int image_id)176 int arm_bl2_handle_post_image_load(unsigned int image_id)
177 {
178 int err = 0;
179 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
180 #ifdef SPD_opteed
181 bl_mem_params_node_t *pager_mem_params = NULL;
182 bl_mem_params_node_t *paged_mem_params = NULL;
183 #endif
184 assert(bl_mem_params != NULL);
185
186 switch (image_id) {
187 #ifdef __aarch64__
188 case BL32_IMAGE_ID:
189 #ifdef SPD_opteed
190 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
191 assert(pager_mem_params);
192
193 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
194 assert(paged_mem_params);
195
196 err = parse_optee_header(&bl_mem_params->ep_info,
197 &pager_mem_params->image_info,
198 &paged_mem_params->image_info);
199 if (err != 0) {
200 WARN("OPTEE header parse error.\n");
201 }
202 #endif
203 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
204 break;
205 #endif
206
207 case BL33_IMAGE_ID:
208 /* BL33 expects to receive the primary CPU MPID (through r0) */
209 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
210 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
211 break;
212
213 #ifdef SCP_BL2_BASE
214 case SCP_BL2_IMAGE_ID:
215 /* The subsequent handling of SCP_BL2 is platform specific */
216 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
217 if (err) {
218 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
219 }
220 break;
221 #endif
222 default:
223 /* Do nothing in default case */
224 break;
225 }
226
227 return err;
228 }
229
230 /*******************************************************************************
231 * This function can be used by the platforms to update/use image
232 * information for given `image_id`.
233 ******************************************************************************/
arm_bl2_plat_handle_post_image_load(unsigned int image_id)234 int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
235 {
236 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
237 /* For Secure Partitions we don't need post processing */
238 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
239 (image_id < MAX_NUMBER_IDS)) {
240 return 0;
241 }
242 #endif
243 return arm_bl2_handle_post_image_load(image_id);
244 }
245
bl2_plat_handle_post_image_load(unsigned int image_id)246 int bl2_plat_handle_post_image_load(unsigned int image_id)
247 {
248 return arm_bl2_plat_handle_post_image_load(image_id);
249 }
250
251 #if MEASURED_BOOT
252 /* Read TCG_DIGEST_SIZE bytes of BL2 hash data */
bl2_plat_get_hash(void * data)253 void bl2_plat_get_hash(void *data)
254 {
255 arm_bl2_get_hash(data);
256 }
257 #endif
258