1 /*
2 * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <string.h>
8
9 #include <libfdt.h>
10
11 #include <platform_def.h>
12
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <common/desc_image_load.h>
18 #include <common/image_decompress.h>
19 #include <drivers/console.h>
20 #include <drivers/io/io_driver.h>
21 #include <drivers/io/io_storage.h>
22 #include <lib/mmio.h>
23 #include <lib/xlat_tables/xlat_tables_defs.h>
24 #include <plat/common/platform.h>
25 #if RCAR_GEN3_BL33_GZIP == 1
26 #include <tf_gunzip.h>
27 #endif
28
29 #include "avs_driver.h"
30 #include "boot_init_dram.h"
31 #include "cpg_registers.h"
32 #include "board.h"
33 #include "emmc_def.h"
34 #include "emmc_hal.h"
35 #include "emmc_std.h"
36
37 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
38 #include "iic_dvfs.h"
39 #endif
40
41 #include "io_common.h"
42 #include "io_rcar.h"
43 #include "qos_init.h"
44 #include "rcar_def.h"
45 #include "rcar_private.h"
46 #include "rcar_version.h"
47 #include "rom_api.h"
48
49 #if RCAR_BL2_DCACHE == 1
50 /*
51 * Following symbols are only used during plat_arch_setup() only
52 * when RCAR_BL2_DCACHE is enabled.
53 */
54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
56
57 #if USE_COHERENT_MEM
58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
60 #endif
61
62 #endif
63
64 extern void plat_rcar_gic_driver_init(void);
65 extern void plat_rcar_gic_init(void);
66 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
67 extern void bl2_system_cpg_init(void);
68 extern void bl2_secure_setting(void);
69 extern void bl2_cpg_init(void);
70 extern void rcar_io_emmc_setup(void);
71 extern void rcar_io_setup(void);
72 extern void rcar_swdt_release(void);
73 extern void rcar_swdt_init(void);
74 extern void rcar_rpc_init(void);
75 extern void rcar_pfc_init(void);
76 extern void rcar_dma_init(void);
77
78 static void bl2_init_generic_timer(void);
79
80 /* R-Car Gen3 product check */
81 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
82 #define TARGET_PRODUCT PRR_PRODUCT_H3
83 #define TARGET_NAME "R-Car H3"
84 #elif RCAR_LSI == RCAR_M3
85 #define TARGET_PRODUCT PRR_PRODUCT_M3
86 #define TARGET_NAME "R-Car M3"
87 #elif RCAR_LSI == RCAR_M3N
88 #define TARGET_PRODUCT PRR_PRODUCT_M3N
89 #define TARGET_NAME "R-Car M3N"
90 #elif RCAR_LSI == RCAR_V3M
91 #define TARGET_PRODUCT PRR_PRODUCT_V3M
92 #define TARGET_NAME "R-Car V3M"
93 #elif RCAR_LSI == RCAR_E3
94 #define TARGET_PRODUCT PRR_PRODUCT_E3
95 #define TARGET_NAME "R-Car E3"
96 #elif RCAR_LSI == RCAR_D3
97 #define TARGET_PRODUCT PRR_PRODUCT_D3
98 #define TARGET_NAME "R-Car D3"
99 #elif RCAR_LSI == RCAR_AUTO
100 #define TARGET_NAME "R-Car H3/M3/M3N/V3M"
101 #endif
102
103 #if (RCAR_LSI == RCAR_E3)
104 #define GPIO_INDT (GPIO_INDT6)
105 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
106 #else
107 #define GPIO_INDT (GPIO_INDT1)
108 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
109 #endif
110
111 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
112 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
113 assert_bl31_params_do_not_fit_in_shared_memory);
114
115 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
116
117 /* FDT with DRAM configuration */
118 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
119 static void *fdt = (void *)fdt_blob;
120
unsigned_num_print(unsigned long long int unum,unsigned int radix,char * string)121 static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
122 char *string)
123 {
124 /* Just need enough space to store 64 bit decimal integer */
125 char num_buf[20];
126 int i = 0;
127 unsigned int rem;
128
129 do {
130 rem = unum % radix;
131 if (rem < 0xa)
132 num_buf[i] = '0' + rem;
133 else
134 num_buf[i] = 'a' + (rem - 0xa);
135 i++;
136 unum /= radix;
137 } while (unum > 0U);
138
139 while (--i >= 0)
140 *string++ = num_buf[i];
141 *string = 0;
142 }
143
144 #if (RCAR_LOSSY_ENABLE == 1)
145 typedef struct bl2_lossy_info {
146 uint32_t magic;
147 uint32_t a0;
148 uint32_t b0;
149 } bl2_lossy_info_t;
150
bl2_lossy_gen_fdt(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)151 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
152 uint64_t end_addr, uint32_t format,
153 uint32_t enable, int fcnlnode)
154 {
155 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
156 char nodename[40] = { 0 };
157 int ret, node;
158
159 /* Ignore undefined addresses */
160 if (start_addr == 0 && end_addr == 0)
161 return;
162
163 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
164 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
165
166 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
167 if (ret < 0) {
168 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
169 panic();
170 }
171
172 ret = fdt_setprop_string(fdt, node, "compatible",
173 "renesas,lossy-decompression");
174 if (ret < 0) {
175 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
176 panic();
177 }
178
179 ret = fdt_appendprop_string(fdt, node, "compatible",
180 "shared-dma-pool");
181 if (ret < 0) {
182 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
183 panic();
184 }
185
186 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
187 if (ret < 0) {
188 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
189 panic();
190 }
191
192 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
193 if (ret < 0) {
194 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
195 panic();
196 }
197
198 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
199 if (ret < 0) {
200 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
201 panic();
202 }
203
204 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
205 if (ret < 0) {
206 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
207 panic();
208 }
209 }
210
bl2_lossy_setting(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)211 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
212 uint64_t end_addr, uint32_t format,
213 uint32_t enable, int fcnlnode)
214 {
215 bl2_lossy_info_t info;
216 uint32_t reg;
217
218 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
219
220 reg = format | (start_addr >> 20);
221 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
222 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
224
225 info.magic = 0x12345678U;
226 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
227 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
228
229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
232
233 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
234 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
235 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
236 }
237 #endif
238
bl2_plat_flush_bl31_params(void)239 void bl2_plat_flush_bl31_params(void)
240 {
241 uint32_t product_cut, product, cut;
242 uint32_t boot_dev, boot_cpu;
243 uint32_t lcs, reg, val;
244
245 reg = mmio_read_32(RCAR_MODEMR);
246 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
247
248 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
249 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
250 emmc_terminate();
251
252 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
253 bl2_secure_setting();
254
255 reg = mmio_read_32(RCAR_PRR);
256 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
257 product = reg & PRR_PRODUCT_MASK;
258 cut = reg & PRR_CUT_MASK;
259
260 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
261 goto tlb;
262
263 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
264 goto tlb;
265
266 if (product == PRR_PRODUCT_D3)
267 goto tlb;
268
269 /* Disable MFIS write protection */
270 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
271
272 tlb:
273 reg = mmio_read_32(RCAR_MODEMR);
274 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
275 if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
276 boot_cpu != MODEMR_BOOT_CPU_CA53)
277 goto mmu;
278
279 if (product_cut == PRR_PRODUCT_H3_CUT20) {
280 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
281 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
282 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
283 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
284 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
285 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
286 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
287 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
288 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
289 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
290 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
291 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
292 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
293 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
294 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
295 }
296
297 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
298 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
299 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
300 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
301 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
302 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
303 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
304
305 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
306 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
307 }
308
309 mmu:
310 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
311 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
312
313 val = rcar_rom_get_lcs(&lcs);
314 if (val) {
315 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
316 panic();
317 }
318
319 if (lcs == LCS_SE)
320 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
321
322 rcar_swdt_release();
323 bl2_system_cpg_init();
324
325 #if RCAR_BL2_DCACHE == 1
326 /* Disable data cache (clean and invalidate) */
327 disable_mmu_el3();
328 #endif
329 }
330
is_ddr_backup_mode(void)331 static uint32_t is_ddr_backup_mode(void)
332 {
333 #if RCAR_SYSTEM_SUSPEND
334 static uint32_t reason = RCAR_COLD_BOOT;
335 static uint32_t once;
336
337 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
338 uint8_t data;
339 #endif
340 if (once)
341 return reason;
342
343 once = 1;
344 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
345 return reason;
346
347 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
348 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
349 ERROR("BL2: REG Keep10 READ ERROR.\n");
350 panic();
351 }
352
353 if (KEEP10_MAGIC != data)
354 reason = RCAR_WARM_BOOT;
355 #else
356 reason = RCAR_WARM_BOOT;
357 #endif
358 return reason;
359 #else
360 return RCAR_COLD_BOOT;
361 #endif
362 }
363
364 #if RCAR_GEN3_BL33_GZIP == 1
bl2_plat_preload_setup(void)365 void bl2_plat_preload_setup(void)
366 {
367 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
368 }
369 #endif
370
bl2_plat_handle_pre_image_load(unsigned int image_id)371 int bl2_plat_handle_pre_image_load(unsigned int image_id)
372 {
373 u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
374 bl_mem_params_node_t *bl_mem_params;
375
376 bl_mem_params = get_bl_mem_params_node(image_id);
377
378 #if RCAR_GEN3_BL33_GZIP == 1
379 if (image_id == BL33_IMAGE_ID) {
380 image_decompress_prepare(&bl_mem_params->image_info);
381 }
382 #endif
383
384 if (image_id != BL31_IMAGE_ID)
385 return 0;
386
387 if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
388 goto cold_boot;
389
390 *boot_kind = RCAR_WARM_BOOT;
391 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
392
393 console_flush();
394 bl2_plat_flush_bl31_params();
395
396 /* will not return */
397 bl2_enter_bl31(&bl_mem_params->ep_info);
398
399 cold_boot:
400 *boot_kind = RCAR_COLD_BOOT;
401 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
402
403 return 0;
404 }
405
rcar_get_dest_addr_from_cert(uint32_t certid,uintptr_t * dest)406 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest)
407 {
408 uint32_t cert, len;
409 int ret;
410
411 ret = rcar_get_certificate(certid, &cert);
412 if (ret) {
413 ERROR("%s : cert file load error", __func__);
414 return 1;
415 }
416
417 rcar_read_certificate((uint64_t) cert, &len, dest);
418
419 return 0;
420 }
421
bl2_plat_handle_post_image_load(unsigned int image_id)422 int bl2_plat_handle_post_image_load(unsigned int image_id)
423 {
424 static bl2_to_bl31_params_mem_t *params;
425 bl_mem_params_node_t *bl_mem_params;
426 uintptr_t dest;
427 int ret;
428
429 if (!params) {
430 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
431 memset((void *)PARAMS_BASE, 0, sizeof(*params));
432 }
433
434 bl_mem_params = get_bl_mem_params_node(image_id);
435
436 switch (image_id) {
437 case BL31_IMAGE_ID:
438 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID,
439 &dest);
440 if (!ret)
441 bl_mem_params->image_info.image_base = dest;
442 break;
443 case BL32_IMAGE_ID:
444 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID,
445 &dest);
446 if (!ret)
447 bl_mem_params->image_info.image_base = dest;
448
449 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
450 sizeof(entry_point_info_t));
451 break;
452 case BL33_IMAGE_ID:
453 #if RCAR_GEN3_BL33_GZIP == 1
454 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
455 /* decompress gzip-compressed image */
456 ret = image_decompress(&bl_mem_params->image_info);
457 if (ret != 0) {
458 return ret;
459 }
460 } else {
461 /* plain image, copy it in place */
462 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
463 bl_mem_params->image_info.image_size);
464 }
465 #endif
466 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
467 sizeof(entry_point_info_t));
468 break;
469 }
470
471 return 0;
472 }
473
bl2_plat_sec_mem_layout(void)474 struct meminfo *bl2_plat_sec_mem_layout(void)
475 {
476 return &bl2_tzram_layout;
477 }
478
bl2_populate_compatible_string(void * dt)479 static void bl2_populate_compatible_string(void *dt)
480 {
481 uint32_t board_type;
482 uint32_t board_rev;
483 uint32_t reg;
484 int ret;
485
486 fdt_setprop_u32(dt, 0, "#address-cells", 2);
487 fdt_setprop_u32(dt, 0, "#size-cells", 2);
488
489 /* Populate compatible string */
490 rcar_get_board_type(&board_type, &board_rev);
491 switch (board_type) {
492 case BOARD_SALVATOR_X:
493 ret = fdt_setprop_string(dt, 0, "compatible",
494 "renesas,salvator-x");
495 break;
496 case BOARD_SALVATOR_XS:
497 ret = fdt_setprop_string(dt, 0, "compatible",
498 "renesas,salvator-xs");
499 break;
500 case BOARD_STARTER_KIT:
501 ret = fdt_setprop_string(dt, 0, "compatible",
502 "renesas,m3ulcb");
503 break;
504 case BOARD_STARTER_KIT_PRE:
505 ret = fdt_setprop_string(dt, 0, "compatible",
506 "renesas,h3ulcb");
507 break;
508 case BOARD_EAGLE:
509 ret = fdt_setprop_string(dt, 0, "compatible",
510 "renesas,eagle");
511 break;
512 case BOARD_EBISU:
513 case BOARD_EBISU_4D:
514 ret = fdt_setprop_string(dt, 0, "compatible",
515 "renesas,ebisu");
516 break;
517 case BOARD_DRAAK:
518 ret = fdt_setprop_string(dt, 0, "compatible",
519 "renesas,draak");
520 break;
521 default:
522 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
523 panic();
524 }
525
526 if (ret < 0) {
527 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
528 panic();
529 }
530
531 reg = mmio_read_32(RCAR_PRR);
532 switch (reg & PRR_PRODUCT_MASK) {
533 case PRR_PRODUCT_H3:
534 ret = fdt_appendprop_string(dt, 0, "compatible",
535 "renesas,r8a7795");
536 break;
537 case PRR_PRODUCT_M3:
538 ret = fdt_appendprop_string(dt, 0, "compatible",
539 "renesas,r8a7796");
540 break;
541 case PRR_PRODUCT_M3N:
542 ret = fdt_appendprop_string(dt, 0, "compatible",
543 "renesas,r8a77965");
544 break;
545 case PRR_PRODUCT_V3M:
546 ret = fdt_appendprop_string(dt, 0, "compatible",
547 "renesas,r8a77970");
548 break;
549 case PRR_PRODUCT_E3:
550 ret = fdt_appendprop_string(dt, 0, "compatible",
551 "renesas,r8a77990");
552 break;
553 case PRR_PRODUCT_D3:
554 ret = fdt_appendprop_string(dt, 0, "compatible",
555 "renesas,r8a77995");
556 break;
557 default:
558 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
559 panic();
560 }
561
562 if (ret < 0) {
563 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
564 panic();
565 }
566 }
567
bl2_add_rpc_node(void)568 static void bl2_add_rpc_node(void)
569 {
570 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
571 int ret, node;
572
573 node = ret = fdt_add_subnode(fdt, 0, "soc");
574 if (ret < 0) {
575 goto err;
576 }
577
578 node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000");
579 if (ret < 0) {
580 goto err;
581 }
582
583 ret = fdt_setprop_string(fdt, node, "status", "okay");
584 if (ret < 0) {
585 goto err;
586 }
587
588 return;
589 err:
590 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
591 panic();
592 #endif
593 }
594
bl2_add_dram_entry(uint64_t start,uint64_t size)595 static void bl2_add_dram_entry(uint64_t start, uint64_t size)
596 {
597 char nodename[32] = { 0 };
598 uint64_t fdtsize;
599 int ret, node;
600
601 fdtsize = cpu_to_fdt64(size);
602
603 snprintf(nodename, sizeof(nodename), "memory@");
604 unsigned_num_print(start, 16, nodename + strlen(nodename));
605 node = ret = fdt_add_subnode(fdt, 0, nodename);
606 if (ret < 0) {
607 goto err;
608 }
609
610 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
611 if (ret < 0) {
612 goto err;
613 }
614
615 ret = fdt_setprop_u64(fdt, node, "reg", start);
616 if (ret < 0) {
617 goto err;
618 }
619
620 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
621 sizeof(fdtsize));
622 if (ret < 0) {
623 goto err;
624 }
625
626 return;
627 err:
628 NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n",
629 start, start + size - 1, ret);
630 panic();
631 }
632
bl2_advertise_dram_entries(uint64_t dram_config[8])633 static void bl2_advertise_dram_entries(uint64_t dram_config[8])
634 {
635 uint64_t start, size, size32;
636 int chan;
637
638 for (chan = 0; chan < 4; chan++) {
639 start = dram_config[2 * chan];
640 size = dram_config[2 * chan + 1];
641 if (!size)
642 continue;
643
644 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
645 chan, start, start + size - 1,
646 (size >> 30) ? : size >> 20,
647 (size >> 30) ? "G" : "M");
648 }
649
650 /*
651 * We add the DT nodes in reverse order here. The fdt_add_subnode()
652 * adds the DT node before the first existing DT node, so we have
653 * to add them in reverse order to get nodes sorted by address in
654 * the resulting DT.
655 */
656 for (chan = 3; chan >= 0; chan--) {
657 start = dram_config[2 * chan];
658 size = dram_config[2 * chan + 1];
659 if (!size)
660 continue;
661
662 /*
663 * Channel 0 is mapped in 32bit space and the first
664 * 128 MiB are reserved and the maximum size is 2GiB.
665 */
666 if (chan == 0) {
667 /* Limit the 32bit entry to 2 GiB - 128 MiB */
668 size32 = size - 0x8000000U;
669 if (size32 >= 0x78000000U) {
670 size32 = 0x78000000U;
671 }
672
673 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
674 bl2_add_dram_entry(0x48000000, size32);
675
676 /*
677 * If channel 0 is less than 2 GiB long, the
678 * entire memory fits into the 32bit space entry,
679 * so move on to the next channel.
680 */
681 if (size <= 0x80000000U) {
682 continue;
683 }
684
685 /*
686 * If channel 0 is more than 2 GiB long, emit
687 * another entry which covers the rest of the
688 * memory in channel 0, in the 64bit space.
689 *
690 * Start of this new entry is at 2 GiB offset
691 * from the beginning of the 64bit channel 0
692 * address, size is 2 GiB shorter than total
693 * size of the channel.
694 */
695 start += 0x80000000U;
696 size -= 0x80000000U;
697 }
698
699 bl2_add_dram_entry(start, size);
700 }
701 }
702
bl2_advertise_dram_size(uint32_t product)703 static void bl2_advertise_dram_size(uint32_t product)
704 {
705 uint64_t dram_config[8] = {
706 [0] = 0x400000000ULL,
707 [2] = 0x500000000ULL,
708 [4] = 0x600000000ULL,
709 [6] = 0x700000000ULL,
710 };
711
712 switch (product) {
713 case PRR_PRODUCT_H3:
714 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
715 /* 4GB(1GBx4) */
716 dram_config[1] = 0x40000000ULL;
717 dram_config[3] = 0x40000000ULL;
718 dram_config[5] = 0x40000000ULL;
719 dram_config[7] = 0x40000000ULL;
720 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
721 (RCAR_DRAM_CHANNEL == 5) && \
722 (RCAR_DRAM_SPLIT == 2)
723 /* 4GB(2GBx2 2ch split) */
724 dram_config[1] = 0x80000000ULL;
725 dram_config[3] = 0x80000000ULL;
726 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
727 /* 8GB(2GBx4: default) */
728 dram_config[1] = 0x80000000ULL;
729 dram_config[3] = 0x80000000ULL;
730 dram_config[5] = 0x80000000ULL;
731 dram_config[7] = 0x80000000ULL;
732 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
733 break;
734
735 case PRR_PRODUCT_M3:
736 #if (RCAR_GEN3_ULCB == 1)
737 /* 2GB(1GBx2 2ch split) */
738 dram_config[1] = 0x40000000ULL;
739 dram_config[5] = 0x40000000ULL;
740 #else
741 /* 4GB(2GBx2 2ch split) */
742 dram_config[1] = 0x80000000ULL;
743 dram_config[5] = 0x80000000ULL;
744 #endif
745 break;
746
747 case PRR_PRODUCT_M3N:
748 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
749 /* 4GB(4GBx1) */
750 dram_config[1] = 0x100000000ULL;
751 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
752 /* 2GB(1GBx2) */
753 dram_config[1] = 0x80000000ULL;
754 #endif
755 break;
756
757 case PRR_PRODUCT_V3M:
758 /* 1GB(512MBx2) */
759 dram_config[1] = 0x40000000ULL;
760 break;
761
762 case PRR_PRODUCT_E3:
763 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
764 /* 1GB(512MBx2) */
765 dram_config[1] = 0x40000000ULL;
766 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
767 /* 2GB(512MBx4) */
768 dram_config[1] = 0x80000000ULL;
769 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
770 /* 4GB(1GBx4) */
771 dram_config[1] = 0x100000000ULL;
772 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
773 break;
774
775 case PRR_PRODUCT_D3:
776 /* 512MB */
777 dram_config[1] = 0x20000000ULL;
778 break;
779 }
780
781 bl2_advertise_dram_entries(dram_config);
782 }
783
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)784 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
785 u_register_t arg3, u_register_t arg4)
786 {
787 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
788 uint32_t product, product_cut, major, minor;
789 int32_t ret;
790 const char *str;
791 const char *unknown = "unknown";
792 const char *cpu_ca57 = "CA57";
793 const char *cpu_ca53 = "CA53";
794 const char *product_m3n = "M3N";
795 const char *product_h3 = "H3";
796 const char *product_m3 = "M3";
797 const char *product_e3 = "E3";
798 const char *product_d3 = "D3";
799 const char *product_v3m = "V3M";
800 const char *lcs_secure = "SE";
801 const char *lcs_cm = "CM";
802 const char *lcs_dm = "DM";
803 const char *lcs_sd = "SD";
804 const char *lcs_fa = "FA";
805 const char *sscg_off = "PLL1 nonSSCG Clock select";
806 const char *sscg_on = "PLL1 SSCG Clock select";
807 const char *boot_hyper80 = "HyperFlash(80MHz)";
808 const char *boot_qspi40 = "QSPI Flash(40MHz)";
809 const char *boot_qspi80 = "QSPI Flash(80MHz)";
810 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
811 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
812 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
813 const char *boot_hyper160 = "HyperFlash(150MHz)";
814 #else
815 const char *boot_hyper160 = "HyperFlash(160MHz)";
816 #endif
817 #if (RCAR_LOSSY_ENABLE == 1)
818 int fcnlnode;
819 #endif
820
821 bl2_init_generic_timer();
822
823 reg = mmio_read_32(RCAR_MODEMR);
824 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
825 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
826
827 bl2_cpg_init();
828
829 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
830 boot_cpu == MODEMR_BOOT_CPU_CA53) {
831 rcar_pfc_init();
832 rcar_console_boot_init();
833 }
834
835 plat_rcar_gic_driver_init();
836 plat_rcar_gic_init();
837 rcar_swdt_init();
838
839 /* FIQ interrupts are taken to EL3 */
840 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
841
842 write_daifclr(DAIF_FIQ_BIT);
843
844 reg = read_midr();
845 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
846 switch (midr) {
847 case MIDR_CA57:
848 str = cpu_ca57;
849 break;
850 case MIDR_CA53:
851 str = cpu_ca53;
852 break;
853 default:
854 str = unknown;
855 break;
856 }
857
858 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
859 version_of_renesas);
860
861 reg = mmio_read_32(RCAR_PRR);
862 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
863 product = reg & PRR_PRODUCT_MASK;
864
865 switch (product) {
866 case PRR_PRODUCT_H3:
867 str = product_h3;
868 break;
869 case PRR_PRODUCT_M3:
870 str = product_m3;
871 break;
872 case PRR_PRODUCT_M3N:
873 str = product_m3n;
874 break;
875 case PRR_PRODUCT_V3M:
876 str = product_v3m;
877 break;
878 case PRR_PRODUCT_E3:
879 str = product_e3;
880 break;
881 case PRR_PRODUCT_D3:
882 str = product_d3;
883 break;
884 default:
885 str = unknown;
886 break;
887 }
888
889 if ((PRR_PRODUCT_M3 == product) &&
890 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
891 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
892 /* M3 Ver.1.1 or Ver.1.2 */
893 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
894 str);
895 } else {
896 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
897 str,
898 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
899 }
900 } else {
901 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
902 major = major + RCAR_MAJOR_OFFSET;
903 minor = reg & RCAR_MINOR_MASK;
904 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
905 }
906
907 if (product == PRR_PRODUCT_E3) {
908 reg = mmio_read_32(RCAR_MODEMR);
909 sscg = reg & RCAR_SSCG_MASK;
910 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
911 NOTICE("BL2: %s\n", str);
912 }
913
914 rcar_get_board_type(&type, &rev);
915
916 switch (type) {
917 case BOARD_SALVATOR_X:
918 case BOARD_KRIEK:
919 case BOARD_STARTER_KIT:
920 case BOARD_SALVATOR_XS:
921 case BOARD_EBISU:
922 case BOARD_STARTER_KIT_PRE:
923 case BOARD_EBISU_4D:
924 case BOARD_DRAAK:
925 case BOARD_EAGLE:
926 break;
927 default:
928 type = BOARD_UNKNOWN;
929 break;
930 }
931
932 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
933 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
934 else {
935 NOTICE("BL2: Board is %s Rev.%d.%d\n",
936 GET_BOARD_NAME(type),
937 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
938 }
939
940 #if RCAR_LSI != RCAR_AUTO
941 if (product != TARGET_PRODUCT) {
942 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
943 ERROR("BL2: Please write the correct IPL to flash memory.\n");
944 panic();
945 }
946 #endif
947 rcar_avs_init();
948 rcar_avs_setting();
949
950 switch (boot_dev) {
951 case MODEMR_BOOT_DEV_HYPERFLASH160:
952 str = boot_hyper160;
953 break;
954 case MODEMR_BOOT_DEV_HYPERFLASH80:
955 str = boot_hyper80;
956 break;
957 case MODEMR_BOOT_DEV_QSPI_FLASH40:
958 str = boot_qspi40;
959 break;
960 case MODEMR_BOOT_DEV_QSPI_FLASH80:
961 str = boot_qspi80;
962 break;
963 case MODEMR_BOOT_DEV_EMMC_25X1:
964 #if RCAR_LSI == RCAR_D3
965 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
966 panic();
967 #endif
968 str = boot_emmc25x1;
969 break;
970 case MODEMR_BOOT_DEV_EMMC_50X8:
971 #if RCAR_LSI == RCAR_D3
972 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
973 panic();
974 #endif
975 str = boot_emmc50x8;
976 break;
977 default:
978 str = unknown;
979 break;
980 }
981 NOTICE("BL2: Boot device is %s\n", str);
982
983 rcar_avs_setting();
984 reg = rcar_rom_get_lcs(&lcs);
985 if (reg) {
986 str = unknown;
987 goto lcm_state;
988 }
989
990 switch (lcs) {
991 case LCS_CM:
992 str = lcs_cm;
993 break;
994 case LCS_DM:
995 str = lcs_dm;
996 break;
997 case LCS_SD:
998 str = lcs_sd;
999 break;
1000 case LCS_SE:
1001 str = lcs_secure;
1002 break;
1003 case LCS_FA:
1004 str = lcs_fa;
1005 break;
1006 default:
1007 str = unknown;
1008 break;
1009 }
1010
1011 lcm_state:
1012 NOTICE("BL2: LCM state is %s\n", str);
1013
1014 rcar_avs_end();
1015 is_ddr_backup_mode();
1016
1017 bl2_tzram_layout.total_base = BL31_BASE;
1018 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
1019
1020 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1021 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1022 ret = rcar_dram_init();
1023 if (ret) {
1024 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
1025 panic();
1026 }
1027 rcar_qos_init();
1028 }
1029
1030 /* Set up FDT */
1031 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
1032 if (ret) {
1033 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
1034 panic();
1035 }
1036
1037 /* Add platform compatible string */
1038 bl2_populate_compatible_string(fdt);
1039
1040 /* Enable RPC if unlocked */
1041 bl2_add_rpc_node();
1042
1043 /* Print DRAM layout */
1044 bl2_advertise_dram_size(product);
1045
1046 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1047 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
1048 if (rcar_emmc_init() != EMMC_SUCCESS) {
1049 NOTICE("BL2: Failed to eMMC driver initialize.\n");
1050 panic();
1051 }
1052 rcar_emmc_memcard_power(EMMC_POWER_ON);
1053 if (rcar_emmc_mount() != EMMC_SUCCESS) {
1054 NOTICE("BL2: Failed to eMMC mount operation.\n");
1055 panic();
1056 }
1057 } else {
1058 rcar_rpc_init();
1059 rcar_dma_init();
1060 }
1061
1062 reg = mmio_read_32(RST_WDTRSTCR);
1063 reg &= ~WDTRSTCR_RWDT_RSTMSK;
1064 reg |= WDTRSTCR_PASSWORD;
1065 mmio_write_32(RST_WDTRSTCR, reg);
1066
1067 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
1068 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
1069
1070 reg = mmio_read_32(RCAR_PRR);
1071 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
1072 mmio_write_32(CPG_CA57DBGRCR,
1073 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
1074
1075 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
1076 mmio_write_32(CPG_CA53DBGRCR,
1077 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
1078
1079 if (product_cut == PRR_PRODUCT_H3_CUT10) {
1080 reg = mmio_read_32(CPG_PLL2CR);
1081 reg &= ~((uint32_t) 1 << 5);
1082 mmio_write_32(CPG_PLL2CR, reg);
1083
1084 reg = mmio_read_32(CPG_PLL4CR);
1085 reg &= ~((uint32_t) 1 << 5);
1086 mmio_write_32(CPG_PLL4CR, reg);
1087
1088 reg = mmio_read_32(CPG_PLL0CR);
1089 reg &= ~((uint32_t) 1 << 12);
1090 mmio_write_32(CPG_PLL0CR, reg);
1091 }
1092 #if (RCAR_LOSSY_ENABLE == 1)
1093 NOTICE("BL2: Lossy Decomp areas\n");
1094
1095 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
1096 if (fcnlnode < 0) {
1097 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
1098 fcnlnode);
1099 panic();
1100 }
1101
1102 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
1103 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
1104 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
1105 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
1106 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
1107 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
1108 #endif
1109
1110 fdt_pack(fdt);
1111 NOTICE("BL2: FDT at %p\n", fdt);
1112
1113 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1114 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
1115 rcar_io_emmc_setup();
1116 else
1117 rcar_io_setup();
1118 }
1119
bl2_el3_plat_arch_setup(void)1120 void bl2_el3_plat_arch_setup(void)
1121 {
1122 #if RCAR_BL2_DCACHE == 1
1123 NOTICE("BL2: D-Cache enable\n");
1124 rcar_configure_mmu_el3(BL2_BASE,
1125 BL2_END - BL2_BASE,
1126 BL2_RO_BASE, BL2_RO_LIMIT
1127 #if USE_COHERENT_MEM
1128 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
1129 #endif
1130 );
1131 #endif
1132 }
1133
bl2_platform_setup(void)1134 void bl2_platform_setup(void)
1135 {
1136
1137 }
1138
bl2_init_generic_timer(void)1139 static void bl2_init_generic_timer(void)
1140 {
1141 /* FIXME: V3M 16.666 MHz ? */
1142 #if RCAR_LSI == RCAR_D3
1143 uint32_t reg_cntfid = EXTAL_DRAAK;
1144 #elif RCAR_LSI == RCAR_E3
1145 uint32_t reg_cntfid = EXTAL_EBISU;
1146 #else /* RCAR_LSI == RCAR_E3 */
1147 uint32_t reg;
1148 uint32_t reg_cntfid;
1149 uint32_t modemr;
1150 uint32_t modemr_pll;
1151 uint32_t board_type;
1152 uint32_t board_rev;
1153 uint32_t pll_table[] = {
1154 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
1155 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
1156 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
1157 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
1158 };
1159
1160 modemr = mmio_read_32(RCAR_MODEMR);
1161 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
1162
1163 /* Set frequency data in CNTFID0 */
1164 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
1165 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1166 switch (modemr_pll) {
1167 case MD14_MD13_TYPE_0:
1168 rcar_get_board_type(&board_type, &board_rev);
1169 if (BOARD_SALVATOR_XS == board_type) {
1170 reg_cntfid = EXTAL_SALVATOR_XS;
1171 }
1172 break;
1173 case MD14_MD13_TYPE_3:
1174 if (PRR_PRODUCT_H3_CUT10 == reg) {
1175 reg_cntfid = reg_cntfid >> 1U;
1176 }
1177 break;
1178 default:
1179 /* none */
1180 break;
1181 }
1182 #endif /* RCAR_LSI == RCAR_E3 */
1183 /* Update memory mapped and register based freqency */
1184 write_cntfrq_el0((u_register_t )reg_cntfid);
1185 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
1186 /* Enable counter */
1187 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
1188 (uint32_t)CNTCR_EN);
1189 }
1190