• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1# CPU INFOrmation library
2
3[![BSD (2 clause) License](https://img.shields.io/badge/License-BSD%202--Clause%20%22Simplified%22%20License-blue.svg)](https://github.com/pytorch/cpuinfo/blob/master/LICENSE)
4[![Linux/Mac build status](https://img.shields.io/travis/pytorch/cpuinfo.svg)](https://travis-ci.org/pytorch/cpuinfo)
5[![Windows build status](https://ci.appveyor.com/api/projects/status/g5khy9nr0xm458t7/branch/master?svg=true)](https://ci.appveyor.com/project/MaratDukhan/cpuinfo/branch/master)
6
7cpuinfo is a library to detect essential for performance optimization information about host CPU.
8
9## Features
10
11- **Cross-platform** availability:
12  - Linux, Windows, macOS, Android, and iOS operating systems
13  - x86, x86-64, ARM, and ARM64 architectures
14- Modern **C/C++ interface**
15  - Thread-safe
16  - No memory allocation after initialization
17  - No exceptions thrown
18- Detection of **supported instruction sets**, up to AVX512 (x86) and ARMv8.3 extensions
19- Detection of SoC and core information:
20  - **Processor (SoC) name**
21  - Vendor and **microarchitecture** for each CPU core
22  - ID (**MIDR** on ARM, **CPUID** leaf 1 EAX value on x86) for each CPU core
23- Detection of **cache information**:
24  - Cache type (instruction/data/unified), size and line size
25  - Cache associativity
26  - Cores and logical processors (hyper-threads) sharing the cache
27- Detection of **topology information** (relative between logical processors, cores, and processor packages)
28- Well-tested **production-quality** code:
29  - 60+ mock tests based on data from real devices
30  - Includes work-arounds for common bugs in hardware and OS kernels
31  - Supports systems with heterogenous cores, such as **big.LITTLE** and Max.Med.Min
32- Permissive **open-source** license (Simplified BSD)
33
34## Examples
35
36Log processor name:
37
38```c
39cpuinfo_initialize();
40printf("Running on %s CPU\n", cpuinfo_get_package(0)->name);
41```
42
43Detect if target is a 32-bit or 64-bit ARM system:
44
45```c
46#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
47    /* 32-bit ARM-specific code here */
48#endif
49```
50
51Check if the host CPU support ARM NEON
52
53```c
54cpuinfo_initialize();
55if (cpuinfo_has_arm_neon()) {
56    neon_implementation(arguments);
57}
58```
59
60Check if the host CPU supports x86 AVX
61
62```c
63cpuinfo_initialize();
64if (cpuinfo_has_x86_avx()) {
65    avx_implementation(arguments);
66}
67```
68
69Check if the thread runs on a Cortex-A53 core
70
71```c
72cpuinfo_initialize();
73switch (cpuinfo_get_current_core()->uarch) {
74    case cpuinfo_uarch_cortex_a53:
75        cortex_a53_implementation(arguments);
76        break;
77    default:
78        generic_implementation(arguments);
79        break;
80}
81```
82
83Get the size of level 1 data cache on the fastest core in the processor (e.g. big core in big.LITTLE ARM systems):
84
85```c
86cpuinfo_initialize();
87const size_t l1_size = cpuinfo_get_processor(0)->cache.l1d->size;
88```
89
90Pin thread to cores sharing L2 cache with the current core (Linux or Android)
91
92```c
93cpuinfo_initialize();
94cpu_set_t cpu_set;
95CPU_ZERO(&cpu_set);
96const struct cpuinfo_cache* current_l2 = cpuinfo_get_current_processor()->cache.l2;
97for (uint32_t i = 0; i < current_l2->processor_count; i++) {
98    CPU_SET(cpuinfo_get_processor(current_l2->processor_start + i)->linux_id, &cpu_set);
99}
100pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpu_set);
101```
102
103## Exposed information
104- [x] Processor (SoC) name
105- [x] Microarchitecture
106- [x] Usable instruction sets
107- [ ] CPU frequency
108- [x] Cache
109  - [x] Size
110  - [x] Associativity
111  - [x] Line size
112  - [x] Number of partitions
113  - [x] Flags (unified, inclusive, complex hash function)
114  - [x] Topology (logical processors that share this cache level)
115- [ ] TLB
116  - [ ] Number of entries
117  - [ ] Associativity
118  - [ ] Covered page types (instruction, data)
119  - [ ] Covered page sizes
120- [x] Topology information
121  - [x] Logical processors
122  - [x] Cores
123  - [x] Packages (sockets)
124
125## Supported environments:
126- [x] Android
127  - [x] x86 ABI
128  - [x] x86_64 ABI
129  - [x] armeabi ABI
130  - [x] armeabiv7-a ABI
131  - [x] arm64-v8a ABI
132  - [ ] ~~mips ABI~~
133  - [ ] ~~mips64 ABI~~
134- [x] Linux
135  - [x] x86
136  - [x] x86-64
137  - [x] 32-bit ARM (ARMv5T and later)
138  - [x] ARM64
139  - [ ] PowerPC64
140- [x] iOS
141  - [x] x86 (iPhone simulator)
142  - [x] x86-64 (iPhone simulator)
143  - [x] ARMv7
144  - [x] ARM64
145- [x] OS X
146  - [x] x86
147  - [x] x86-64
148- [x] Windows
149  - [x] x86
150  - [x] x86-64
151
152## Methods
153
154- Processor (SoC) name detection
155  - [x] Using CPUID leaves 0x80000002–0x80000004 on x86/x86-64
156  - [x] Using `/proc/cpuinfo` on ARM
157  - [x] Using `ro.chipname`, `ro.board.platform`, `ro.product.board`, `ro.mediatek.platform`, `ro.arch` properties (Android)
158  - [ ] Using kernel log (`dmesg`) on ARM Linux
159- Vendor and microarchitecture detection
160  - [x] Intel-designed x86/x86-64 cores (up to Sunny Cove, Goldmont Plus, and Knights Mill)
161  - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen 2)
162  - [ ] VIA-designed x86/x86-64 cores
163  - [ ] Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise)
164  - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/N1)
165  - [x] Qualcomm-designed ARM cores (Scorpion, Krait, and Kryo)
166  - [x] Nvidia-designed ARM cores (Denver and Carmel)
167  - [x] Samsung-designed ARM cores (Exynos)
168  - [x] Intel-designed ARM cores (XScale up to 3rd-gen)
169  - [x] Apple-designed ARM cores (up to Lightning and Thunder)
170  - [x] Cavium-designed ARM cores (ThunderX)
171  - [x] AppliedMicro-designed ARM cores (X-Gene)
172- Instruction set detection
173  - [x] Using CPUID (x86/x86-64)
174  - [x] Using `/proc/cpuinfo` on 32-bit ARM EABI (Linux)
175  - [x] Using microarchitecture heuristics on (32-bit ARM)
176  - [x] Using `FPSID` and `WCID` registers (32-bit ARM)
177  - [x] Using `getauxval` (Linux/ARM)
178  - [x] Using `/proc/self/auxv` (Android/ARM)
179  - [ ] Using instruction probing on ARM (Linux)
180  - [ ] Using CPUID registers on ARM64 (Linux)
181- Cache detection
182  - [x] Using CPUID leaf 0x00000002 (x86/x86-64)
183  - [x] Using CPUID leaf 0x00000004 (non-AMD x86/x86-64)
184  - [ ] Using CPUID leaves 0x80000005-0x80000006 (AMD x86/x86-64)
185  - [x] Using CPUID leaf 0x8000001D (AMD x86/x86-64)
186  - [x] Using `/proc/cpuinfo` (Linux/pre-ARMv7)
187  - [x] Using microarchitecture heuristics (ARM)
188  - [x] Using chipset name (ARM)
189  - [x] Using `sysctlbyname` (Mach)
190  - [x] Using sysfs `typology` directories (ARM/Linux)
191  - [ ] Using sysfs `cache` directories (Linux)
192- TLB detection
193  - [x] Using CPUID leaf 0x00000002 (x86/x86-64)
194  - [ ] Using CPUID leaves 0x80000005-0x80000006 and 0x80000019 (AMD x86/x86-64)
195  - [x] Using microarchitecture heuristics (ARM)
196- Topology detection
197  - [x] Using CPUID leaf 0x00000001 on x86/x86-64 (legacy APIC ID)
198  - [x] Using CPUID leaf 0x0000000B on x86/x86-64 (Intel APIC ID)
199  - [ ] Using CPUID leaf 0x8000001E on x86/x86-64 (AMD APIC ID)
200  - [x] Using `/proc/cpuinfo` (Linux)
201  - [x] Using `host_info` (Mach)
202  - [x] Using `GetLogicalProcessorInformationEx` (Windows)
203  - [x] Using sysfs (Linux)
204  - [x] Using chipset name (ARM/Linux)
205