1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <unistd.h>
27 #if HAVE_ALLOCA_H
28 # include <alloca.h>
29 #endif
30
31 #include "CUnit/Basic.h"
32
33 #include "amdgpu_test.h"
34 #include "amdgpu_drm.h"
35 #include "amdgpu_internal.h"
36
37 #include <pthread.h>
38
39
40 /*
41 * This defines the delay in MS after which memory location designated for
42 * compression against reference value is written to, unblocking command
43 * processor
44 */
45 #define WRITE_MEM_ADDRESS_DELAY_MS 100
46
47 #define PACKET_TYPE3 3
48
49 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
50 (((op) & 0xFF) << 8) | \
51 ((n) & 0x3FFF) << 16)
52
53 #define PACKET3_WAIT_REG_MEM 0x3C
54 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
55 /* 0 - always
56 * 1 - <
57 * 2 - <=
58 * 3 - ==
59 * 4 - !=
60 * 5 - >=
61 * 6 - >
62 */
63 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
64 /* 0 - reg
65 * 1 - mem
66 */
67 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
68 /* 0 - wait_reg_mem
69 * 1 - wr_wait_wr_reg
70 */
71 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
72 /* 0 - me
73 * 1 - pfp
74 */
75
76 #define PACKET3_WRITE_DATA 0x37
77 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
78 /* 0 - register
79 * 1 - memory (sync - via GRBM)
80 * 2 - gl2
81 * 3 - gds
82 * 4 - reserved
83 * 5 - memory (async - direct)
84 */
85 #define WR_ONE_ADDR (1 << 16)
86 #define WR_CONFIRM (1 << 20)
87 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
88 /* 0 - LRU
89 * 1 - Stream
90 */
91 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
92 /* 0 - me
93 * 1 - pfp
94 * 2 - ce
95 */
96
97 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
98
99 #define SDMA_PKT_HEADER_OP(x) (x & 0xff)
100 #define SDMA_OP_POLL_REGMEM 8
101
102 static amdgpu_device_handle device_handle;
103 static uint32_t major_version;
104 static uint32_t minor_version;
105
106 static pthread_t stress_thread;
107 static uint32_t *ptr;
108
109 static uint32_t family_id;
110 static uint32_t chip_rev;
111 static uint32_t chip_id;
112
113 int use_uc_mtype = 0;
114
115 static void amdgpu_deadlock_helper(unsigned ip_type);
116 static void amdgpu_deadlock_gfx(void);
117 static void amdgpu_deadlock_compute(void);
118 static void amdgpu_illegal_reg_access();
119 static void amdgpu_illegal_mem_access();
120 static void amdgpu_deadlock_sdma(void);
121 static void amdgpu_dispatch_hang_gfx(void);
122 static void amdgpu_dispatch_hang_compute(void);
123 static void amdgpu_dispatch_hang_slow_gfx(void);
124 static void amdgpu_dispatch_hang_slow_compute(void);
125 static void amdgpu_draw_hang_gfx(void);
126 static void amdgpu_draw_hang_slow_gfx(void);
127
suite_deadlock_tests_enable(void)128 CU_BOOL suite_deadlock_tests_enable(void)
129 {
130 CU_BOOL enable = CU_TRUE;
131
132 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
133 &minor_version, &device_handle))
134 return CU_FALSE;
135
136 family_id = device_handle->info.family_id;
137 chip_id = device_handle->info.chip_external_rev;
138 chip_rev = device_handle->info.chip_rev;
139
140 /*
141 * Only enable for ASICs supporting GPU reset and for which it's enabled
142 * by default (currently GFX8/9 dGPUS)
143 */
144 if (family_id != AMDGPU_FAMILY_VI &&
145 family_id != AMDGPU_FAMILY_AI &&
146 family_id != AMDGPU_FAMILY_CI) {
147 printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
148 enable = CU_FALSE;
149 }
150
151 if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
152 if (amdgpu_set_test_active("Deadlock Tests",
153 "gfx ring block test (set amdgpu.lockup_timeout=50)",
154 CU_FALSE))
155 fprintf(stderr, "test deactivation failed - %s\n",
156 CU_get_error_msg());
157 }
158
159 if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
160 use_uc_mtype = 1;
161
162 if (amdgpu_device_deinitialize(device_handle))
163 return CU_FALSE;
164
165 return enable;
166 }
167
suite_deadlock_tests_init(void)168 int suite_deadlock_tests_init(void)
169 {
170 int r;
171
172 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
173 &minor_version, &device_handle);
174
175 if (r) {
176 if ((r == -EACCES) && (errno == EACCES))
177 printf("\n\nError:%s. "
178 "Hint:Try to run this test program as root.",
179 strerror(errno));
180 return CUE_SINIT_FAILED;
181 }
182
183 return CUE_SUCCESS;
184 }
185
suite_deadlock_tests_clean(void)186 int suite_deadlock_tests_clean(void)
187 {
188 int r = amdgpu_device_deinitialize(device_handle);
189
190 if (r == 0)
191 return CUE_SUCCESS;
192 else
193 return CUE_SCLEAN_FAILED;
194 }
195
196
197 CU_TestInfo deadlock_tests[] = {
198 { "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx },
199 { "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute },
200 { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma },
201 { "illegal reg access test", amdgpu_illegal_reg_access },
202 { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access },
203 { "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx },
204 { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute },
205 { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx },
206 { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute },
207 { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx },
208 { "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx },
209 CU_TEST_INFO_NULL,
210 };
211
write_mem_address(void * data)212 static void *write_mem_address(void *data)
213 {
214 int i;
215
216 /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */
217 for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++)
218 usleep(1000);
219
220 ptr[256] = 0x1;
221
222 return 0;
223 }
224
amdgpu_deadlock_gfx(void)225 static void amdgpu_deadlock_gfx(void)
226 {
227 amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX);
228 }
229
amdgpu_deadlock_compute(void)230 static void amdgpu_deadlock_compute(void)
231 {
232 amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE);
233 }
234
amdgpu_deadlock_helper(unsigned ip_type)235 static void amdgpu_deadlock_helper(unsigned ip_type)
236 {
237 amdgpu_context_handle context_handle;
238 amdgpu_bo_handle ib_result_handle;
239 void *ib_result_cpu;
240 uint64_t ib_result_mc_address;
241 struct amdgpu_cs_request ibs_request;
242 struct amdgpu_cs_ib_info ib_info;
243 struct amdgpu_cs_fence fence_status;
244 uint32_t expired;
245 int i, r;
246 amdgpu_bo_list_handle bo_list;
247 amdgpu_va_handle va_handle;
248
249 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
250 CU_ASSERT_EQUAL(r, 0);
251
252 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
253 CU_ASSERT_EQUAL(r, 0);
254
255 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
256 AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
257 &ib_result_handle, &ib_result_cpu,
258 &ib_result_mc_address, &va_handle);
259 CU_ASSERT_EQUAL(r, 0);
260
261 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
262 &bo_list);
263 CU_ASSERT_EQUAL(r, 0);
264
265 ptr = ib_result_cpu;
266
267 ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5);
268 ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
269 WAIT_REG_MEM_FUNCTION(4) | /* != */
270 WAIT_REG_MEM_ENGINE(0)); /* me */
271 ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc;
272 ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
273 ptr[4] = 0x00000000; /* reference value */
274 ptr[5] = 0xffffffff; /* and mask */
275 ptr[6] = 0x00000004; /* poll interval */
276
277 for (i = 7; i < 16; ++i)
278 ptr[i] = 0xffff1000;
279
280
281 ptr[256] = 0x0; /* the memory we wait on to change */
282
283
284
285 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
286 ib_info.ib_mc_address = ib_result_mc_address;
287 ib_info.size = 16;
288
289 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
290 ibs_request.ip_type = ip_type;
291 ibs_request.ring = 0;
292 ibs_request.number_of_ibs = 1;
293 ibs_request.ibs = &ib_info;
294 ibs_request.resources = bo_list;
295 ibs_request.fence_info.handle = NULL;
296 for (i = 0; i < 200; i++) {
297 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
298 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
299
300 }
301
302 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
303 fence_status.context = context_handle;
304 fence_status.ip_type = ip_type;
305 fence_status.ip_instance = 0;
306 fence_status.ring = 0;
307 fence_status.fence = ibs_request.seq_no;
308
309 r = amdgpu_cs_query_fence_status(&fence_status,
310 AMDGPU_TIMEOUT_INFINITE,0, &expired);
311 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
312
313 pthread_join(stress_thread, NULL);
314
315 r = amdgpu_bo_list_destroy(bo_list);
316 CU_ASSERT_EQUAL(r, 0);
317
318 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
319 ib_result_mc_address, 4096);
320 CU_ASSERT_EQUAL(r, 0);
321
322 r = amdgpu_cs_ctx_free(context_handle);
323 CU_ASSERT_EQUAL(r, 0);
324 }
325
amdgpu_deadlock_sdma(void)326 static void amdgpu_deadlock_sdma(void)
327 {
328 amdgpu_context_handle context_handle;
329 amdgpu_bo_handle ib_result_handle;
330 void *ib_result_cpu;
331 uint64_t ib_result_mc_address;
332 struct amdgpu_cs_request ibs_request;
333 struct amdgpu_cs_ib_info ib_info;
334 struct amdgpu_cs_fence fence_status;
335 uint32_t expired;
336 int i, r;
337 amdgpu_bo_list_handle bo_list;
338 amdgpu_va_handle va_handle;
339 struct drm_amdgpu_info_hw_ip info;
340 uint32_t ring_id;
341
342 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &info);
343 CU_ASSERT_EQUAL(r, 0);
344
345 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
346 CU_ASSERT_EQUAL(r, 0);
347
348 for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
349 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
350 CU_ASSERT_EQUAL(r, 0);
351
352 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
353 AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
354 &ib_result_handle, &ib_result_cpu,
355 &ib_result_mc_address, &va_handle);
356 CU_ASSERT_EQUAL(r, 0);
357
358 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
359 &bo_list);
360 CU_ASSERT_EQUAL(r, 0);
361
362 ptr = ib_result_cpu;
363 i = 0;
364
365 ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
366 (0 << 26) | /* WAIT_REG_MEM */
367 (4 << 28) | /* != */
368 (1 << 31); /* memory */
369 ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc;
370 ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
371 ptr[i++] = 0x00000000; /* reference value */
372 ptr[i++] = 0xffffffff; /* and mask */
373 ptr[i++] = 4 | /* poll interval */
374 (0xfff << 16); /* retry count */
375
376 for (; i < 16; i++)
377 ptr[i] = 0;
378
379 ptr[256] = 0x0; /* the memory we wait on to change */
380
381 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
382 ib_info.ib_mc_address = ib_result_mc_address;
383 ib_info.size = 16;
384
385 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
386 ibs_request.ip_type = AMDGPU_HW_IP_DMA;
387 ibs_request.ring = ring_id;
388 ibs_request.number_of_ibs = 1;
389 ibs_request.ibs = &ib_info;
390 ibs_request.resources = bo_list;
391 ibs_request.fence_info.handle = NULL;
392
393 for (i = 0; i < 200; i++) {
394 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
395 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
396
397 }
398
399 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
400 fence_status.context = context_handle;
401 fence_status.ip_type = AMDGPU_HW_IP_DMA;
402 fence_status.ip_instance = 0;
403 fence_status.ring = ring_id;
404 fence_status.fence = ibs_request.seq_no;
405
406 r = amdgpu_cs_query_fence_status(&fence_status,
407 AMDGPU_TIMEOUT_INFINITE,0, &expired);
408 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
409
410 pthread_join(stress_thread, NULL);
411
412 r = amdgpu_bo_list_destroy(bo_list);
413 CU_ASSERT_EQUAL(r, 0);
414
415 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
416 ib_result_mc_address, 4096);
417 CU_ASSERT_EQUAL(r, 0);
418 }
419 r = amdgpu_cs_ctx_free(context_handle);
420 CU_ASSERT_EQUAL(r, 0);
421 }
422
bad_access_helper(int reg_access)423 static void bad_access_helper(int reg_access)
424 {
425 amdgpu_context_handle context_handle;
426 amdgpu_bo_handle ib_result_handle;
427 void *ib_result_cpu;
428 uint64_t ib_result_mc_address;
429 struct amdgpu_cs_request ibs_request;
430 struct amdgpu_cs_ib_info ib_info;
431 struct amdgpu_cs_fence fence_status;
432 uint32_t expired;
433 int i, r;
434 amdgpu_bo_list_handle bo_list;
435 amdgpu_va_handle va_handle;
436
437 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
438 CU_ASSERT_EQUAL(r, 0);
439
440 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
441 AMDGPU_GEM_DOMAIN_GTT, 0, 0,
442 &ib_result_handle, &ib_result_cpu,
443 &ib_result_mc_address, &va_handle);
444 CU_ASSERT_EQUAL(r, 0);
445
446 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
447 &bo_list);
448 CU_ASSERT_EQUAL(r, 0);
449
450 ptr = ib_result_cpu;
451 i = 0;
452
453 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
454 ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM;
455 ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0;
456 ptr[i++] = 0;
457 ptr[i++] = 0xdeadbeef;
458
459 for (; i < 16; ++i)
460 ptr[i] = 0xffff1000;
461
462 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
463 ib_info.ib_mc_address = ib_result_mc_address;
464 ib_info.size = 16;
465
466 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
467 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
468 ibs_request.ring = 0;
469 ibs_request.number_of_ibs = 1;
470 ibs_request.ibs = &ib_info;
471 ibs_request.resources = bo_list;
472 ibs_request.fence_info.handle = NULL;
473
474 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
475 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
476
477
478 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
479 fence_status.context = context_handle;
480 fence_status.ip_type = AMDGPU_HW_IP_GFX;
481 fence_status.ip_instance = 0;
482 fence_status.ring = 0;
483 fence_status.fence = ibs_request.seq_no;
484
485 r = amdgpu_cs_query_fence_status(&fence_status,
486 AMDGPU_TIMEOUT_INFINITE,0, &expired);
487 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
488
489 r = amdgpu_bo_list_destroy(bo_list);
490 CU_ASSERT_EQUAL(r, 0);
491
492 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
493 ib_result_mc_address, 4096);
494 CU_ASSERT_EQUAL(r, 0);
495
496 r = amdgpu_cs_ctx_free(context_handle);
497 CU_ASSERT_EQUAL(r, 0);
498 }
499
amdgpu_illegal_reg_access()500 static void amdgpu_illegal_reg_access()
501 {
502 bad_access_helper(1);
503 }
504
amdgpu_illegal_mem_access()505 static void amdgpu_illegal_mem_access()
506 {
507 bad_access_helper(0);
508 }
509
amdgpu_dispatch_hang_gfx(void)510 static void amdgpu_dispatch_hang_gfx(void)
511 {
512 amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
513 }
514
amdgpu_dispatch_hang_compute(void)515 static void amdgpu_dispatch_hang_compute(void)
516 {
517 amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
518 }
519
amdgpu_dispatch_hang_slow_gfx(void)520 static void amdgpu_dispatch_hang_slow_gfx(void)
521 {
522 amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
523 }
524
amdgpu_dispatch_hang_slow_compute(void)525 static void amdgpu_dispatch_hang_slow_compute(void)
526 {
527 amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
528 }
529
amdgpu_draw_hang_gfx(void)530 static void amdgpu_draw_hang_gfx(void)
531 {
532 int r;
533 struct drm_amdgpu_info_hw_ip info;
534 uint32_t ring_id;
535
536 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
537 CU_ASSERT_EQUAL(r, 0);
538 if (!info.available_rings)
539 printf("SKIP ... as there's no graphic ring\n");
540
541 for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
542 amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
543 amdgpu_memcpy_draw_test(device_handle, ring_id, 1);
544 amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
545 }
546 }
547
amdgpu_draw_hang_slow_gfx(void)548 static void amdgpu_draw_hang_slow_gfx(void)
549 {
550 struct drm_amdgpu_info_hw_ip info;
551 uint32_t ring_id;
552 int r;
553
554 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
555 CU_ASSERT_EQUAL(r, 0);
556
557 for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
558 amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
559 amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id);
560 amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
561 }
562 }
563