1Reading src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz... 2gpu_id: 420 3cmd: X/23360: fence=1029603 4cmd: glxgears/23375: fence=1029604 5############################################################ 6cmdstream: 414 dwords 7t0 write RBBM_PERFCTR_CTL (0170) 8 RBBM_PERFCTR_CTL: 0x1 9108ce000: 0000: 00000170 00000001 10t0 write GRAS_DEBUG_ECO_CONTROL (0c81) 11 GRAS_DEBUG_ECO_CONTROL: 0 12108ce008: 0000: 00000c81 00000000 13t0 write SP_MODE_CONTROL (0ec3) 14 SP_MODE_CONTROL: 0x6 15108ce010: 0000: 00000ec3 00000006 16t0 write TPL1_TP_MODE_CONTROL (0f03) 17 TPL1_TP_MODE_CONTROL: 0x3a 18108ce018: 0000: 00000f03 0000003a 19t0 write UNKNOWN_0D01 (0d01) 20 UNKNOWN_0D01: 0x1 21108ce020: 0000: 00000d01 00000001 22t0 write UNKNOWN_0E42 (0e42) 23 UNKNOWN_0E42: 0 24108ce028: 0000: 00000e42 00000000 25t0 write UCHE_CACHE_WAYS_VFD (0e8c) 26 UCHE_CACHE_WAYS_VFD: 0x7 27108ce030: 0000: 00000e8c 00000007 28t0 write UCHE_CACHE_MODE_CONTROL (0e80) 29 UCHE_CACHE_MODE_CONTROL: 0 30108ce038: 0000: 00000e80 00000000 31t0 write UCHE_INVALIDATE0 (0e8a) 32 UCHE_INVALIDATE0: 0 33 UCHE_INVALIDATE1: 0x12 34108ce040: 0000: 00010e8a 00000000 00000012 35t0 write HLSQ_MODE_CONTROL (0e05) 36 HLSQ_MODE_CONTROL: 0 37108ce04c: 0000: 00000e05 00000000 38t0 write UNKNOWN_0CC5 (0cc5) 39 UNKNOWN_0CC5: 0x6 40108ce054: 0000: 00000cc5 00000006 41t0 write UNKNOWN_0CC6 (0cc6) 42 UNKNOWN_0CC6: 0 43108ce05c: 0000: 00000cc6 00000000 44t0 write UNKNOWN_0EC2 (0ec2) 45 UNKNOWN_0EC2: 0x40000 46108ce064: 0000: 00000ec2 00040000 47t0 write UNKNOWN_2001 (2001) 48 UNKNOWN_2001: 0 49108ce06c: 0000: 00002001 00000000 50t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) 51108ce074: 0000: c0003b00 00001000 52t0 write UNKNOWN_20EF (20ef) 53 UNKNOWN_20EF: 0 54108ce07c: 0000: 000020ef 00000000 55t0 write RB_BLEND_RED (20f0) 56 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 57 RB_BLEND_RED_F32: 0.000000 58 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 59 RB_BLEND_GREEN_F32: 0.007813 60108ce084: 0000: 000320f0 00000000 00000000 00000000 3c0000ff 61t0 write UNKNOWN_2152 (2152) 62 UNKNOWN_2152: 0 63108ce098: 0000: 00002152 00000000 64t0 write UNKNOWN_2153 (2153) 65 UNKNOWN_2153: 0 66108ce0a0: 0000: 00002153 00000000 67t0 write UNKNOWN_2154 (2154) 68 UNKNOWN_2154: 0 69108ce0a8: 0000: 00002154 00000000 70t0 write UNKNOWN_2155 (2155) 71 UNKNOWN_2155: 0 72108ce0b0: 0000: 00002155 00000000 73t0 write UNKNOWN_2156 (2156) 74 UNKNOWN_2156: 0 75108ce0b8: 0000: 00002156 00000000 76t0 write UNKNOWN_2157 (2157) 77 UNKNOWN_2157: 0 78108ce0c0: 0000: 00002157 00000000 79t0 write UNKNOWN_21C3 (21c3) 80 UNKNOWN_21C3: 0x1d 81108ce0c8: 0000: 000021c3 0000001d 82t0 write PC_GS_PARAM (21e5) 83 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 84108ce0d0: 0000: 000021e5 00000000 85t0 write UNKNOWN_21E6 (21e6) 86 UNKNOWN_21E6: 0x1 87108ce0d8: 0000: 000021e6 00000001 88t0 write PC_HS_PARAM (21e7) 89 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 90108ce0e0: 0000: 000021e7 00000000 91t0 write UNKNOWN_22D7 (22d7) 92 UNKNOWN_22D7: 0 93108ce0e8: 0000: 000022d7 00000000 94t0 write TPL1_TP_TEX_OFFSET (2380) 95 TPL1_TP_TEX_OFFSET: 0 96108ce0f0: 0000: 00002380 00000000 97t0 write TPL1_TP_TEX_COUNT (2381) 98 TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 } 99108ce0f8: 0000: 00002381 00000010 100t0 write TPL1_TP_FS_TEX_COUNT (23a0) 101 TPL1_TP_FS_TEX_COUNT: 0x10 102108ce100: 0000: 000023a0 00000010 103t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) 104 { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } 105 { ADDR_LO = 0 } 106108ce108: 0000: c0014300 00040000 00000000 107t0 write SP_VS_PVT_MEM_PARAM (22e2) 108 SP_VS_PVT_MEM_PARAM: 0x8000001 109 SP_VS_PVT_MEM_ADDR: 0x10cd7000 110108ce114: 0000: 000122e2 08000001 10cd7000 111t0 write SP_FS_PVT_MEM_PARAM (22ec) 112 SP_FS_PVT_MEM_PARAM: 0x8000001 113 SP_FS_PVT_MEM_ADDR: 0x10cd9000 114108ce120: 0000: 000122ec 08000001 10cd9000 115t0 write GRAS_SC_CONTROL (207b) 116 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 117108ce12c: 0000: 0000207b 00000800 118t0 write RB_MSAA_CONTROL (20a2) 119 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 120108ce134: 0000: 000020a2 00001000 121t0 write GRAS_CL_GB_CLIP_ADJ (2004) 122 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } 123108ce13c: 0000: 00002004 00000000 124t0 write RB_ALPHA_CONTROL (20f8) 125 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } 126108ce144: 0000: 000020f8 00000e00 127t0 write RB_FS_OUTPUT (20f9) 128 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 129108ce14c: 0000: 000020f9 ffff0000 130t0 write GRAS_ALPHA_CONTROL (2073) 131 GRAS_ALPHA_CONTROL: { 0 } 132108ce154: 0000: 00002073 00000000 133t0 write VSC_BIN_SIZE (0c00) 134 VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 } 135108ce15c: 0000: 00000c00 0000014a 136t0 write VSC_SIZE_ADDRESS (0c01) 137 VSC_SIZE_ADDRESS: 0x10cdb000 138108ce164: 0000: 00000c01 10cdb000 139t0 write VSC_PIPE_CONFIG[0].REG (0c08) 140 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } 141 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 142 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 143 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 144 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 145 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 146 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 147 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 148108ce16c: 0000: 00070c08 01100000 00000000 00000000 00000000 00000000 00000000 00000000 149* 150t0 write VSC_PIPE_DATA_ADDRESS[0].REG (0c10) 151 VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000 152 VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000 153 VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000 154 VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000 155 VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000 156 VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000 157 VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000 158 VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000 159108ce190: 0000: 00070c10 10cdc000 10d1c000 10d5c000 10d9c000 10ddc000 10e1c000 10e5c000 160108ce1b0: 0020: 10e9c000 161t0 write VSC_PIPE_DATA_LENGTH[0].REG (0c18) 162 VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0 163 VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0 164 VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0 165 VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0 166 VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0 167 VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0 168 VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0 169 VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0 170108ce1b4: 0000: 00070c18 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 171108ce1d4: 0020: 0003ffe0 172t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 173108ce1d8: 0000: c0002600 00000000 174t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) 175 RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } 176108ce1e0: 0000: 00000ce0 012c012c 177t0 write RB_MODE_CONTROL (20a0) 178 RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM } 179108ce1e8: 0000: 000020a0 00010a0a 180t0 write RB_DEPTH_INFO (2103) 181 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 } 182 RB_DEPTH_PITCH: 1280 183 RB_DEPTH_PITCH2: 1280 184108ce1f0: 0000: 00022103 00064002 00000028 00000028 185t0 write RB_STENCIL_INFO (2108) 186 RB_STENCIL_INFO: { STENCIL_BASE = 0 } 187 RB_STENCIL_PITCH: 0 188108ce200: 0000: 00012108 00000000 00000000 189t0 write GRAS_DEPTH_CONTROL (2077) 190 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 } 191108ce20c: 0000: 00002077 00000002 192t0 write PC_VSTREAM_CONTROL (21c2) 193 PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 } 194108ce214: 0000: 000021c2 00000000 195t3 opcode: (null) (4c) (4 dwords) 196108ce21c: 0000: c0024c00 00000000 00000000 012b012b 197t0 write RB_MRT[0].BUF_INFO (20a5) 198 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 } 199 RB_MRT[0].BASE: 0 200 RB_MRT[0].CONTROL3: { STRIDE = 1280 } 201108ce22c: 0000: 000220a5 0014089a 00000000 00002800 202t0 write RB_MRT[0x1].BUF_INFO (20aa) 203 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 204 RB_MRT[0x1].BASE: 0 205 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } 206108ce23c: 0000: 000220aa 00000080 00000000 00000000 207t0 write RB_MRT[0x2].BUF_INFO (20af) 208 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 209 RB_MRT[0x2].BASE: 0 210 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } 211108ce24c: 0000: 000220af 00000080 00000000 00000000 212t0 write RB_MRT[0x3].BUF_INFO (20b4) 213 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 214 RB_MRT[0x3].BASE: 0 215 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } 216108ce25c: 0000: 000220b4 00000080 00000000 00000000 217t0 write RB_MRT[0x4].BUF_INFO (20b9) 218 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 219 RB_MRT[0x4].BASE: 0 220 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } 221108ce26c: 0000: 000220b9 00000080 00000000 00000000 222t0 write RB_MRT[0x5].BUF_INFO (20be) 223 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 224 RB_MRT[0x5].BASE: 0 225 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } 226108ce27c: 0000: 000220be 00000080 00000000 00000000 227t0 write RB_MRT[0x6].BUF_INFO (20c3) 228 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 229 RB_MRT[0x6].BASE: 0 230 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } 231108ce28c: 0000: 000220c3 00000080 00000000 00000000 232t0 write RB_MRT[0x7].BUF_INFO (20c8) 233 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 234 RB_MRT[0x7].BASE: 0 235 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } 236108ce29c: 0000: 000220c8 00000080 00000000 00000000 237t0 write RB_BIN_OFFSET (210d) 238 RB_BIN_OFFSET: { X = 0 | Y = 0 } 239108ce2ac: 0000: 0000210d 00000000 240t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) 241 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 242 GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } 243108ce2b4: 0000: 0001207c 00000000 012b012b 244t0 write RB_RENDER_CONTROL (20a1) 245 RB_RENDER_CONTROL: { 0x8 } 246108ce2c0: 0000: 000020a1 00000008 247t0 write CP_SCRATCH[0x6].REG (057e) 248 CP_SCRATCH[0x6].REG: 0x73 249 :0,0,115,0 250108ce2c8: 0000: 0000057e 00000073 251t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) 252 ibaddr:109ce000 253 ibsize:00000f2e 254t0 write CP_SCRATCH[0x5].REG (057d) 255 CP_SCRATCH[0x5].REG: 0x1 256 :0,1,115,0 257109ce000: 0000: 0000057d 00000001 258t0 write RB_RENDER_COMPONENTS (20fb) 259 RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 260109ce008: 0000: 000020fb 0000000f 261t0 write RB_ALPHA_CONTROL (20f8) 262 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } 263109ce010: 0000: 000020f8 00000000 264t0 write RB_STENCIL_CONTROL (2106) 265 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 266 RB_STENCIL_CONTROL2: { 0 } 267109ce018: 0000: 00012106 00000000 00000000 268t0 write RB_STENCILREFMASK (210b) 269 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 270 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 271109ce024: 0000: 0001210b 00000000 00000000 272t0 write RB_DEPTH_CONTROL (2101) 273 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE } 274109ce030: 0000: 00002101 80000076 275t0 write GRAS_ALPHA_CONTROL (2073) 276 GRAS_ALPHA_CONTROL: { 0 } 277109ce038: 0000: 00002073 00000000 278t0 write GRAS_SU_MODE_CONTROL (2078) 279 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS } 280109ce040: 0000: 00002078 00100004 281t0 write GRAS_SU_POINT_MINMAX (2070) 282 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 283 GRAS_SU_POINT_SIZE: 0.000000 284109ce048: 0000: 00012070 00000000 00000000 285t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 286 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 287 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 288 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 289109ce054: 0000: 00022074 00000000 00000000 00000000 290t0 write GRAS_CL_CLIP_CNTL (2000) 291 GRAS_CL_CLIP_CNTL: { 0x80000 } 292109ce064: 0000: 00002000 00080000 293t0 write PC_PRIM_VTX_CNTL (21c4) 294 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 295 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 296109ce06c: 0000: 000121c4 02000000 00000012 297t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 298 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 299 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 300109ce078: 0000: 0001209c 012b012b 00000000 301t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 302109ce084: 0000: c0002600 00000000 303t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) 304 GRAS_CL_VPORT_XOFFSET_0: 150.000000 305 GRAS_CL_VPORT_XSCALE_0: 150.000000 306 GRAS_CL_VPORT_YOFFSET_0: 150.000000 307 GRAS_CL_VPORT_YSCALE_0: -150.000000 308 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 309 GRAS_CL_VPORT_ZSCALE_0: 1.000000 310109ce08c: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000 311t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 312 RB_VPORT_Z_CLAMP[0].MIN: 0 313 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 314109ce0a8: 0000: 00012120 00000000 00ffffff 315t0 write HLSQ_UPDATE_CONTROL (23db) 316 HLSQ_UPDATE_CONTROL: 0x3 317109ce0b4: 0000: 000023db 00000003 318t0 write HLSQ_CONTROL_0_REG (23c0) 319 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 320 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 321 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 322 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 323 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 324109ce0bc: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 325t0 write HLSQ_VS_CONTROL_REG (23c5) 326 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 327 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 328 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 329 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 330 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 331109ce0d4: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200 332t0 write SP_SP_CTRL_REG (22c0) 333 SP_SP_CTRL_REG: { 0x140010 } 334109ce0ec: 0000: 000022c0 00140010 335t0 write SP_INSTR_CACHE_CTRL (22c1) 336 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 337109ce0f4: 0000: 000022c1 000005ff 338t0 write SP_VS_LENGTH_REG (22e5) 339 SP_VS_LENGTH_REG: 1 340109ce0fc: 0000: 000022e5 00000001 341t0 write SP_VS_CTRL_REG0 (22c4) 342 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 343 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 344 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } 345109ce104: 0000: 000222c4 00200400 04000042 0000fc00 346t0 write SP_VS_OBJ_OFFSET_REG (22e0) 347 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 348 SP_VS_OBJ_START: 0x1073c000 349109ce114: 0000: 000122e0 00000000 1073c000 350t0 write SP_FS_LENGTH_REG (22ef) 351 SP_FS_LENGTH_REG: 1 352109ce120: 0000: 000022ef 00000001 353t0 write SP_FS_CTRL_REG0 (22e8) 354 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 355 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } 356109ce128: 0000: 000122e8 00340400 8000003e 357t0 write SP_FS_OBJ_OFFSET_REG (22ea) 358 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 359 SP_FS_OBJ_START: 0x1073b000 360109ce134: 0000: 000122ea 7e420000 1073b000 361t0 write SP_HS_OBJ_OFFSET_REG (230d) 362 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 363109ce140: 0000: 0000230d 7e420000 364t0 write SP_DS_OBJ_OFFSET_REG (2334) 365 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 366109ce148: 0000: 00002334 7e420000 367t0 write SP_GS_OBJ_OFFSET_REG (235b) 368 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 369109ce150: 0000: 0000235b 7e420000 370t0 write GRAS_CNTL (2003) 371 GRAS_CNTL: { 0 } 372109ce158: 0000: 00002003 00000000 373t0 write RB_RENDER_CONTROL2 (20a3) 374 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 375109ce160: 0000: 000020a3 00000000 376t0 write RB_FS_OUTPUT_REG (2100) 377 RB_FS_OUTPUT_REG: { MRT = 1 } 378109ce168: 0000: 00002100 00000001 379t0 write SP_FS_OUTPUT_REG (22f0) 380 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 381109ce170: 0000: 000022f0 0000fc01 382t0 write SP_FS_MRT[0].REG (22f1) 383 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 384 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 385 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 386 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 387 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 388 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 389 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 390 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 391109ce178: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 392* 393t0 write VPC_ATTR (2140) 394 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 395 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 396109ce19c: 0000: 00012140 40001000 00000000 397t0 write VPC_VARYING_INTERP[0].MODE (2142) 398 VPC_VARYING_INTERP[0].MODE: 0 399 VPC_VARYING_INTERP[0x1].MODE: 0 400 VPC_VARYING_INTERP[0x2].MODE: 0 401 VPC_VARYING_INTERP[0x3].MODE: 0 402 VPC_VARYING_INTERP[0x4].MODE: 0 403 VPC_VARYING_INTERP[0x5].MODE: 0 404 VPC_VARYING_INTERP[0x6].MODE: 0 405 VPC_VARYING_INTERP[0x7].MODE: 0 406109ce1a8: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 407* 408t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 409 VPC_VARYING_PS_REPL[0].MODE: 0 410 VPC_VARYING_PS_REPL[0x1].MODE: 0 411 VPC_VARYING_PS_REPL[0x2].MODE: 0 412 VPC_VARYING_PS_REPL[0x3].MODE: 0 413 VPC_VARYING_PS_REPL[0x4].MODE: 0 414 VPC_VARYING_PS_REPL[0x5].MODE: 0 415 VPC_VARYING_PS_REPL[0x6].MODE: 0 416 VPC_VARYING_PS_REPL[0x7].MODE: 0 417109ce1cc: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 418* 419t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 420 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 421 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 422 :0:0000:0000[03000000x_00000000x] end 423 :0:0001:0001[00000000x_00000000x] nop 424 :0:0002:0002[00000000x_00000000x] nop 425 :0:0003:0003[00000000x_00000000x] nop 426 :0:0004:0004[00000000x_00000000x] nop 427 Register Stats: 428 - used (half): (cnt=0, max=0) 429 - used (full): (cnt=0, max=0) 430 - input (half): (cnt=0, max=0) 431 - input (full): (cnt=0, max=0) 432 - max const: 0 433 434 - output (half): (cnt=0, max=0) (estimated) 435 - output (full): (cnt=0, max=0) (estimated) 436 - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 last-baryf, 0 half, 0 full 437 - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 438 - shaderdb: 0 (ss), 0 (sy) 439109ce1f0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000 440* 441t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 442 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 443 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 444 :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x 445 :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y 446 :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z 447 :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w 448 :0:0004:0004[03000000x_00000000x] end 449 :0:0005:0005[00000000x_00000000x] nop 450 :0:0006:0006[00000000x_00000000x] nop 451 :0:0007:0007[00000000x_00000000x] nop 452 :0:0008:0008[00000000x_00000000x] nop 453 Register Stats: 454 - used (half): (cnt=0, max=0) 455 - used (full): 0-3 (cnt=4, max=3) 456 - input (half): (cnt=0, max=0) 457 - input (full): (cnt=0, max=0) 458 - max const: 3 459 460 - output (half): (cnt=0, max=0) (estimated) 461 - output (full): 0-3 (cnt=4, max=3) (estimated) 462 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 last-baryf, 0 half, 1 full 463 - shaderdb: 5 cat0, 4 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 464 - shaderdb: 0 (ss), 0 (sy) 465109ce27c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002 466109ce29c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000 467* 468t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) 469 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } 470 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 471109ce314: 0.000000 0.000000 0.000000 0.000000 -nan -nan 0.000000 0.000000 472109ce334: 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 473109ce314: 0000: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000405 00000000 474109ce334: 0020: 00000000 00000000 02070000 00000000 00000000 00000000 00000000 00000000 475109ce308: 0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 ffffffff 476109ce328: 0020: ffffffff 00000405 00000000 00000000 00000000 02070000 00000000 00000000 477* 478t0 write RB_MRT[0].CONTROL (20a4) 479 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 480109ce354: 0000: 000020a4 0f000c00 481t0 write RB_MRT[0].BLEND_CONTROL (20a8) 482 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 483109ce35c: 0000: 000020a8 00000000 484t0 write RB_MRT[0x1].CONTROL (20a9) 485 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 486109ce364: 0000: 000020a9 00000c00 487t0 write RB_MRT[0x1].BLEND_CONTROL (20ad) 488 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 489109ce36c: 0000: 000020ad 00000000 490t0 write RB_MRT[0x2].CONTROL (20ae) 491 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 492109ce374: 0000: 000020ae 00000c00 493t0 write RB_MRT[0x2].BLEND_CONTROL (20b2) 494 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 495109ce37c: 0000: 000020b2 00000000 496t0 write RB_MRT[0x3].CONTROL (20b3) 497 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 498109ce384: 0000: 000020b3 00000c00 499t0 write RB_MRT[0x3].BLEND_CONTROL (20b7) 500 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 501109ce38c: 0000: 000020b7 00000000 502t0 write RB_MRT[0x4].CONTROL (20b8) 503 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 504109ce394: 0000: 000020b8 00000c00 505t0 write RB_MRT[0x4].BLEND_CONTROL (20bc) 506 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 507109ce39c: 0000: 000020bc 00000000 508t0 write RB_MRT[0x5].CONTROL (20bd) 509 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 510109ce3a4: 0000: 000020bd 00000c00 511t0 write RB_MRT[0x5].BLEND_CONTROL (20c1) 512 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 513109ce3ac: 0000: 000020c1 00000000 514t0 write RB_MRT[0x6].CONTROL (20c2) 515 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 516109ce3b4: 0000: 000020c2 00000c00 517t0 write RB_MRT[0x6].BLEND_CONTROL (20c6) 518 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 519109ce3bc: 0000: 000020c6 00000000 520t0 write RB_MRT[0x7].CONTROL (20c7) 521 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 522109ce3c4: 0000: 000020c7 00000c00 523t0 write RB_MRT[0x7].BLEND_CONTROL (20cb) 524 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 525109ce3cc: 0000: 000020cb 00000000 526t0 write RB_FS_OUTPUT (20f9) 527 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } 528109ce3d4: 0000: 000020f9 ffff0100 529t0 write RB_BLEND_RED (20f0) 530 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 531 RB_BLEND_RED_F32: 0.000000 532 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 533 RB_BLEND_GREEN_F32: 0.000000 534 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 535 RB_BLEND_BLUE_F32: 0.000000 536 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 537 RB_BLEND_ALPHA_F32: 0.000000 538109ce3dc: 0000: 000720f0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 539* 540t0 write VFD_FETCH[0].INSTR_0 (220a) 541 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 542 VFD_FETCH[0].INSTR_1: 0x1074a000 543 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } 544 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 545109ce400: 0000: 0003220a 0000060b 1074a000 00001000 00000001 546t0 write VFD_DECODE[0].INSTR (228a) 547 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 548109ce414: 0000: 0000228a 2c0000df 549t0 write VFD_CONTROL_0 (2200) 550 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 551 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 552 VFD_CONTROL_2: 0 553 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 554 VFD_CONTROL_4: 0 555109ce41c: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 556t0 write UCHE_INVALIDATE0 (0e8a) 557 UCHE_INVALIDATE0: 0 558 UCHE_INVALIDATE1: 0x12 559109ce434: 0000: 00010e8a 00000000 00000012 560t0 write VFD_INDEX_OFFSET (2208) 561 VFD_INDEX_OFFSET: 0 562 UNKNOWN_2209: 0 563109ce440: 0000: 00012208 00000000 00000000 564t0 write PC_RESTART_INDEX (21c6) 565 PC_RESTART_INDEX: 0xffffffff 566109ce44c: 0000: 000021c6 ffffffff 567t0 write CP_SCRATCH[0x7].REG (057f) 568 CP_SCRATCH[0x7].REG: 0x2 569 :0,1,115,2 570109ce454: 0000: 0000057f 00000002 571t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) 572 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS } 573 { NUM_INSTANCES = 1 } 574 { NUM_INDICES = 2 } 575 draw[0] register values 576!+ 00000001 RBBM_PERFCTR_CTL: 0x1 577!+ 00000001 CP_SCRATCH[0x5].REG: 0x1 578 :0,1,115,2 579!+ 00000073 CP_SCRATCH[0x6].REG: 0x73 580 :0,1,115,2 581!+ 00000002 CP_SCRATCH[0x7].REG: 0x2 582 :0,1,115,2 583!+ 0000014a VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 } 584!+ 10cdb000 VSC_SIZE_ADDRESS: 0x10cdb000 585!+ 01100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } 586 + 00000000 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 587 + 00000000 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 588 + 00000000 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 589 + 00000000 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 590 + 00000000 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 591 + 00000000 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 592 + 00000000 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 593!+ 10cdc000 VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000 594!+ 10d1c000 VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000 595!+ 10d5c000 VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000 596!+ 10d9c000 VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000 597!+ 10ddc000 VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000 598!+ 10e1c000 VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000 599!+ 10e5c000 VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000 600!+ 10e9c000 VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000 601!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0 602!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0 603!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0 604!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0 605!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0 606!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0 607!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0 608!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0 609 + 00000000 GRAS_DEBUG_ECO_CONTROL: 0 610!+ 00000006 UNKNOWN_0CC5: 0x6 611 + 00000000 UNKNOWN_0CC6: 0 612!+ 012c012c RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } 613!+ 00000001 UNKNOWN_0D01: 0x1 614 + 00000000 HLSQ_MODE_CONTROL: 0 615 + 00000000 UNKNOWN_0E42: 0 616 + 00000000 UCHE_CACHE_MODE_CONTROL: 0 617 + 00000000 UCHE_INVALIDATE0: 0 618!+ 00000012 UCHE_INVALIDATE1: 0x12 619!+ 00000007 UCHE_CACHE_WAYS_VFD: 0x7 620!+ 00040000 UNKNOWN_0EC2: 0x40000 621!+ 00000006 SP_MODE_CONTROL: 0x6 622!+ 0000003a TPL1_TP_MODE_CONTROL: 0x3a 623!+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 624 + 00000000 UNKNOWN_2001: 0 625 + 00000000 GRAS_CNTL: { 0 } 626 + 00000000 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } 627!+ 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 628!+ 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 629!+ 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 630!+ c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 631 + 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 632!+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000 633 + 00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } 634 + 00000000 GRAS_SU_POINT_SIZE: 0.000000 635 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 636 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 637 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 638 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 639!+ 00000002 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 } 640!+ 00100004 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS } 641!+ 00000800 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 642 + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } 643!+ 012b012b GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } 644!+ 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 645 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 646!+ 00010a0a RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM } 647!+ 00000008 RB_RENDER_CONTROL: { 0x8 } 648!+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } 649 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 650!+ 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 651!+ 0014089a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 } 652 + 00000000 RB_MRT[0].BASE: 0 653!+ 00002800 RB_MRT[0].CONTROL3: { STRIDE = 1280 } 654 + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 655!+ 00000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 656!+ 00000080 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 657 + 00000000 RB_MRT[0x1].BASE: 0 658 + 00000000 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } 659 + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 660!+ 00000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 661!+ 00000080 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 662 + 00000000 RB_MRT[0x2].BASE: 0 663 + 00000000 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } 664 + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 665!+ 00000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 666!+ 00000080 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 667 + 00000000 RB_MRT[0x3].BASE: 0 668 + 00000000 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } 669 + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 670!+ 00000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 671!+ 00000080 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 672 + 00000000 RB_MRT[0x4].BASE: 0 673 + 00000000 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } 674 + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 675!+ 00000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 676!+ 00000080 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 677 + 00000000 RB_MRT[0x5].BASE: 0 678 + 00000000 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } 679 + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 680!+ 00000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 681!+ 00000080 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 682 + 00000000 RB_MRT[0x6].BASE: 0 683 + 00000000 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } 684 + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 685!+ 00000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } 686!+ 00000080 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } 687 + 00000000 RB_MRT[0x7].BASE: 0 688 + 00000000 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } 689 + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 690 + 00000000 UNKNOWN_20EF: 0 691 + 00000000 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 692 + 00000000 RB_BLEND_RED_F32: 0.000000 693 + 00000000 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 694 + 00000000 RB_BLEND_GREEN_F32: 0.000000 695 + 00000000 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 696 + 00000000 RB_BLEND_BLUE_F32: 0.000000 697 + 00000000 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } 698 + 00000000 RB_BLEND_ALPHA_F32: 0.000000 699 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } 700!+ ffff0100 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } 701!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } 702!+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 703!+ 80000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE } 704!+ 00064002 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 } 705!+ 00000028 RB_DEPTH_PITCH: 1280 706!+ 00000028 RB_DEPTH_PITCH2: 1280 707 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 708 + 00000000 RB_STENCIL_CONTROL2: { 0 } 709 + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } 710 + 00000000 RB_STENCIL_PITCH: 0 711 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 712 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 713 + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } 714 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 715!+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 716!+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 717 + 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 718 + 00000000 VPC_VARYING_INTERP[0].MODE: 0 719 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 720 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 721 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 722 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 723 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 724 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 725 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 726 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 727 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 728 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 729 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 730 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 731 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 732 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 733 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 734 + 00000000 UNKNOWN_2152: 0 735 + 00000000 UNKNOWN_2153: 0 736 + 00000000 UNKNOWN_2154: 0 737 + 00000000 UNKNOWN_2155: 0 738 + 00000000 UNKNOWN_2156: 0 739 + 00000000 UNKNOWN_2157: 0 740 + 00000000 PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 } 741!+ 0000001d UNKNOWN_21C3: 0x1d 742!+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 743!+ 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 744!+ ffffffff PC_RESTART_INDEX: 0xffffffff 745 + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } 746!+ 00000001 UNKNOWN_21E6: 0x1 747 + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } 748!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 749!+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 750 + 00000000 VFD_CONTROL_2: 0 751!+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 752 + 00000000 VFD_CONTROL_4: 0 753 + 00000000 VFD_INDEX_OFFSET: 0 754 + 00000000 UNKNOWN_2209: 0 755!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 756!+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000 757!+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } 758!+ 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 759!+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 760!+ 00140010 SP_SP_CTRL_REG: { 0x140010 } 761!+ 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 762!+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 763!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 764!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } 765 + 00000000 UNKNOWN_22D7: 0 766 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 767!+ 1073c000 SP_VS_OBJ_START: 0x1073c000 768!+ 08000001 SP_VS_PVT_MEM_PARAM: 0x8000001 769!+ 10cd7000 SP_VS_PVT_MEM_ADDR: 0x10cd7000 770!+ 00000001 SP_VS_LENGTH_REG: 1 771!+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 772!+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } 773!+ 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 774!+ 1073b000 SP_FS_OBJ_START: 0x1073b000 775!+ 08000001 SP_FS_PVT_MEM_PARAM: 0x8000001 776!+ 10cd9000 SP_FS_PVT_MEM_ADDR: 0x10cd9000 777!+ 00000001 SP_FS_LENGTH_REG: 1 778!+ 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 779!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 780 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 781 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 782 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 783 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 784 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 785 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 786 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 787!+ 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 788!+ 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 789!+ 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 790 + 00000000 TPL1_TP_TEX_OFFSET: 0 791!+ 00000010 TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 } 792!+ 00000010 TPL1_TP_FS_TEX_COUNT: 0x10 793!+ 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 794!+ fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 795!+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 796!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 797!+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 798!+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 799!+ 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 800!+ 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 801!+ 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 802!+ 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 803!+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 804109ce45c: 0000: c0023800 00000888 00000001 00000002 805t0 write CP_SCRATCH[0x7].REG (057f) 806 CP_SCRATCH[0x7].REG: 0x3 807 :0,1,115,3 808109ce46c: 0000: 0000057f 00000003 809t0 write CP_SCRATCH[0x5].REG (057d) 810 CP_SCRATCH[0x5].REG: 0x7 811 :0,7,115,3 812109ce474: 0000: 0000057d 00000007 813t0 write RB_ALPHA_CONTROL (20f8) 814 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } 815109ce47c: 0000: 000020f8 00000000 816t0 write RB_STENCIL_CONTROL (2106) 817 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 818 RB_STENCIL_CONTROL2: { 0 } 819109ce484: 0000: 00012106 00000000 00000000 820t0 write RB_STENCILREFMASK (210b) 821 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 822 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 823109ce490: 0000: 0001210b 00000000 00000000 824t0 write RB_DEPTH_CONTROL (2101) 825 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 826109ce49c: 0000: 00002101 80000016 827t0 write GRAS_ALPHA_CONTROL (2073) 828 GRAS_ALPHA_CONTROL: { 0 } 829109ce4a4: 0000: 00002073 00000000 830t0 write GRAS_SU_MODE_CONTROL (2078) 831 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 832109ce4ac: 0000: 00002078 00100012 833t0 write GRAS_SU_POINT_MINMAX (2070) 834 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 835 GRAS_SU_POINT_SIZE: 1.000000 836109ce4b4: 0000: 00012070 00100010 00000010 837t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 838 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 839 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 840 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 841109ce4c0: 0000: 00022074 00000000 00000000 00000000 842t0 write GRAS_CL_CLIP_CNTL (2000) 843 GRAS_CL_CLIP_CNTL: { 0x80000 } 844109ce4d0: 0000: 00002000 00080000 845t0 write PC_PRIM_VTX_CNTL (21c4) 846 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 847 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 848109ce4d8: 0000: 000121c4 02000001 00000012 849t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 850 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 851 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 852109ce4e4: 0000: 0001209c 012b012b 00000000 853t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 854109ce4f0: 0000: c0002600 00000000 855t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) 856 GRAS_CL_VPORT_XOFFSET_0: 150.000000 857 GRAS_CL_VPORT_XSCALE_0: 150.000000 858 GRAS_CL_VPORT_YOFFSET_0: 150.000000 859 GRAS_CL_VPORT_YSCALE_0: -150.000000 860 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 861 GRAS_CL_VPORT_ZSCALE_0: 0.500000 862109ce4f8: 0000: 00052008 43160000 43160000 43160000 c3160000 3f000000 3f000000 863t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 864 RB_VPORT_Z_CLAMP[0].MIN: 0 865 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 866109ce514: 0000: 00012120 00000000 00ffffff 867t0 write HLSQ_UPDATE_CONTROL (23db) 868 HLSQ_UPDATE_CONTROL: 0x3 869109ce520: 0000: 000023db 00000003 870t0 write HLSQ_CONTROL_0_REG (23c0) 871 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 872 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 873 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 874 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 875 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 876109ce528: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 877t0 write HLSQ_VS_CONTROL_REG (23c5) 878 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 879 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 880 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 881 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 882 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 883109ce540: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 884t0 write SP_SP_CTRL_REG (22c0) 885 SP_SP_CTRL_REG: { 0x140010 } 886109ce558: 0000: 000022c0 00140010 887t0 write SP_INSTR_CACHE_CTRL (22c1) 888 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 889109ce560: 0000: 000022c1 000005ff 890t0 write SP_VS_LENGTH_REG (22e5) 891 SP_VS_LENGTH_REG: 4 892109ce568: 0000: 000022e5 00000004 893t0 write SP_VS_CTRL_REG0 (22c4) 894 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 895 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 896 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 897109ce570: 0000: 000222c4 00201000 04000042 0010fc06 898t0 write SP_VS_OUT[0].REG (22c7) 899 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 900109ce580: 0000: 000022c7 00001e0a 901t0 write SP_VS_VPC_DST[0].REG (22d8) 902 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 903109ce588: 0000: 000022d8 08080808 904t0 write SP_VS_OBJ_OFFSET_REG (22e0) 905 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 906 SP_VS_OBJ_START: 0x10cd0000 907109ce590: 0000: 000122e0 00000000 10cd0000 908t0 write SP_FS_LENGTH_REG (22ef) 909 SP_FS_LENGTH_REG: 1 910109ce59c: 0000: 000022ef 00000001 911t0 write SP_FS_CTRL_REG0 (22e8) 912 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 913 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 914109ce5a4: 0000: 000122e8 00340402 8010003e 915t0 write SP_FS_OBJ_OFFSET_REG (22ea) 916 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 917 SP_FS_OBJ_START: 0x10cd2000 918109ce5b0: 0000: 000122ea 7e420000 10cd2000 919t0 write SP_HS_OBJ_OFFSET_REG (230d) 920 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 921109ce5bc: 0000: 0000230d 7e420000 922t0 write SP_DS_OBJ_OFFSET_REG (2334) 923 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 924109ce5c4: 0000: 00002334 7e420000 925t0 write SP_GS_OBJ_OFFSET_REG (235b) 926 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 927109ce5cc: 0000: 0000235b 7e420000 928t0 write GRAS_CNTL (2003) 929 GRAS_CNTL: { 0 } 930109ce5d4: 0000: 00002003 00000000 931t0 write RB_RENDER_CONTROL2 (20a3) 932 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 933109ce5dc: 0000: 000020a3 00000000 934t0 write RB_FS_OUTPUT_REG (2100) 935 RB_FS_OUTPUT_REG: { MRT = 1 } 936109ce5e4: 0000: 00002100 00000001 937t0 write SP_FS_OUTPUT_REG (22f0) 938 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 939109ce5ec: 0000: 000022f0 0000fc01 940t0 write SP_FS_MRT[0].REG (22f1) 941 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 942 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 943 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 944 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 945 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 946 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 947 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 948 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 949109ce5f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 950* 951t0 write VPC_ATTR (2140) 952 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 953 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 954109ce618: 0000: 00012140 42001004 00040400 955t0 write VPC_VARYING_INTERP[0].MODE (2142) 956 VPC_VARYING_INTERP[0].MODE: 0x55 957 VPC_VARYING_INTERP[0x1].MODE: 0 958 VPC_VARYING_INTERP[0x2].MODE: 0 959 VPC_VARYING_INTERP[0x3].MODE: 0 960 VPC_VARYING_INTERP[0x4].MODE: 0 961 VPC_VARYING_INTERP[0x5].MODE: 0 962 VPC_VARYING_INTERP[0x6].MODE: 0 963 VPC_VARYING_INTERP[0x7].MODE: 0 964109ce624: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 965* 966t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 967 VPC_VARYING_PS_REPL[0].MODE: 0 968 VPC_VARYING_PS_REPL[0x1].MODE: 0 969 VPC_VARYING_PS_REPL[0x2].MODE: 0 970 VPC_VARYING_PS_REPL[0x3].MODE: 0 971 VPC_VARYING_PS_REPL[0x4].MODE: 0 972 VPC_VARYING_PS_REPL[0x5].MODE: 0 973 VPC_VARYING_PS_REPL[0x6].MODE: 0 974 VPC_VARYING_PS_REPL[0x7].MODE: 0 975109ce648: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 976* 977t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 978 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 979 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 980 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 981 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 982 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 983 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 984 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 985 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 986 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x 987 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 988 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y 989 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 990 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 991 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 992 :0:0012:0012[00000000x_00000000x] nop 993 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x 994 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 995 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y 996 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 997 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z 998 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 999 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w 1000 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x 1001 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y 1002 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z 1003 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x 1004 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w 1005 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x 1006 :0:0026:0026[00000000x_00000000x] nop 1007 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x 1008 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z 1009 :0:0029:0029[00000200x_00000000x] (rpt2)nop 1010 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x 1011 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x 1012 :0:0032:0034[00000200x_00000000x] (rpt2)nop 1013 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y 1014 :0:0034:0038[00000000x_00000000x] nop 1015 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x 1016 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x 1017 :0:0037:0041[00000200x_00000000x] (rpt2)nop 1018 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y 1019 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x 1020 :0:0040:0046[00000200x_00000000x] (rpt2)nop 1021 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x 1022 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x 1023 :0:0043:0051[00000200x_00000000x] (rpt2)nop 1024 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x 1025 :0:0045:0055[00000200x_00000000x] (rpt2)nop 1026 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 1027 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x 1028 :0:0048:0060[00000100x_00000000x] (rpt1)nop 1029 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 1030 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y 1031 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z 1032 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w 1033 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y 1034 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z 1035 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x 1036 :0:0056:0069[03000000x_00000000x] end 1037 :0:0057:0070[00000000x_00000000x] nop 1038 :0:0058:0071[00000000x_00000000x] nop 1039 :0:0059:0072[00000000x_00000000x] nop 1040 :0:0060:0073[00000000x_00000000x] nop 1041 Register Stats: 1042 - used (half): (cnt=0, max=0) 1043 - used (full): 0-13 (cnt=14, max=13) 1044 - input (half): (cnt=0, max=0) 1045 - input (full): 2-5 (cnt=4, max=5) 1046 - max const: 52 1047 1048 - output (half): (cnt=0, max=0) (estimated) 1049 - output (full): 6-13 (cnt=8, max=13) (estimated) 1050 - shaderdb: 74 instructions, 27 nops, 47 non-nops, (61 instlen), 0 last-baryf, 0 half, 4 full 1051 - shaderdb: 28 cat0, 8 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 1052 - shaderdb: 1 (ss), 0 (sy) 1053109ce66c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 1054109ce68c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 1055109ce6ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 1056109ce6cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 1057109ce6ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a 1058109ce70c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 1059109ce72c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 1060109ce74c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 1061109ce76c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 1062109ce78c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 1063109ce7ac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 1064109ce7cc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 1065109ce7ec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 1066109ce80c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 1067109ce82c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 1068* 1069t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 1070 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 1071 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 1072 :0:0000:0000[00000000x_00000000x] nop 1073 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 1074 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 1075 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 1076 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 1077 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 1078 :0:0006:0006[03000000x_00000000x] end 1079 :0:0007:0007[00000000x_00000000x] nop 1080 :0:0008:0008[00000000x_00000000x] nop 1081 :0:0009:0009[00000000x_00000000x] nop 1082 :0:0010:0010[00000000x_00000000x] nop 1083 Register Stats: 1084 - used (half): (cnt=0, max=0) 1085 - used (full): 0-3 (cnt=4, max=3) 1086 - input (half): (cnt=0, max=0) 1087 - input (full): 0-3 (cnt=4, max=3) 1088 - max const: 0 1089 1090 - output (half): (cnt=0, max=0) (estimated) 1091 - output (full): (cnt=0, max=0) (estimated) 1092 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 1093 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 1094 - shaderdb: 1 (ss), 0 (sy) 1095109ce878: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 1096109ce898: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 1097109ce8b8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1098* 1099t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 1100 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 1101 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 1102109ce910: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 1103109ce930: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 1104109ce950: 0.000000 0.000000 1.000000 1.000000 0.160000 0.020000 0.000000 1.000000 1105109ce970: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 1106109ce990: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000 1107109ce9b0: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 1108109ce910: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 1109109ce930: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 1110109ce950: 0040: 00000000 00000000 3f800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000 1111109ce970: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 1112109ce990: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 1113109ce9b0: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 1114109ce904: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 1115109ce924: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 1116109ce944: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 3f800000 3f800000 3e23d70b 1117109ce964: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 1118109ce984: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd 1119109ce9a4: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000 1120109ce9c4: 00c0: 00000000 00000000 3f800000 1121t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 1122 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 1123 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 1124109ce9dc: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 1125109ce9dc: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 1126109ce9d0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 1127t0 write RB_MRT[0].CONTROL (20a4) 1128 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1129109ce9ec: 0000: 000020a4 0f000c00 1130t0 write RB_MRT[0].BLEND_CONTROL (20a8) 1131 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1132109ce9f4: 0000: 000020a8 00000000 1133t0 write RB_MRT[0x1].CONTROL (20a9) 1134 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1135109ce9fc: 0000: 000020a9 0f000c00 1136t0 write RB_MRT[0x1].BLEND_CONTROL (20ad) 1137 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1138109cea04: 0000: 000020ad 00000000 1139t0 write RB_MRT[0x2].CONTROL (20ae) 1140 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1141109cea0c: 0000: 000020ae 0f000c00 1142t0 write RB_MRT[0x2].BLEND_CONTROL (20b2) 1143 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1144109cea14: 0000: 000020b2 00000000 1145t0 write RB_MRT[0x3].CONTROL (20b3) 1146 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1147109cea1c: 0000: 000020b3 0f000c00 1148t0 write RB_MRT[0x3].BLEND_CONTROL (20b7) 1149 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1150109cea24: 0000: 000020b7 00000000 1151t0 write RB_MRT[0x4].CONTROL (20b8) 1152 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1153109cea2c: 0000: 000020b8 0f000c00 1154t0 write RB_MRT[0x4].BLEND_CONTROL (20bc) 1155 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1156109cea34: 0000: 000020bc 00000000 1157t0 write RB_MRT[0x5].CONTROL (20bd) 1158 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1159109cea3c: 0000: 000020bd 0f000c00 1160t0 write RB_MRT[0x5].BLEND_CONTROL (20c1) 1161 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1162109cea44: 0000: 000020c1 00000000 1163t0 write RB_MRT[0x6].CONTROL (20c2) 1164 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1165109cea4c: 0000: 000020c2 0f000c00 1166t0 write RB_MRT[0x6].BLEND_CONTROL (20c6) 1167 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1168109cea54: 0000: 000020c6 00000000 1169t0 write RB_MRT[0x7].CONTROL (20c7) 1170 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1171109cea5c: 0000: 000020c7 0f000c00 1172t0 write RB_MRT[0x7].BLEND_CONTROL (20cb) 1173 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1174109cea64: 0000: 000020cb 00000000 1175t0 write RB_FS_OUTPUT (20f9) 1176 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 1177109cea6c: 0000: 000020f9 ffff0000 1178t0 write VFD_FETCH[0].INSTR_0 (220a) 1179 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 1180 VFD_FETCH[0].INSTR_1: 0x107cb000 1181 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 1182 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 1183109cea74: 0000: 0003220a 0000060b 107cb000 00100000 00000001 1184t0 write VFD_DECODE[0].INSTR (228a) 1185 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 1186109cea88: 0000: 0000228a 2c0020df 1187t0 write VFD_CONTROL_0 (2200) 1188 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 1189 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 1190 VFD_CONTROL_2: 0 1191 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 1192 VFD_CONTROL_4: 0 1193109cea90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 1194t0 write UCHE_INVALIDATE0 (0e8a) 1195 UCHE_INVALIDATE0: 0 1196 UCHE_INVALIDATE1: 0x12 1197109ceaa8: 0000: 00010e8a 00000000 00000012 1198t0 write VFD_INDEX_OFFSET (2208) 1199 VFD_INDEX_OFFSET: 0 1200 UNKNOWN_2209: 0 1201109ceab4: 0000: 00012208 00000000 00000000 1202t0 write PC_RESTART_INDEX (21c6) 1203 PC_RESTART_INDEX: 0xffffffff 1204109ceac0: 0000: 000021c6 ffffffff 1205t0 write CP_SCRATCH[0x7].REG (057f) 1206 CP_SCRATCH[0x7].REG: 0x8 1207 :0,7,115,8 1208109ceac8: 0000: 0000057f 00000008 1209t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 1210 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 1211 { NUM_INSTANCES = 1 } 1212 { NUM_INDICES = 240 } 1213 { FIRST_INDX = 0 } 1214 { INDX_BASE = 0x10bd0000 } 1215 { INDX_SIZE = 480 } 1216 draw[1] register values 1217!+ 00000007 CP_SCRATCH[0x5].REG: 0x7 1218 :0,7,115,8 1219!+ 00000008 CP_SCRATCH[0x7].REG: 0x8 1220 :0,7,115,8 1221 + 00000000 UCHE_INVALIDATE0: 0 1222 + 00000012 UCHE_INVALIDATE1: 0x12 1223 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 1224 + 00000000 GRAS_CNTL: { 0 } 1225 + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 1226 + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 1227 + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 1228 + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 1229!+ 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 1230!+ 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 1231!+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 1232!+ 00000010 GRAS_SU_POINT_SIZE: 1.000000 1233 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 1234 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 1235 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 1236 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 1237!+ 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 1238 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 1239 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1240 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 1241 + 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1242 + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1243!+ 0f000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1244 + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1245!+ 0f000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1246 + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1247!+ 0f000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1248 + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1249!+ 0f000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1250 + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1251!+ 0f000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1252 + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1253!+ 0f000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1254 + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1255!+ 0f000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } 1256 + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } 1257 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } 1258!+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } 1259 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 1260!+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 1261 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 1262 + 00000000 RB_STENCIL_CONTROL2: { 0 } 1263 + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1264 + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } 1265 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 1266 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 1267!+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 1268!+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 1269!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 1270 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 1271 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 1272 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 1273 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 1274 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 1275 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 1276 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 1277 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 1278 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 1279 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 1280 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 1281 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 1282 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 1283 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 1284 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 1285!+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1286 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1287 + ffffffff PC_RESTART_INDEX: 0xffffffff 1288 + 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 1289 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 1290 + 00000000 VFD_CONTROL_2: 0 1291 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 1292 + 00000000 VFD_CONTROL_4: 0 1293 + 00000000 VFD_INDEX_OFFSET: 0 1294 + 00000000 UNKNOWN_2209: 0 1295 + 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 1296!+ 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 1297!+ 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 1298 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 1299!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 1300 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 1301 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 1302!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 1303 + 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 1304!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 1305!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 1306!+ 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 1307 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 1308!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 1309!+ 00000004 SP_VS_LENGTH_REG: 4 1310!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 1311!+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 1312 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1313!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 1314 + 00000001 SP_FS_LENGTH_REG: 1 1315 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 1316 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 1317 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 1318 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 1319 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 1320 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 1321 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 1322 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 1323 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 1324 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1325 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1326 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1327 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 1328 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 1329 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 1330 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 1331 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 1332!+ 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 1333 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 1334 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1335 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1336 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1337 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 1338109cead0: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0000 000001e0 1339t0 write CP_SCRATCH[0x7].REG (057f) 1340 CP_SCRATCH[0x7].REG: 0x9 1341 :0,7,115,9 1342109ceaec: 0000: 0000057f 00000009 1343t0 write CP_SCRATCH[0x5].REG (057d) 1344 CP_SCRATCH[0x5].REG: 0xd 1345 :0,13,115,9 1346109ceaf4: 0000: 0000057d 0000000d 1347t0 write PC_PRIM_VTX_CNTL (21c4) 1348 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1349 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1350109ceafc: 0000: 000121c4 02000001 00000012 1351t0 write VFD_INDEX_OFFSET (2208) 1352 VFD_INDEX_OFFSET: 0 1353 UNKNOWN_2209: 0 1354109ceb08: 0000: 00012208 00000000 00000000 1355t0 write PC_RESTART_INDEX (21c6) 1356 PC_RESTART_INDEX: 0xffffffff 1357109ceb14: 0000: 000021c6 ffffffff 1358t0 write CP_SCRATCH[0x7].REG (057f) 1359 CP_SCRATCH[0x7].REG: 0xe 1360 :0,13,115,14 1361109ceb1c: 0000: 0000057f 0000000e 1362t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 1363 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 1364 { NUM_INSTANCES = 1 } 1365 { NUM_INDICES = 120 } 1366 { FIRST_INDX = 0 } 1367 { INDX_BASE = 0x10bd01e0 } 1368 { INDX_SIZE = 240 } 1369 draw[2] register values 1370!+ 0000000d CP_SCRATCH[0x5].REG: 0xd 1371 :0,13,115,14 1372!+ 0000000e CP_SCRATCH[0x7].REG: 0xe 1373 :0,13,115,14 1374 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1375 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1376 + ffffffff PC_RESTART_INDEX: 0xffffffff 1377 + 00000000 VFD_INDEX_OFFSET: 0 1378 + 00000000 UNKNOWN_2209: 0 1379109ceb24: 0000: c0053800 00000404 00000001 00000078 00000000 10bd01e0 000000f0 1380t0 write CP_SCRATCH[0x7].REG (057f) 1381 CP_SCRATCH[0x7].REG: 0xf 1382 :0,13,115,15 1383109ceb40: 0000: 0000057f 0000000f 1384t0 write CP_SCRATCH[0x5].REG (057d) 1385 CP_SCRATCH[0x5].REG: 0x13 1386 :0,19,115,15 1387109ceb48: 0000: 0000057d 00000013 1388t0 write PC_PRIM_VTX_CNTL (21c4) 1389 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1390 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1391109ceb50: 0000: 000121c4 02000001 00000012 1392t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 1393109ceb5c: 0000: c0002600 00000000 1394t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 1395 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 1396 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 1397109ceb70: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 1398109ceb90: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 1399109cebb0: 0.000000 0.000000 -1.000000 1.000000 0.160000 0.020000 0.000000 1.000000 1400109cebd0: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 1401109cebf0: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000 1402109cec10: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 1403109ceb70: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 1404109ceb90: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 1405109cebb0: 0040: 00000000 00000000 bf800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000 1406109cebd0: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 1407109cebf0: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 1408109cec10: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 1409109ceb64: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 1410109ceb84: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 1411109ceba4: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 bf800000 3f800000 3e23d70b 1412109cebc4: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 1413109cebe4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd 1414109cec04: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000 1415109cec24: 00c0: 00000000 00000000 3f800000 1416t0 write VFD_INDEX_OFFSET (2208) 1417 VFD_INDEX_OFFSET: 0 1418 UNKNOWN_2209: 0 1419109cec30: 0000: 00012208 00000000 00000000 1420t0 write PC_RESTART_INDEX (21c6) 1421 PC_RESTART_INDEX: 0xffffffff 1422109cec3c: 0000: 000021c6 ffffffff 1423t0 write CP_SCRATCH[0x7].REG (057f) 1424 CP_SCRATCH[0x7].REG: 0x14 1425 :0,19,115,20 1426109cec44: 0000: 0000057f 00000014 1427t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 1428 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 1429 { NUM_INSTANCES = 1 } 1430 { NUM_INDICES = 240 } 1431 { FIRST_INDX = 0 } 1432 { INDX_BASE = 0x10bd02d0 } 1433 { INDX_SIZE = 480 } 1434 draw[3] register values 1435!+ 00000013 CP_SCRATCH[0x5].REG: 0x13 1436 :0,19,115,20 1437!+ 00000014 CP_SCRATCH[0x7].REG: 0x14 1438 :0,19,115,20 1439 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1440 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1441 + ffffffff PC_RESTART_INDEX: 0xffffffff 1442 + 00000000 VFD_INDEX_OFFSET: 0 1443 + 00000000 UNKNOWN_2209: 0 1444109cec4c: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd02d0 000001e0 1445t0 write CP_SCRATCH[0x7].REG (057f) 1446 CP_SCRATCH[0x7].REG: 0x15 1447 :0,19,115,21 1448109cec68: 0000: 0000057f 00000015 1449t0 write CP_SCRATCH[0x5].REG (057d) 1450 CP_SCRATCH[0x5].REG: 0x19 1451 :0,25,115,21 1452109cec70: 0000: 0000057d 00000019 1453t0 write PC_PRIM_VTX_CNTL (21c4) 1454 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1455 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1456109cec78: 0000: 000121c4 02000001 00000012 1457t0 write VFD_INDEX_OFFSET (2208) 1458 VFD_INDEX_OFFSET: 0 1459 UNKNOWN_2209: 0 1460109cec84: 0000: 00012208 00000000 00000000 1461t0 write PC_RESTART_INDEX (21c6) 1462 PC_RESTART_INDEX: 0xffffffff 1463109cec90: 0000: 000021c6 ffffffff 1464t0 write CP_SCRATCH[0x7].REG (057f) 1465 CP_SCRATCH[0x7].REG: 0x1a 1466 :0,25,115,26 1467109cec98: 0000: 0000057f 0000001a 1468t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 1469 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 1470 { NUM_INSTANCES = 1 } 1471 { NUM_INDICES = 120 } 1472 { FIRST_INDX = 0 } 1473 { INDX_BASE = 0x10bd04b0 } 1474 { INDX_SIZE = 240 } 1475 draw[4] register values 1476!+ 00000019 CP_SCRATCH[0x5].REG: 0x19 1477 :0,25,115,26 1478!+ 0000001a CP_SCRATCH[0x7].REG: 0x1a 1479 :0,25,115,26 1480 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1481 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1482 + ffffffff PC_RESTART_INDEX: 0xffffffff 1483 + 00000000 VFD_INDEX_OFFSET: 0 1484 + 00000000 UNKNOWN_2209: 0 1485109ceca0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd04b0 000000f0 1486t0 write CP_SCRATCH[0x7].REG (057f) 1487 CP_SCRATCH[0x7].REG: 0x1b 1488 :0,25,115,27 1489109cecbc: 0000: 0000057f 0000001b 1490t0 write CP_SCRATCH[0x5].REG (057d) 1491 CP_SCRATCH[0x5].REG: 0x1f 1492 :0,31,115,27 1493109cecc4: 0000: 0000057d 0000001f 1494t0 write RB_DEPTH_CONTROL (2101) 1495 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 1496109ceccc: 0000: 00002101 80000016 1497t0 write GRAS_ALPHA_CONTROL (2073) 1498 GRAS_ALPHA_CONTROL: { 0 } 1499109cecd4: 0000: 00002073 00000000 1500t0 write PC_PRIM_VTX_CNTL (21c4) 1501 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1502 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1503109cecdc: 0000: 000121c4 02000001 00000012 1504t0 write HLSQ_UPDATE_CONTROL (23db) 1505 HLSQ_UPDATE_CONTROL: 0x3 1506109cece8: 0000: 000023db 00000003 1507t0 write HLSQ_CONTROL_0_REG (23c0) 1508 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 1509 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 1510 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 1511 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 1512 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 1513109cecf0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 1514t0 write HLSQ_VS_CONTROL_REG (23c5) 1515 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 1516 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 1517 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1518 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1519 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1520109ced08: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 1521t0 write SP_SP_CTRL_REG (22c0) 1522 SP_SP_CTRL_REG: { 0x140010 } 1523109ced20: 0000: 000022c0 00140010 1524t0 write SP_INSTR_CACHE_CTRL (22c1) 1525 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 1526109ced28: 0000: 000022c1 000005ff 1527t0 write SP_VS_LENGTH_REG (22e5) 1528 SP_VS_LENGTH_REG: 4 1529109ced30: 0000: 000022e5 00000004 1530t0 write SP_VS_CTRL_REG0 (22c4) 1531 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 1532 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 1533 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 1534109ced38: 0000: 000222c4 00201400 08000042 0010fc0a 1535t0 write SP_VS_OUT[0].REG (22c7) 1536 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 1537109ced48: 0000: 000022c7 00001e0e 1538t0 write SP_VS_VPC_DST[0].REG (22d8) 1539 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 1540109ced50: 0000: 000022d8 08080808 1541t0 write SP_VS_OBJ_OFFSET_REG (22e0) 1542 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 1543 SP_VS_OBJ_START: 0x10cd5000 1544109ced58: 0000: 000122e0 00000000 10cd5000 1545t0 write SP_FS_LENGTH_REG (22ef) 1546 SP_FS_LENGTH_REG: 1 1547109ced64: 0000: 000022ef 00000001 1548t0 write SP_FS_CTRL_REG0 (22e8) 1549 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 1550 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 1551109ced6c: 0000: 000122e8 00340402 8010003e 1552t0 write SP_FS_OBJ_OFFSET_REG (22ea) 1553 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1554 SP_FS_OBJ_START: 0x10cd2000 1555109ced78: 0000: 000122ea 7e420000 10cd2000 1556t0 write SP_HS_OBJ_OFFSET_REG (230d) 1557 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1558109ced84: 0000: 0000230d 7e420000 1559t0 write SP_DS_OBJ_OFFSET_REG (2334) 1560 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1561109ced8c: 0000: 00002334 7e420000 1562t0 write SP_GS_OBJ_OFFSET_REG (235b) 1563 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1564109ced94: 0000: 0000235b 7e420000 1565t0 write GRAS_CNTL (2003) 1566 GRAS_CNTL: { 0 } 1567109ced9c: 0000: 00002003 00000000 1568t0 write RB_RENDER_CONTROL2 (20a3) 1569 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 1570109ceda4: 0000: 000020a3 00000000 1571t0 write RB_FS_OUTPUT_REG (2100) 1572 RB_FS_OUTPUT_REG: { MRT = 1 } 1573109cedac: 0000: 00002100 00000001 1574t0 write SP_FS_OUTPUT_REG (22f0) 1575 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 1576109cedb4: 0000: 000022f0 0000fc01 1577t0 write SP_FS_MRT[0].REG (22f1) 1578 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 1579 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 1580 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 1581 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 1582 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 1583 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 1584 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 1585 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 1586109cedbc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 1587* 1588t0 write VPC_ATTR (2140) 1589 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 1590 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 1591109cede0: 0000: 00012140 42001004 00040400 1592t0 write VPC_VARYING_INTERP[0].MODE (2142) 1593 VPC_VARYING_INTERP[0].MODE: 0x55 1594 VPC_VARYING_INTERP[0x1].MODE: 0 1595 VPC_VARYING_INTERP[0x2].MODE: 0 1596 VPC_VARYING_INTERP[0x3].MODE: 0 1597 VPC_VARYING_INTERP[0x4].MODE: 0 1598 VPC_VARYING_INTERP[0x5].MODE: 0 1599 VPC_VARYING_INTERP[0x6].MODE: 0 1600 VPC_VARYING_INTERP[0x7].MODE: 0 1601109cedec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 1602* 1603t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 1604 VPC_VARYING_PS_REPL[0].MODE: 0 1605 VPC_VARYING_PS_REPL[0x1].MODE: 0 1606 VPC_VARYING_PS_REPL[0x2].MODE: 0 1607 VPC_VARYING_PS_REPL[0x3].MODE: 0 1608 VPC_VARYING_PS_REPL[0x4].MODE: 0 1609 VPC_VARYING_PS_REPL[0x5].MODE: 0 1610 VPC_VARYING_PS_REPL[0x6].MODE: 0 1611 VPC_VARYING_PS_REPL[0x7].MODE: 0 1612109cee10: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1613* 1614t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 1615 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 1616 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 1617 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 1618 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 1619 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 1620 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 1621 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 1622 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 1623 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 1624 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 1625 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 1626 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 1627 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 1628 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 1629 :0:0012:0012[00000000x_00000000x] nop 1630 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 1631 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 1632 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 1633 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 1634 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 1635 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 1636 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 1637 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 1638 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 1639 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 1640 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 1641 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 1642 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 1643 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 1644 :0:0027:0027[00000200x_00000000x] (rpt2)nop 1645 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 1646 :0:0029:0031[00000000x_00000000x] nop 1647 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 1648 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 1649 :0:0032:0034[00000200x_00000000x] (rpt2)nop 1650 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 1651 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 1652 :0:0035:0039[00000200x_00000000x] (rpt2)nop 1653 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 1654 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 1655 :0:0038:0044[00000200x_00000000x] (rpt2)nop 1656 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 1657 :0:0040:0048[00000200x_00000000x] (rpt2)nop 1658 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 1659 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 1660 :0:0043:0053[00000100x_00000000x] (rpt1)nop 1661 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 1662 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 1663 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 1664 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 1665 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 1666 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 1667 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 1668 :0:0051:0062[03000000x_00000000x] end 1669 :0:0052:0063[00000000x_00000000x] nop 1670 :0:0053:0064[00000000x_00000000x] nop 1671 :0:0054:0065[00000000x_00000000x] nop 1672 :0:0055:0066[00000000x_00000000x] nop 1673 Register Stats: 1674 - used (half): (cnt=0, max=0) 1675 - used (full): 0-8 10-17 (cnt=17, max=17) 1676 - input (half): (cnt=0, max=0) 1677 - input (full): 2-8 (cnt=7, max=8) 1678 - max const: 52 1679 1680 - output (half): (cnt=0, max=0) (estimated) 1681 - output (full): 10-17 (cnt=8, max=17) (estimated) 1682 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 1683 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 1684 - shaderdb: 1 (ss), 0 (sy) 1685109cee34: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 1686109cee54: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 1687109cee74: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 1688109cee94: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 1689109ceeb4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 1690109ceed4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 1691109ceef4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 1692109cef14: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 1693109cef34: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 1694109cef54: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 1695109cef74: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 1696109cef94: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 1697109cefb4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 1698109cefd4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 1699* 1700t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 1701 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 1702 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 1703 :0:0000:0000[00000000x_00000000x] nop 1704 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 1705 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 1706 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 1707 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 1708 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 1709 :0:0006:0006[03000000x_00000000x] end 1710 :0:0007:0007[00000000x_00000000x] nop 1711 :0:0008:0008[00000000x_00000000x] nop 1712 :0:0009:0009[00000000x_00000000x] nop 1713 :0:0010:0010[00000000x_00000000x] nop 1714 Register Stats: 1715 - used (half): (cnt=0, max=0) 1716 - used (full): 0-3 (cnt=4, max=3) 1717 - input (half): (cnt=0, max=0) 1718 - input (full): 0-3 (cnt=4, max=3) 1719 - max const: 0 1720 1721 - output (half): (cnt=0, max=0) (estimated) 1722 - output (full): (cnt=0, max=0) (estimated) 1723 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 1724 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 1725 - shaderdb: 1 (ss), 0 (sy) 1726109cf040: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 1727109cf060: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 1728109cf080: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 1729* 1730t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 1731109cf0cc: 0000: c0002600 00000000 1732t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 1733 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 1734 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 1735109cf0e0: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 1736109cf100: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 1737109cf120: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000 1738109cf140: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 1739109cf160: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 1740109cf180: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 1741109cf0e0: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 1742109cf100: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 1743109cf120: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 1744109cf140: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 1745109cf160: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 1746109cf180: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 1747109cf0d4: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 1748109cf0f4: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 1749109cf114: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 1750109cf134: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 1751109cf154: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000 1752109cf174: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 1753109cf194: 00c0: 02020202 02020202 00000202 1754t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 1755 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 1756 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 1757109cf1ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 1758109cf1ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 1759109cf1a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 1760t0 write VFD_FETCH[0].INSTR_0 (220a) 1761 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 1762 VFD_FETCH[0].INSTR_1: 0x107cb000 1763 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 1764 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 1765109cf1bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 1766t0 write VFD_DECODE[0].INSTR (228a) 1767 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 1768109cf1d0: 0000: 0000228a 6c0020df 1769t0 write VFD_FETCH[0x1].INSTR_0 (220e) 1770 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 1771 VFD_FETCH[0x1].INSTR_1: 0x107cb00c 1772 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 1773 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 1774109cf1d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 1775t0 write VFD_DECODE[0x1].INSTR (228b) 1776 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 1777109cf1ec: 0000: 0000228b 2c0060df 1778t0 write VFD_CONTROL_0 (2200) 1779 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 1780 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 1781 VFD_CONTROL_2: 0 1782 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 1783 VFD_CONTROL_4: 0 1784109cf1f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 1785t0 write UCHE_INVALIDATE0 (0e8a) 1786 UCHE_INVALIDATE0: 0 1787 UCHE_INVALIDATE1: 0x12 1788109cf20c: 0000: 00010e8a 00000000 00000012 1789t0 write VFD_INDEX_OFFSET (2208) 1790 VFD_INDEX_OFFSET: 0 1791 UNKNOWN_2209: 0 1792109cf218: 0000: 00012208 00000000 00000000 1793t0 write PC_RESTART_INDEX (21c6) 1794 PC_RESTART_INDEX: 0xffffffff 1795109cf224: 0000: 000021c6 ffffffff 1796t0 write CP_SCRATCH[0x7].REG (057f) 1797 CP_SCRATCH[0x7].REG: 0x20 1798 :0,31,115,32 1799109cf22c: 0000: 0000057f 00000020 1800t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 1801 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 1802 { NUM_INSTANCES = 1 } 1803 { NUM_INDICES = 480 } 1804 { FIRST_INDX = 0 } 1805 { INDX_BASE = 0x10bd05a0 } 1806 { INDX_SIZE = 960 } 1807 draw[5] register values 1808!+ 0000001f CP_SCRATCH[0x5].REG: 0x1f 1809 :0,31,115,32 1810!+ 00000020 CP_SCRATCH[0x7].REG: 0x20 1811 :0,31,115,32 1812 + 00000000 UCHE_INVALIDATE0: 0 1813 + 00000012 UCHE_INVALIDATE1: 0x12 1814 + 00000000 GRAS_CNTL: { 0 } 1815 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 1816 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 1817 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 1818 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 1819 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 1820 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 1821 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 1822 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 1823 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 1824 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 1825 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 1826 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 1827 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 1828 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 1829 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 1830 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 1831 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 1832 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 1833 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 1834 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 1835 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 1836 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 1837 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1838 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1839 + ffffffff PC_RESTART_INDEX: 0xffffffff 1840!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 1841 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 1842 + 00000000 VFD_CONTROL_2: 0 1843 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 1844 + 00000000 VFD_CONTROL_4: 0 1845 + 00000000 VFD_INDEX_OFFSET: 0 1846 + 00000000 UNKNOWN_2209: 0 1847!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 1848 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 1849 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 1850 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 1851!+ 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 1852!+ 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c 1853!+ 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 1854!+ 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 1855!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 1856!+ 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 1857 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 1858 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 1859!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 1860!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 1861!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 1862!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 1863 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 1864 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 1865!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 1866 + 00000004 SP_VS_LENGTH_REG: 4 1867 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 1868 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 1869 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1870 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 1871 + 00000001 SP_FS_LENGTH_REG: 1 1872 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 1873 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 1874 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 1875 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 1876 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 1877 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 1878 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 1879 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 1880 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 1881 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1882 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1883 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1884 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 1885 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 1886 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 1887 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 1888 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 1889 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 1890 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 1891 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1892 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1893 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1894 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 1895109cf234: 0000: c0053800 00000404 00000001 000001e0 00000000 10bd05a0 000003c0 1896t0 write CP_SCRATCH[0x7].REG (057f) 1897 CP_SCRATCH[0x7].REG: 0x21 1898 :0,31,115,33 1899109cf250: 0000: 0000057f 00000021 1900t0 write CP_SCRATCH[0x5].REG (057d) 1901 CP_SCRATCH[0x5].REG: 0x25 1902 :0,37,115,33 1903109cf258: 0000: 0000057d 00000025 1904t0 write RB_DEPTH_CONTROL (2101) 1905 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 1906109cf260: 0000: 00002101 80000016 1907t0 write GRAS_ALPHA_CONTROL (2073) 1908 GRAS_ALPHA_CONTROL: { 0 } 1909109cf268: 0000: 00002073 00000000 1910t0 write GRAS_SU_MODE_CONTROL (2078) 1911 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 1912109cf270: 0000: 00002078 00100012 1913t0 write GRAS_SU_POINT_MINMAX (2070) 1914 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 1915 GRAS_SU_POINT_SIZE: 1.000000 1916109cf278: 0000: 00012070 00100010 00000010 1917t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 1918 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 1919 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 1920 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 1921109cf284: 0000: 00022074 00000000 00000000 00000000 1922t0 write GRAS_CL_CLIP_CNTL (2000) 1923 GRAS_CL_CLIP_CNTL: { 0x80000 } 1924109cf294: 0000: 00002000 00080000 1925t0 write PC_PRIM_VTX_CNTL (21c4) 1926 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 1927 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 1928109cf29c: 0000: 000121c4 02000001 00000012 1929t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 1930 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 1931 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 1932109cf2a8: 0000: 0001209c 012b012b 00000000 1933t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 1934 RB_VPORT_Z_CLAMP[0].MIN: 0 1935 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 1936109cf2b4: 0000: 00012120 00000000 00ffffff 1937t0 write HLSQ_UPDATE_CONTROL (23db) 1938 HLSQ_UPDATE_CONTROL: 0x3 1939109cf2c0: 0000: 000023db 00000003 1940t0 write HLSQ_CONTROL_0_REG (23c0) 1941 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 1942 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 1943 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 1944 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 1945 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 1946109cf2c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc 1947t0 write HLSQ_VS_CONTROL_REG (23c5) 1948 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 1949 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 1950 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1951 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1952 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 1953109cf2e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 1954t0 write SP_SP_CTRL_REG (22c0) 1955 SP_SP_CTRL_REG: { 0x140010 } 1956109cf2f8: 0000: 000022c0 00140010 1957t0 write SP_INSTR_CACHE_CTRL (22c1) 1958 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 1959109cf300: 0000: 000022c1 000005ff 1960t0 write SP_VS_LENGTH_REG (22e5) 1961 SP_VS_LENGTH_REG: 4 1962109cf308: 0000: 000022e5 00000004 1963t0 write SP_VS_CTRL_REG0 (22c4) 1964 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 1965 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 1966 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 1967109cf310: 0000: 000222c4 00201400 08000042 0010fc0a 1968t0 write SP_VS_OUT[0].REG (22c7) 1969 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 1970109cf320: 0000: 000022c7 00001e0e 1971t0 write SP_VS_VPC_DST[0].REG (22d8) 1972 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 1973109cf328: 0000: 000022d8 08080808 1974t0 write SP_VS_OBJ_OFFSET_REG (22e0) 1975 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 1976 SP_VS_OBJ_START: 0x10cd5000 1977109cf330: 0000: 000122e0 00000000 10cd5000 1978t0 write SP_FS_LENGTH_REG (22ef) 1979 SP_FS_LENGTH_REG: 1 1980109cf33c: 0000: 000022ef 00000001 1981t0 write SP_FS_CTRL_REG0 (22e8) 1982 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 1983 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 1984109cf344: 0000: 000122e8 00340802 8010003e 1985t0 write SP_FS_OBJ_OFFSET_REG (22ea) 1986 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1987 SP_FS_OBJ_START: 0x108cb000 1988109cf350: 0000: 000122ea 7e420000 108cb000 1989t0 write SP_HS_OBJ_OFFSET_REG (230d) 1990 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1991109cf35c: 0000: 0000230d 7e420000 1992t0 write SP_DS_OBJ_OFFSET_REG (2334) 1993 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1994109cf364: 0000: 00002334 7e420000 1995t0 write SP_GS_OBJ_OFFSET_REG (235b) 1996 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 1997109cf36c: 0000: 0000235b 7e420000 1998t0 write GRAS_CNTL (2003) 1999 GRAS_CNTL: { IJ_PERSP } 2000109cf374: 0000: 00002003 00000001 2001t0 write RB_RENDER_CONTROL2 (20a3) 2002 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 2003109cf37c: 0000: 000020a3 00001000 2004t0 write RB_FS_OUTPUT_REG (2100) 2005 RB_FS_OUTPUT_REG: { MRT = 1 } 2006109cf384: 0000: 00002100 00000001 2007t0 write SP_FS_OUTPUT_REG (22f0) 2008 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 2009109cf38c: 0000: 000022f0 0000fc01 2010t0 write SP_FS_MRT[0].REG (22f1) 2011 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 2012 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 2013 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 2014 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 2015 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 2016 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 2017 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 2018 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 2019109cf394: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 2020109cf3b4: 0020: 00000002 2021t0 write VPC_ATTR (2140) 2022 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 2023 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 2024109cf3b8: 0000: 00012140 42001004 00040400 2025t0 write VPC_VARYING_INTERP[0].MODE (2142) 2026 VPC_VARYING_INTERP[0].MODE: 0 2027 VPC_VARYING_INTERP[0x1].MODE: 0 2028 VPC_VARYING_INTERP[0x2].MODE: 0 2029 VPC_VARYING_INTERP[0x3].MODE: 0 2030 VPC_VARYING_INTERP[0x4].MODE: 0 2031 VPC_VARYING_INTERP[0x5].MODE: 0 2032 VPC_VARYING_INTERP[0x6].MODE: 0 2033 VPC_VARYING_INTERP[0x7].MODE: 0 2034109cf3c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2035* 2036t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 2037 VPC_VARYING_PS_REPL[0].MODE: 0 2038 VPC_VARYING_PS_REPL[0x1].MODE: 0 2039 VPC_VARYING_PS_REPL[0x2].MODE: 0 2040 VPC_VARYING_PS_REPL[0x3].MODE: 0 2041 VPC_VARYING_PS_REPL[0x4].MODE: 0 2042 VPC_VARYING_PS_REPL[0x5].MODE: 0 2043 VPC_VARYING_PS_REPL[0x6].MODE: 0 2044 VPC_VARYING_PS_REPL[0x7].MODE: 0 2045109cf3e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2046* 2047t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 2048 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 2049 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 2050 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 2051 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 2052 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 2053 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 2054 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 2055 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 2056 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 2057 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 2058 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 2059 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 2060 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 2061 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 2062 :0:0012:0012[00000000x_00000000x] nop 2063 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 2064 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 2065 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 2066 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 2067 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 2068 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 2069 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 2070 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 2071 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 2072 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 2073 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 2074 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 2075 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 2076 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 2077 :0:0027:0027[00000200x_00000000x] (rpt2)nop 2078 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 2079 :0:0029:0031[00000000x_00000000x] nop 2080 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 2081 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 2082 :0:0032:0034[00000200x_00000000x] (rpt2)nop 2083 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 2084 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 2085 :0:0035:0039[00000200x_00000000x] (rpt2)nop 2086 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 2087 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 2088 :0:0038:0044[00000200x_00000000x] (rpt2)nop 2089 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 2090 :0:0040:0048[00000200x_00000000x] (rpt2)nop 2091 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 2092 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 2093 :0:0043:0053[00000100x_00000000x] (rpt1)nop 2094 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 2095 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 2096 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 2097 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 2098 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 2099 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 2100 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 2101 :0:0051:0062[03000000x_00000000x] end 2102 :0:0052:0063[00000000x_00000000x] nop 2103 :0:0053:0064[00000000x_00000000x] nop 2104 :0:0054:0065[00000000x_00000000x] nop 2105 :0:0055:0066[00000000x_00000000x] nop 2106 Register Stats: 2107 - used (half): (cnt=0, max=0) 2108 - used (full): 0-8 10-17 (cnt=17, max=17) 2109 - input (half): (cnt=0, max=0) 2110 - input (full): 2-8 (cnt=7, max=8) 2111 - max const: 52 2112 2113 - output (half): (cnt=0, max=0) (estimated) 2114 - output (full): 10-17 (cnt=8, max=17) (estimated) 2115 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 2116 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 2117 - shaderdb: 1 (ss), 0 (sy) 2118109cf40c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 2119109cf42c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 2120109cf44c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 2121109cf46c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 2122109cf48c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 2123109cf4ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 2124109cf4cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 2125109cf4ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 2126109cf50c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 2127109cf52c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 2128109cf54c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 2129109cf56c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 2130109cf58c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 2131109cf5ac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 2132* 2133t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 2134 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 2135 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 2136 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x 2137 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x 2138 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x 2139 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x 2140 :0:0004:0004[03000000x_00000000x] end 2141 :0:0005:0005[00000000x_00000000x] nop 2142 :0:0006:0006[00000000x_00000000x] nop 2143 :0:0007:0007[00000000x_00000000x] nop 2144 :0:0008:0008[00000000x_00000000x] nop 2145 Register Stats: 2146 - used (half): (cnt=0, max=0) 2147 - used (full): 0 2-5 (cnt=5, max=5) 2148 - input (half): (cnt=0, max=0) 2149 - input (full): 0 (cnt=1, max=0) 2150 - max const: 0 2151 2152 - output (half): (cnt=0, max=0) (estimated) 2153 - output (full): 2-5 (cnt=4, max=5) (estimated) 2154 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full 2155 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 2156 - shaderdb: 0 (ss), 0 (sy) 2157109cf618: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 2158109cf638: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 2159* 2160t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 2161109cf6a4: 0000: c0002600 00000000 2162t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 2163 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 2164 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 2165109cf6b8: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 2166109cf6d8: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 2167109cf6f8: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000 2168109cf718: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 2169109cf738: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 2170109cf758: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 2171109cf6b8: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 2172109cf6d8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 2173109cf6f8: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 2174109cf718: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 2175109cf738: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 2176109cf758: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 2177109cf6ac: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 2178109cf6cc: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 2179109cf6ec: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 2180109cf70c: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 2181109cf72c: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000 2182109cf74c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 2183109cf76c: 00c0: 02020202 02020202 00000202 2184t0 write VFD_INDEX_OFFSET (2208) 2185 VFD_INDEX_OFFSET: 0 2186 UNKNOWN_2209: 0 2187109cf778: 0000: 00012208 00000000 00000000 2188t0 write PC_RESTART_INDEX (21c6) 2189 PC_RESTART_INDEX: 0xffffffff 2190109cf784: 0000: 000021c6 ffffffff 2191t0 write CP_SCRATCH[0x7].REG (057f) 2192 CP_SCRATCH[0x7].REG: 0x26 2193 :0,37,115,38 2194109cf78c: 0000: 0000057f 00000026 2195t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 2196 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 2197 { NUM_INSTANCES = 1 } 2198 { NUM_INDICES = 120 } 2199 { FIRST_INDX = 0 } 2200 { INDX_BASE = 0x10bd0960 } 2201 { INDX_SIZE = 240 } 2202 draw[6] register values 2203!+ 00000025 CP_SCRATCH[0x5].REG: 0x25 2204 :0,37,115,38 2205!+ 00000026 CP_SCRATCH[0x7].REG: 0x26 2206 :0,37,115,38 2207 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 2208!+ 00000001 GRAS_CNTL: { IJ_PERSP } 2209 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 2210 + 00000010 GRAS_SU_POINT_SIZE: 1.000000 2211 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 2212 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 2213 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 2214 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 2215 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 2216 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 2217 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2218!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 2219 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 2220 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 2221 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 2222 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 2223 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 2224 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 2225!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 2226 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 2227 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 2228 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 2229 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 2230 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 2231 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 2232 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 2233 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 2234 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 2235 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 2236 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 2237 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 2238 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 2239 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 2240 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 2241 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2242 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2243 + ffffffff PC_RESTART_INDEX: 0xffffffff 2244 + 00000000 VFD_INDEX_OFFSET: 0 2245 + 00000000 UNKNOWN_2209: 0 2246 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 2247 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 2248 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 2249 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 2250 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 2251 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 2252 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 2253 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 2254 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 2255 + 00000004 SP_VS_LENGTH_REG: 4 2256!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 2257 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 2258 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2259!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 2260 + 00000001 SP_FS_LENGTH_REG: 1 2261 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 2262!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 2263!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 2264!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 2265!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 2266!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 2267!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 2268!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 2269!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 2270 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2271 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2272 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2273 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 2274 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 2275 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 2276!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 2277 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 2278 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 2279 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 2280 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2281 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2282 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2283 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 2284109cf794: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0960 000000f0 2285t0 write CP_SCRATCH[0x7].REG (057f) 2286 CP_SCRATCH[0x7].REG: 0x27 2287 :0,37,115,39 2288109cf7b0: 0000: 0000057f 00000027 2289t0 write CP_SCRATCH[0x5].REG (057d) 2290 CP_SCRATCH[0x5].REG: 0x2b 2291 :0,43,115,39 2292109cf7b8: 0000: 0000057d 0000002b 2293t0 write RB_DEPTH_CONTROL (2101) 2294 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 2295109cf7c0: 0000: 00002101 80000016 2296t0 write GRAS_ALPHA_CONTROL (2073) 2297 GRAS_ALPHA_CONTROL: { 0 } 2298109cf7c8: 0000: 00002073 00000000 2299t0 write GRAS_SU_MODE_CONTROL (2078) 2300 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 2301109cf7d0: 0000: 00002078 00100012 2302t0 write GRAS_SU_POINT_MINMAX (2070) 2303 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 2304 GRAS_SU_POINT_SIZE: 1.000000 2305109cf7d8: 0000: 00012070 00100010 00000010 2306t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 2307 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 2308 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 2309 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 2310109cf7e4: 0000: 00022074 00000000 00000000 00000000 2311t0 write GRAS_CL_CLIP_CNTL (2000) 2312 GRAS_CL_CLIP_CNTL: { 0x80000 } 2313109cf7f4: 0000: 00002000 00080000 2314t0 write PC_PRIM_VTX_CNTL (21c4) 2315 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2316 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2317109cf7fc: 0000: 000121c4 02000001 00000012 2318t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 2319 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 2320 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2321109cf808: 0000: 0001209c 012b012b 00000000 2322t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 2323 RB_VPORT_Z_CLAMP[0].MIN: 0 2324 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 2325109cf814: 0000: 00012120 00000000 00ffffff 2326t0 write HLSQ_UPDATE_CONTROL (23db) 2327 HLSQ_UPDATE_CONTROL: 0x3 2328109cf820: 0000: 000023db 00000003 2329t0 write HLSQ_CONTROL_0_REG (23c0) 2330 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 2331 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 2332 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 2333 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 2334 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 2335109cf828: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 2336t0 write HLSQ_VS_CONTROL_REG (23c5) 2337 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 2338 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 2339 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2340 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2341 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2342109cf840: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 2343t0 write SP_SP_CTRL_REG (22c0) 2344 SP_SP_CTRL_REG: { 0x140010 } 2345109cf858: 0000: 000022c0 00140010 2346t0 write SP_INSTR_CACHE_CTRL (22c1) 2347 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 2348109cf860: 0000: 000022c1 000005ff 2349t0 write SP_VS_LENGTH_REG (22e5) 2350 SP_VS_LENGTH_REG: 4 2351109cf868: 0000: 000022e5 00000004 2352t0 write SP_VS_CTRL_REG0 (22c4) 2353 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 2354 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 2355 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 2356109cf870: 0000: 000222c4 00201000 04000042 0010fc06 2357t0 write SP_VS_OUT[0].REG (22c7) 2358 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 2359109cf880: 0000: 000022c7 00001e0a 2360t0 write SP_VS_VPC_DST[0].REG (22d8) 2361 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 2362109cf888: 0000: 000022d8 08080808 2363t0 write SP_VS_OBJ_OFFSET_REG (22e0) 2364 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 2365 SP_VS_OBJ_START: 0x10cd0000 2366109cf890: 0000: 000122e0 00000000 10cd0000 2367t0 write SP_FS_LENGTH_REG (22ef) 2368 SP_FS_LENGTH_REG: 1 2369109cf89c: 0000: 000022ef 00000001 2370t0 write SP_FS_CTRL_REG0 (22e8) 2371 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 2372 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 2373109cf8a4: 0000: 000122e8 00340402 8010003e 2374t0 write SP_FS_OBJ_OFFSET_REG (22ea) 2375 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2376 SP_FS_OBJ_START: 0x10cd2000 2377109cf8b0: 0000: 000122ea 7e420000 10cd2000 2378t0 write SP_HS_OBJ_OFFSET_REG (230d) 2379 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2380109cf8bc: 0000: 0000230d 7e420000 2381t0 write SP_DS_OBJ_OFFSET_REG (2334) 2382 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2383109cf8c4: 0000: 00002334 7e420000 2384t0 write SP_GS_OBJ_OFFSET_REG (235b) 2385 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2386109cf8cc: 0000: 0000235b 7e420000 2387t0 write GRAS_CNTL (2003) 2388 GRAS_CNTL: { 0 } 2389109cf8d4: 0000: 00002003 00000000 2390t0 write RB_RENDER_CONTROL2 (20a3) 2391 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 2392109cf8dc: 0000: 000020a3 00000000 2393t0 write RB_FS_OUTPUT_REG (2100) 2394 RB_FS_OUTPUT_REG: { MRT = 1 } 2395109cf8e4: 0000: 00002100 00000001 2396t0 write SP_FS_OUTPUT_REG (22f0) 2397 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 2398109cf8ec: 0000: 000022f0 0000fc01 2399t0 write SP_FS_MRT[0].REG (22f1) 2400 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 2401 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 2402 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 2403 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 2404 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 2405 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 2406 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 2407 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 2408109cf8f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 2409* 2410t0 write VPC_ATTR (2140) 2411 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 2412 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 2413109cf918: 0000: 00012140 42001004 00040400 2414t0 write VPC_VARYING_INTERP[0].MODE (2142) 2415 VPC_VARYING_INTERP[0].MODE: 0x55 2416 VPC_VARYING_INTERP[0x1].MODE: 0 2417 VPC_VARYING_INTERP[0x2].MODE: 0 2418 VPC_VARYING_INTERP[0x3].MODE: 0 2419 VPC_VARYING_INTERP[0x4].MODE: 0 2420 VPC_VARYING_INTERP[0x5].MODE: 0 2421 VPC_VARYING_INTERP[0x6].MODE: 0 2422 VPC_VARYING_INTERP[0x7].MODE: 0 2423109cf924: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 2424* 2425t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 2426 VPC_VARYING_PS_REPL[0].MODE: 0 2427 VPC_VARYING_PS_REPL[0x1].MODE: 0 2428 VPC_VARYING_PS_REPL[0x2].MODE: 0 2429 VPC_VARYING_PS_REPL[0x3].MODE: 0 2430 VPC_VARYING_PS_REPL[0x4].MODE: 0 2431 VPC_VARYING_PS_REPL[0x5].MODE: 0 2432 VPC_VARYING_PS_REPL[0x6].MODE: 0 2433 VPC_VARYING_PS_REPL[0x7].MODE: 0 2434109cf948: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2435* 2436t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 2437 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 2438 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 2439 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 2440 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 2441 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 2442 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 2443 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 2444 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 2445 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x 2446 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 2447 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y 2448 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 2449 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 2450 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 2451 :0:0012:0012[00000000x_00000000x] nop 2452 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x 2453 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 2454 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y 2455 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 2456 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z 2457 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 2458 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w 2459 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x 2460 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y 2461 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z 2462 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x 2463 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w 2464 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x 2465 :0:0026:0026[00000000x_00000000x] nop 2466 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x 2467 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z 2468 :0:0029:0029[00000200x_00000000x] (rpt2)nop 2469 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x 2470 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x 2471 :0:0032:0034[00000200x_00000000x] (rpt2)nop 2472 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y 2473 :0:0034:0038[00000000x_00000000x] nop 2474 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x 2475 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x 2476 :0:0037:0041[00000200x_00000000x] (rpt2)nop 2477 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y 2478 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x 2479 :0:0040:0046[00000200x_00000000x] (rpt2)nop 2480 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x 2481 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x 2482 :0:0043:0051[00000200x_00000000x] (rpt2)nop 2483 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x 2484 :0:0045:0055[00000200x_00000000x] (rpt2)nop 2485 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 2486 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x 2487 :0:0048:0060[00000100x_00000000x] (rpt1)nop 2488 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 2489 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y 2490 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z 2491 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w 2492 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y 2493 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z 2494 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x 2495 :0:0056:0069[03000000x_00000000x] end 2496 :0:0057:0070[00000000x_00000000x] nop 2497 :0:0058:0071[00000000x_00000000x] nop 2498 :0:0059:0072[00000000x_00000000x] nop 2499 :0:0060:0073[00000000x_00000000x] nop 2500 Register Stats: 2501 - used (half): (cnt=0, max=0) 2502 - used (full): 0-13 (cnt=14, max=13) 2503 - input (half): (cnt=0, max=0) 2504 - input (full): 2-5 (cnt=4, max=5) 2505 - max const: 52 2506 2507 - output (half): (cnt=0, max=0) (estimated) 2508 - output (full): 6-13 (cnt=8, max=13) (estimated) 2509 - shaderdb: 74 instructions, 27 nops, 47 non-nops, (61 instlen), 0 last-baryf, 0 half, 4 full 2510 - shaderdb: 28 cat0, 8 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 2511 - shaderdb: 1 (ss), 0 (sy) 2512109cf96c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 2513109cf98c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 2514109cf9ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 2515109cf9cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 2516109cf9ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a 2517109cfa0c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 2518109cfa2c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 2519109cfa4c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 2520109cfa6c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 2521109cfa8c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 2522109cfaac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 2523109cfacc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 2524109cfaec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 2525109cfb0c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 2526109cfb2c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 2527* 2528t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 2529 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 2530 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 2531 :0:0000:0000[00000000x_00000000x] nop 2532 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 2533 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 2534 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 2535 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 2536 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 2537 :0:0006:0006[03000000x_00000000x] end 2538 :0:0007:0007[00000000x_00000000x] nop 2539 :0:0008:0008[00000000x_00000000x] nop 2540 :0:0009:0009[00000000x_00000000x] nop 2541 :0:0010:0010[00000000x_00000000x] nop 2542 Register Stats: 2543 - used (half): (cnt=0, max=0) 2544 - used (full): 0-3 (cnt=4, max=3) 2545 - input (half): (cnt=0, max=0) 2546 - input (full): 0-3 (cnt=4, max=3) 2547 - max const: 0 2548 2549 - output (half): (cnt=0, max=0) (estimated) 2550 - output (full): (cnt=0, max=0) (estimated) 2551 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 2552 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 2553 - shaderdb: 1 (ss), 0 (sy) 2554109cfb78: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 2555109cfb98: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 2556109cfbb8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2557* 2558t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 2559109cfc04: 0000: c0002600 00000000 2560t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 2561 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 2562 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 2563109cfc18: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 2564109cfc38: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 2565109cfc58: 0.000000 0.000000 1.000000 1.000000 0.000000 0.160000 0.040000 1.000000 2566109cfc78: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 2567109cfc98: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000 2568109cfcb8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 2569109cfc18: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 2570109cfc38: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 2571109cfc58: 0040: 00000000 00000000 3f800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000 2572109cfc78: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 2573109cfc98: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 2574109cfcb8: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 2575109cfc0c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 2576109cfc2c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 2577109cfc4c: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 3f800000 3f800000 00000000 2578109cfc6c: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 2579109cfc8c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000 2580109cfcac: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000 2581109cfccc: 00c0: 00000000 00000000 3f800000 2582t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 2583 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 2584 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 2585109cfce4: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 2586109cfce4: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 2587109cfcd8: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 2588t0 write VFD_FETCH[0].INSTR_0 (220a) 2589 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 2590 VFD_FETCH[0].INSTR_1: 0x107cb000 2591 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 2592 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 2593109cfcf4: 0000: 0003220a 0000060b 107cb000 00100000 00000001 2594t0 write VFD_DECODE[0].INSTR (228a) 2595 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 2596109cfd08: 0000: 0000228a 2c0020df 2597t0 write VFD_CONTROL_0 (2200) 2598 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 2599 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 2600 VFD_CONTROL_2: 0 2601 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 2602 VFD_CONTROL_4: 0 2603109cfd10: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 2604t0 write UCHE_INVALIDATE0 (0e8a) 2605 UCHE_INVALIDATE0: 0 2606 UCHE_INVALIDATE1: 0x12 2607109cfd28: 0000: 00010e8a 00000000 00000012 2608t0 write VFD_INDEX_OFFSET (2208) 2609 VFD_INDEX_OFFSET: 0 2610 UNKNOWN_2209: 0 2611109cfd34: 0000: 00012208 00000000 00000000 2612t0 write PC_RESTART_INDEX (21c6) 2613 PC_RESTART_INDEX: 0xffffffff 2614109cfd40: 0000: 000021c6 ffffffff 2615t0 write CP_SCRATCH[0x7].REG (057f) 2616 CP_SCRATCH[0x7].REG: 0x2c 2617 :0,43,115,44 2618109cfd48: 0000: 0000057f 0000002c 2619t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 2620 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 2621 { NUM_INSTANCES = 1 } 2622 { NUM_INDICES = 120 } 2623 { FIRST_INDX = 0 } 2624 { INDX_BASE = 0x10bd0a50 } 2625 { INDX_SIZE = 240 } 2626 draw[7] register values 2627!+ 0000002b CP_SCRATCH[0x5].REG: 0x2b 2628 :0,43,115,44 2629!+ 0000002c CP_SCRATCH[0x7].REG: 0x2c 2630 :0,43,115,44 2631 + 00000000 UCHE_INVALIDATE0: 0 2632 + 00000012 UCHE_INVALIDATE1: 0x12 2633 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 2634!+ 00000000 GRAS_CNTL: { 0 } 2635 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 2636 + 00000010 GRAS_SU_POINT_SIZE: 1.000000 2637 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 2638 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 2639 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 2640 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 2641 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 2642 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 2643 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 2644!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 2645 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 2646 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 2647 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 2648 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 2649 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 2650 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 2651!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 2652 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 2653 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 2654 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 2655 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 2656 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 2657 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 2658 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 2659 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 2660 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 2661 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 2662 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 2663 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 2664 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 2665 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 2666 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 2667 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2668 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2669 + ffffffff PC_RESTART_INDEX: 0xffffffff 2670!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 2671 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 2672 + 00000000 VFD_CONTROL_2: 0 2673 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 2674 + 00000000 VFD_CONTROL_4: 0 2675 + 00000000 VFD_INDEX_OFFSET: 0 2676 + 00000000 UNKNOWN_2209: 0 2677!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 2678 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 2679 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 2680 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 2681!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 2682 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 2683 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 2684!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 2685!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 2686!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 2687!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 2688 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 2689 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 2690!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 2691 + 00000004 SP_VS_LENGTH_REG: 4 2692!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 2693 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 2694 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2695!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 2696 + 00000001 SP_FS_LENGTH_REG: 1 2697 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 2698!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 2699!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 2700!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 2701!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 2702!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 2703!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 2704!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 2705!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 2706 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2707 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2708 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2709 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 2710 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 2711 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 2712!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 2713 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 2714 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 2715 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 2716 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2717 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2718 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2719 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 2720109cfd50: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0a50 000000f0 2721t0 write CP_SCRATCH[0x7].REG (057f) 2722 CP_SCRATCH[0x7].REG: 0x2d 2723 :0,43,115,45 2724109cfd6c: 0000: 0000057f 0000002d 2725t0 write CP_SCRATCH[0x5].REG (057d) 2726 CP_SCRATCH[0x5].REG: 0x31 2727 :0,49,115,45 2728109cfd74: 0000: 0000057d 00000031 2729t0 write PC_PRIM_VTX_CNTL (21c4) 2730 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2731 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2732109cfd7c: 0000: 000121c4 02000001 00000012 2733t0 write VFD_INDEX_OFFSET (2208) 2734 VFD_INDEX_OFFSET: 0 2735 UNKNOWN_2209: 0 2736109cfd88: 0000: 00012208 00000000 00000000 2737t0 write PC_RESTART_INDEX (21c6) 2738 PC_RESTART_INDEX: 0xffffffff 2739109cfd94: 0000: 000021c6 ffffffff 2740t0 write CP_SCRATCH[0x7].REG (057f) 2741 CP_SCRATCH[0x7].REG: 0x32 2742 :0,49,115,50 2743109cfd9c: 0000: 0000057f 00000032 2744t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 2745 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 2746 { NUM_INSTANCES = 1 } 2747 { NUM_INDICES = 60 } 2748 { FIRST_INDX = 0 } 2749 { INDX_BASE = 0x10bd0b40 } 2750 { INDX_SIZE = 120 } 2751 draw[8] register values 2752!+ 00000031 CP_SCRATCH[0x5].REG: 0x31 2753 :0,49,115,50 2754!+ 00000032 CP_SCRATCH[0x7].REG: 0x32 2755 :0,49,115,50 2756 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2757 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2758 + ffffffff PC_RESTART_INDEX: 0xffffffff 2759 + 00000000 VFD_INDEX_OFFSET: 0 2760 + 00000000 UNKNOWN_2209: 0 2761109cfda4: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0b40 00000078 2762t0 write CP_SCRATCH[0x7].REG (057f) 2763 CP_SCRATCH[0x7].REG: 0x33 2764 :0,49,115,51 2765109cfdc0: 0000: 0000057f 00000033 2766t0 write CP_SCRATCH[0x5].REG (057d) 2767 CP_SCRATCH[0x5].REG: 0x37 2768 :0,55,115,51 2769109cfdc8: 0000: 0000057d 00000037 2770t0 write PC_PRIM_VTX_CNTL (21c4) 2771 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2772 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2773109cfdd0: 0000: 000121c4 02000001 00000012 2774t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 2775109cfddc: 0000: c0002600 00000000 2776t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 2777 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 2778 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 2779109cfdf0: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 2780109cfe10: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 2781109cfe30: 0.000000 0.000000 -1.000000 1.000000 0.000000 0.160000 0.040000 1.000000 2782109cfe50: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 2783109cfe70: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000 2784109cfe90: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 2785109cfdf0: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 2786109cfe10: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 2787109cfe30: 0040: 00000000 00000000 bf800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000 2788109cfe50: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 2789109cfe70: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 2790109cfe90: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 2791109cfde4: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 2792109cfe04: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 2793109cfe24: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 bf800000 3f800000 00000000 2794109cfe44: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 2795109cfe64: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000 2796109cfe84: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000 2797109cfea4: 00c0: 00000000 00000000 3f800000 2798t0 write VFD_INDEX_OFFSET (2208) 2799 VFD_INDEX_OFFSET: 0 2800 UNKNOWN_2209: 0 2801109cfeb0: 0000: 00012208 00000000 00000000 2802t0 write PC_RESTART_INDEX (21c6) 2803 PC_RESTART_INDEX: 0xffffffff 2804109cfebc: 0000: 000021c6 ffffffff 2805t0 write CP_SCRATCH[0x7].REG (057f) 2806 CP_SCRATCH[0x7].REG: 0x38 2807 :0,55,115,56 2808109cfec4: 0000: 0000057f 00000038 2809t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 2810 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 2811 { NUM_INSTANCES = 1 } 2812 { NUM_INDICES = 120 } 2813 { FIRST_INDX = 0 } 2814 { INDX_BASE = 0x10bd0bb8 } 2815 { INDX_SIZE = 240 } 2816 draw[9] register values 2817!+ 00000037 CP_SCRATCH[0x5].REG: 0x37 2818 :0,55,115,56 2819!+ 00000038 CP_SCRATCH[0x7].REG: 0x38 2820 :0,55,115,56 2821 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2822 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2823 + ffffffff PC_RESTART_INDEX: 0xffffffff 2824 + 00000000 VFD_INDEX_OFFSET: 0 2825 + 00000000 UNKNOWN_2209: 0 2826109cfecc: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0bb8 000000f0 2827t0 write CP_SCRATCH[0x7].REG (057f) 2828 CP_SCRATCH[0x7].REG: 0x39 2829 :0,55,115,57 2830109cfee8: 0000: 0000057f 00000039 2831t0 write CP_SCRATCH[0x5].REG (057d) 2832 CP_SCRATCH[0x5].REG: 0x3d 2833 :0,61,115,57 2834109cfef0: 0000: 0000057d 0000003d 2835t0 write PC_PRIM_VTX_CNTL (21c4) 2836 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2837 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2838109cfef8: 0000: 000121c4 02000001 00000012 2839t0 write VFD_INDEX_OFFSET (2208) 2840 VFD_INDEX_OFFSET: 0 2841 UNKNOWN_2209: 0 2842109cff04: 0000: 00012208 00000000 00000000 2843t0 write PC_RESTART_INDEX (21c6) 2844 PC_RESTART_INDEX: 0xffffffff 2845109cff10: 0000: 000021c6 ffffffff 2846t0 write CP_SCRATCH[0x7].REG (057f) 2847 CP_SCRATCH[0x7].REG: 0x3e 2848 :0,61,115,62 2849109cff18: 0000: 0000057f 0000003e 2850t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 2851 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 2852 { NUM_INSTANCES = 1 } 2853 { NUM_INDICES = 60 } 2854 { FIRST_INDX = 0 } 2855 { INDX_BASE = 0x10bd0ca8 } 2856 { INDX_SIZE = 120 } 2857 draw[10] register values 2858!+ 0000003d CP_SCRATCH[0x5].REG: 0x3d 2859 :0,61,115,62 2860!+ 0000003e CP_SCRATCH[0x7].REG: 0x3e 2861 :0,61,115,62 2862 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2863 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2864 + ffffffff PC_RESTART_INDEX: 0xffffffff 2865 + 00000000 VFD_INDEX_OFFSET: 0 2866 + 00000000 UNKNOWN_2209: 0 2867109cff20: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0ca8 00000078 2868t0 write CP_SCRATCH[0x7].REG (057f) 2869 CP_SCRATCH[0x7].REG: 0x3f 2870 :0,61,115,63 2871109cff3c: 0000: 0000057f 0000003f 2872t0 write CP_SCRATCH[0x5].REG (057d) 2873 CP_SCRATCH[0x5].REG: 0x43 2874 :0,67,115,63 2875109cff44: 0000: 0000057d 00000043 2876t0 write RB_DEPTH_CONTROL (2101) 2877 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 2878109cff4c: 0000: 00002101 80000016 2879t0 write GRAS_ALPHA_CONTROL (2073) 2880 GRAS_ALPHA_CONTROL: { 0 } 2881109cff54: 0000: 00002073 00000000 2882t0 write PC_PRIM_VTX_CNTL (21c4) 2883 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 2884 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 2885109cff5c: 0000: 000121c4 02000001 00000012 2886t0 write HLSQ_UPDATE_CONTROL (23db) 2887 HLSQ_UPDATE_CONTROL: 0x3 2888109cff68: 0000: 000023db 00000003 2889t0 write HLSQ_CONTROL_0_REG (23c0) 2890 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 2891 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 2892 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 2893 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 2894 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 2895109cff70: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 2896t0 write HLSQ_VS_CONTROL_REG (23c5) 2897 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 2898 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 2899 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2900 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2901 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 2902109cff88: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 2903t0 write SP_SP_CTRL_REG (22c0) 2904 SP_SP_CTRL_REG: { 0x140010 } 2905109cffa0: 0000: 000022c0 00140010 2906t0 write SP_INSTR_CACHE_CTRL (22c1) 2907 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 2908109cffa8: 0000: 000022c1 000005ff 2909t0 write SP_VS_LENGTH_REG (22e5) 2910 SP_VS_LENGTH_REG: 4 2911109cffb0: 0000: 000022e5 00000004 2912t0 write SP_VS_CTRL_REG0 (22c4) 2913 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 2914 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 2915 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 2916109cffb8: 0000: 000222c4 00201400 08000042 0010fc0a 2917t0 write SP_VS_OUT[0].REG (22c7) 2918 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 2919109cffc8: 0000: 000022c7 00001e0e 2920t0 write SP_VS_VPC_DST[0].REG (22d8) 2921 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 2922109cffd0: 0000: 000022d8 08080808 2923t0 write SP_VS_OBJ_OFFSET_REG (22e0) 2924 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 2925 SP_VS_OBJ_START: 0x10cd5000 2926109cffd8: 0000: 000122e0 00000000 10cd5000 2927t0 write SP_FS_LENGTH_REG (22ef) 2928 SP_FS_LENGTH_REG: 1 2929109cffe4: 0000: 000022ef 00000001 2930t0 write SP_FS_CTRL_REG0 (22e8) 2931 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 2932 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 2933109cffec: 0000: 000122e8 00340402 8010003e 2934t0 write SP_FS_OBJ_OFFSET_REG (22ea) 2935 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2936 SP_FS_OBJ_START: 0x10cd2000 2937109cfff8: 0000: 000122ea 7e420000 10cd2000 2938t0 write SP_HS_OBJ_OFFSET_REG (230d) 2939 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2940109d0004: 0000: 0000230d 7e420000 2941t0 write SP_DS_OBJ_OFFSET_REG (2334) 2942 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2943109d000c: 0000: 00002334 7e420000 2944t0 write SP_GS_OBJ_OFFSET_REG (235b) 2945 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 2946109d0014: 0000: 0000235b 7e420000 2947t0 write GRAS_CNTL (2003) 2948 GRAS_CNTL: { 0 } 2949109d001c: 0000: 00002003 00000000 2950t0 write RB_RENDER_CONTROL2 (20a3) 2951 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 2952109d0024: 0000: 000020a3 00000000 2953t0 write RB_FS_OUTPUT_REG (2100) 2954 RB_FS_OUTPUT_REG: { MRT = 1 } 2955109d002c: 0000: 00002100 00000001 2956t0 write SP_FS_OUTPUT_REG (22f0) 2957 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 2958109d0034: 0000: 000022f0 0000fc01 2959t0 write SP_FS_MRT[0].REG (22f1) 2960 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 2961 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 2962 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 2963 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 2964 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 2965 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 2966 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 2967 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 2968109d003c: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 2969* 2970t0 write VPC_ATTR (2140) 2971 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 2972 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 2973109d0060: 0000: 00012140 42001004 00040400 2974t0 write VPC_VARYING_INTERP[0].MODE (2142) 2975 VPC_VARYING_INTERP[0].MODE: 0x55 2976 VPC_VARYING_INTERP[0x1].MODE: 0 2977 VPC_VARYING_INTERP[0x2].MODE: 0 2978 VPC_VARYING_INTERP[0x3].MODE: 0 2979 VPC_VARYING_INTERP[0x4].MODE: 0 2980 VPC_VARYING_INTERP[0x5].MODE: 0 2981 VPC_VARYING_INTERP[0x6].MODE: 0 2982 VPC_VARYING_INTERP[0x7].MODE: 0 2983109d006c: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 2984* 2985t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 2986 VPC_VARYING_PS_REPL[0].MODE: 0 2987 VPC_VARYING_PS_REPL[0x1].MODE: 0 2988 VPC_VARYING_PS_REPL[0x2].MODE: 0 2989 VPC_VARYING_PS_REPL[0x3].MODE: 0 2990 VPC_VARYING_PS_REPL[0x4].MODE: 0 2991 VPC_VARYING_PS_REPL[0x5].MODE: 0 2992 VPC_VARYING_PS_REPL[0x6].MODE: 0 2993 VPC_VARYING_PS_REPL[0x7].MODE: 0 2994109d0090: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2995* 2996t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 2997 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 2998 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 2999 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 3000 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 3001 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 3002 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 3003 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 3004 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 3005 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 3006 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 3007 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 3008 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 3009 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 3010 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 3011 :0:0012:0012[00000000x_00000000x] nop 3012 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 3013 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 3014 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 3015 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 3016 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 3017 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 3018 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 3019 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 3020 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 3021 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 3022 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 3023 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 3024 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 3025 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 3026 :0:0027:0027[00000200x_00000000x] (rpt2)nop 3027 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 3028 :0:0029:0031[00000000x_00000000x] nop 3029 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 3030 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 3031 :0:0032:0034[00000200x_00000000x] (rpt2)nop 3032 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 3033 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 3034 :0:0035:0039[00000200x_00000000x] (rpt2)nop 3035 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 3036 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 3037 :0:0038:0044[00000200x_00000000x] (rpt2)nop 3038 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 3039 :0:0040:0048[00000200x_00000000x] (rpt2)nop 3040 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 3041 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 3042 :0:0043:0053[00000100x_00000000x] (rpt1)nop 3043 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 3044 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 3045 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 3046 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 3047 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 3048 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 3049 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 3050 :0:0051:0062[03000000x_00000000x] end 3051 :0:0052:0063[00000000x_00000000x] nop 3052 :0:0053:0064[00000000x_00000000x] nop 3053 :0:0054:0065[00000000x_00000000x] nop 3054 :0:0055:0066[00000000x_00000000x] nop 3055 Register Stats: 3056 - used (half): (cnt=0, max=0) 3057 - used (full): 0-8 10-17 (cnt=17, max=17) 3058 - input (half): (cnt=0, max=0) 3059 - input (full): 2-8 (cnt=7, max=8) 3060 - max const: 52 3061 3062 - output (half): (cnt=0, max=0) (estimated) 3063 - output (full): 10-17 (cnt=8, max=17) (estimated) 3064 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 3065 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 3066 - shaderdb: 1 (ss), 0 (sy) 3067109d00b4: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 3068109d00d4: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 3069109d00f4: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 3070109d0114: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 3071109d0134: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 3072109d0154: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 3073109d0174: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 3074109d0194: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 3075109d01b4: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 3076109d01d4: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 3077109d01f4: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 3078109d0214: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 3079109d0234: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 3080109d0254: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 3081* 3082t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 3083 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 3084 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 3085 :0:0000:0000[00000000x_00000000x] nop 3086 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 3087 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 3088 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 3089 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 3090 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 3091 :0:0006:0006[03000000x_00000000x] end 3092 :0:0007:0007[00000000x_00000000x] nop 3093 :0:0008:0008[00000000x_00000000x] nop 3094 :0:0009:0009[00000000x_00000000x] nop 3095 :0:0010:0010[00000000x_00000000x] nop 3096 Register Stats: 3097 - used (half): (cnt=0, max=0) 3098 - used (full): 0-3 (cnt=4, max=3) 3099 - input (half): (cnt=0, max=0) 3100 - input (full): 0-3 (cnt=4, max=3) 3101 - max const: 0 3102 3103 - output (half): (cnt=0, max=0) (estimated) 3104 - output (full): (cnt=0, max=0) (estimated) 3105 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 3106 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 3107 - shaderdb: 1 (ss), 0 (sy) 3108109d02c0: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 3109109d02e0: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 3110109d0300: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3111* 3112t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 3113109d034c: 0000: c0002600 00000000 3114t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 3115 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 3116 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 3117109d0360: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 3118109d0380: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 3119109d03a0: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000 3120109d03c0: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 3121109d03e0: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000 3122109d0400: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 3123109d0360: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 3124109d0380: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 3125109d03a0: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3126109d03c0: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3127109d03e0: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 3128109d0400: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 3129109d0354: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 3130109d0374: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 3131109d0394: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3132109d03b4: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 3133109d03d4: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 3134109d03f4: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 3135109d0414: 00c0: 02020202 02020202 00000202 3136t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 3137 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 3138 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 3139109d042c: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 3140109d042c: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 3141109d0420: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 3142t0 write VFD_FETCH[0].INSTR_0 (220a) 3143 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 3144 VFD_FETCH[0].INSTR_1: 0x107cb000 3145 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 3146 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 3147109d043c: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 3148t0 write VFD_DECODE[0].INSTR (228a) 3149 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 3150109d0450: 0000: 0000228a 6c0020df 3151t0 write VFD_FETCH[0x1].INSTR_0 (220e) 3152 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 3153 VFD_FETCH[0x1].INSTR_1: 0x107cb00c 3154 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 3155 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 3156109d0458: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 3157t0 write VFD_DECODE[0x1].INSTR (228b) 3158 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 3159109d046c: 0000: 0000228b 2c0060df 3160t0 write VFD_CONTROL_0 (2200) 3161 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 3162 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 3163 VFD_CONTROL_2: 0 3164 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 3165 VFD_CONTROL_4: 0 3166109d0474: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 3167t0 write UCHE_INVALIDATE0 (0e8a) 3168 UCHE_INVALIDATE0: 0 3169 UCHE_INVALIDATE1: 0x12 3170109d048c: 0000: 00010e8a 00000000 00000012 3171t0 write VFD_INDEX_OFFSET (2208) 3172 VFD_INDEX_OFFSET: 0 3173 UNKNOWN_2209: 0 3174109d0498: 0000: 00012208 00000000 00000000 3175t0 write PC_RESTART_INDEX (21c6) 3176 PC_RESTART_INDEX: 0xffffffff 3177109d04a4: 0000: 000021c6 ffffffff 3178t0 write CP_SCRATCH[0x7].REG (057f) 3179 CP_SCRATCH[0x7].REG: 0x44 3180 :0,67,115,68 3181109d04ac: 0000: 0000057f 00000044 3182t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 3183 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 3184 { NUM_INSTANCES = 1 } 3185 { NUM_INDICES = 240 } 3186 { FIRST_INDX = 0 } 3187 { INDX_BASE = 0x10bd0d20 } 3188 { INDX_SIZE = 480 } 3189 draw[11] register values 3190!+ 00000043 CP_SCRATCH[0x5].REG: 0x43 3191 :0,67,115,68 3192!+ 00000044 CP_SCRATCH[0x7].REG: 0x44 3193 :0,67,115,68 3194 + 00000000 UCHE_INVALIDATE0: 0 3195 + 00000012 UCHE_INVALIDATE1: 0x12 3196 + 00000000 GRAS_CNTL: { 0 } 3197 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 3198 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 3199 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 3200 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 3201 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 3202 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 3203 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 3204 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 3205 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 3206 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 3207 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 3208 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 3209 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 3210 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 3211 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 3212 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 3213 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 3214 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 3215 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 3216 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 3217 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 3218 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 3219 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 3220 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 3221 + ffffffff PC_RESTART_INDEX: 0xffffffff 3222!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 3223 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 3224 + 00000000 VFD_CONTROL_2: 0 3225 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 3226 + 00000000 VFD_CONTROL_4: 0 3227 + 00000000 VFD_INDEX_OFFSET: 0 3228 + 00000000 UNKNOWN_2209: 0 3229!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 3230 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 3231 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 3232 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 3233 + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 3234 + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c 3235 + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 3236 + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 3237!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 3238 + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 3239 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 3240 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 3241!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 3242!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 3243!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 3244!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 3245 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 3246 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 3247!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 3248 + 00000004 SP_VS_LENGTH_REG: 4 3249 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 3250 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 3251 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3252 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 3253 + 00000001 SP_FS_LENGTH_REG: 1 3254 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 3255 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 3256 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 3257 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 3258 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 3259 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 3260 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 3261 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 3262 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 3263 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3264 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3265 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3266 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 3267 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 3268 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 3269 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 3270 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 3271 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 3272 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 3273 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3274 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3275 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3276 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 3277109d04b4: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0d20 000001e0 3278t0 write CP_SCRATCH[0x7].REG (057f) 3279 CP_SCRATCH[0x7].REG: 0x45 3280 :0,67,115,69 3281109d04d0: 0000: 0000057f 00000045 3282t0 write CP_SCRATCH[0x5].REG (057d) 3283 CP_SCRATCH[0x5].REG: 0x49 3284 :0,73,115,69 3285109d04d8: 0000: 0000057d 00000049 3286t0 write RB_DEPTH_CONTROL (2101) 3287 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 3288109d04e0: 0000: 00002101 80000016 3289t0 write GRAS_ALPHA_CONTROL (2073) 3290 GRAS_ALPHA_CONTROL: { 0 } 3291109d04e8: 0000: 00002073 00000000 3292t0 write GRAS_SU_MODE_CONTROL (2078) 3293 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 3294109d04f0: 0000: 00002078 00100012 3295t0 write GRAS_SU_POINT_MINMAX (2070) 3296 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 3297 GRAS_SU_POINT_SIZE: 1.000000 3298109d04f8: 0000: 00012070 00100010 00000010 3299t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 3300 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 3301 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 3302 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 3303109d0504: 0000: 00022074 00000000 00000000 00000000 3304t0 write GRAS_CL_CLIP_CNTL (2000) 3305 GRAS_CL_CLIP_CNTL: { 0x80000 } 3306109d0514: 0000: 00002000 00080000 3307t0 write PC_PRIM_VTX_CNTL (21c4) 3308 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 3309 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 3310109d051c: 0000: 000121c4 02000001 00000012 3311t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 3312 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 3313 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3314109d0528: 0000: 0001209c 012b012b 00000000 3315t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 3316 RB_VPORT_Z_CLAMP[0].MIN: 0 3317 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 3318109d0534: 0000: 00012120 00000000 00ffffff 3319t0 write HLSQ_UPDATE_CONTROL (23db) 3320 HLSQ_UPDATE_CONTROL: 0x3 3321109d0540: 0000: 000023db 00000003 3322t0 write HLSQ_CONTROL_0_REG (23c0) 3323 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 3324 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 3325 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 3326 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 3327 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 3328109d0548: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc 3329t0 write HLSQ_VS_CONTROL_REG (23c5) 3330 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 3331 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 3332 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3333 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3334 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3335109d0560: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 3336t0 write SP_SP_CTRL_REG (22c0) 3337 SP_SP_CTRL_REG: { 0x140010 } 3338109d0578: 0000: 000022c0 00140010 3339t0 write SP_INSTR_CACHE_CTRL (22c1) 3340 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 3341109d0580: 0000: 000022c1 000005ff 3342t0 write SP_VS_LENGTH_REG (22e5) 3343 SP_VS_LENGTH_REG: 4 3344109d0588: 0000: 000022e5 00000004 3345t0 write SP_VS_CTRL_REG0 (22c4) 3346 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 3347 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 3348 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 3349109d0590: 0000: 000222c4 00201400 08000042 0010fc0a 3350t0 write SP_VS_OUT[0].REG (22c7) 3351 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 3352109d05a0: 0000: 000022c7 00001e0e 3353t0 write SP_VS_VPC_DST[0].REG (22d8) 3354 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 3355109d05a8: 0000: 000022d8 08080808 3356t0 write SP_VS_OBJ_OFFSET_REG (22e0) 3357 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 3358 SP_VS_OBJ_START: 0x10cd5000 3359109d05b0: 0000: 000122e0 00000000 10cd5000 3360t0 write SP_FS_LENGTH_REG (22ef) 3361 SP_FS_LENGTH_REG: 1 3362109d05bc: 0000: 000022ef 00000001 3363t0 write SP_FS_CTRL_REG0 (22e8) 3364 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 3365 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 3366109d05c4: 0000: 000122e8 00340802 8010003e 3367t0 write SP_FS_OBJ_OFFSET_REG (22ea) 3368 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3369 SP_FS_OBJ_START: 0x108cb000 3370109d05d0: 0000: 000122ea 7e420000 108cb000 3371t0 write SP_HS_OBJ_OFFSET_REG (230d) 3372 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3373109d05dc: 0000: 0000230d 7e420000 3374t0 write SP_DS_OBJ_OFFSET_REG (2334) 3375 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3376109d05e4: 0000: 00002334 7e420000 3377t0 write SP_GS_OBJ_OFFSET_REG (235b) 3378 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3379109d05ec: 0000: 0000235b 7e420000 3380t0 write GRAS_CNTL (2003) 3381 GRAS_CNTL: { IJ_PERSP } 3382109d05f4: 0000: 00002003 00000001 3383t0 write RB_RENDER_CONTROL2 (20a3) 3384 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 3385109d05fc: 0000: 000020a3 00001000 3386t0 write RB_FS_OUTPUT_REG (2100) 3387 RB_FS_OUTPUT_REG: { MRT = 1 } 3388109d0604: 0000: 00002100 00000001 3389t0 write SP_FS_OUTPUT_REG (22f0) 3390 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 3391109d060c: 0000: 000022f0 0000fc01 3392t0 write SP_FS_MRT[0].REG (22f1) 3393 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 3394 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 3395 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 3396 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 3397 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 3398 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 3399 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 3400 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 3401109d0614: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 3402109d0634: 0020: 00000002 3403t0 write VPC_ATTR (2140) 3404 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 3405 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 3406109d0638: 0000: 00012140 42001004 00040400 3407t0 write VPC_VARYING_INTERP[0].MODE (2142) 3408 VPC_VARYING_INTERP[0].MODE: 0 3409 VPC_VARYING_INTERP[0x1].MODE: 0 3410 VPC_VARYING_INTERP[0x2].MODE: 0 3411 VPC_VARYING_INTERP[0x3].MODE: 0 3412 VPC_VARYING_INTERP[0x4].MODE: 0 3413 VPC_VARYING_INTERP[0x5].MODE: 0 3414 VPC_VARYING_INTERP[0x6].MODE: 0 3415 VPC_VARYING_INTERP[0x7].MODE: 0 3416109d0644: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3417* 3418t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 3419 VPC_VARYING_PS_REPL[0].MODE: 0 3420 VPC_VARYING_PS_REPL[0x1].MODE: 0 3421 VPC_VARYING_PS_REPL[0x2].MODE: 0 3422 VPC_VARYING_PS_REPL[0x3].MODE: 0 3423 VPC_VARYING_PS_REPL[0x4].MODE: 0 3424 VPC_VARYING_PS_REPL[0x5].MODE: 0 3425 VPC_VARYING_PS_REPL[0x6].MODE: 0 3426 VPC_VARYING_PS_REPL[0x7].MODE: 0 3427109d0668: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3428* 3429t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 3430 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 3431 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 3432 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 3433 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 3434 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 3435 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 3436 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 3437 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 3438 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 3439 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 3440 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 3441 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 3442 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 3443 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 3444 :0:0012:0012[00000000x_00000000x] nop 3445 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 3446 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 3447 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 3448 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 3449 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 3450 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 3451 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 3452 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 3453 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 3454 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 3455 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 3456 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 3457 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 3458 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 3459 :0:0027:0027[00000200x_00000000x] (rpt2)nop 3460 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 3461 :0:0029:0031[00000000x_00000000x] nop 3462 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 3463 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 3464 :0:0032:0034[00000200x_00000000x] (rpt2)nop 3465 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 3466 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 3467 :0:0035:0039[00000200x_00000000x] (rpt2)nop 3468 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 3469 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 3470 :0:0038:0044[00000200x_00000000x] (rpt2)nop 3471 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 3472 :0:0040:0048[00000200x_00000000x] (rpt2)nop 3473 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 3474 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 3475 :0:0043:0053[00000100x_00000000x] (rpt1)nop 3476 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 3477 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 3478 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 3479 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 3480 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 3481 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 3482 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 3483 :0:0051:0062[03000000x_00000000x] end 3484 :0:0052:0063[00000000x_00000000x] nop 3485 :0:0053:0064[00000000x_00000000x] nop 3486 :0:0054:0065[00000000x_00000000x] nop 3487 :0:0055:0066[00000000x_00000000x] nop 3488 Register Stats: 3489 - used (half): (cnt=0, max=0) 3490 - used (full): 0-8 10-17 (cnt=17, max=17) 3491 - input (half): (cnt=0, max=0) 3492 - input (full): 2-8 (cnt=7, max=8) 3493 - max const: 52 3494 3495 - output (half): (cnt=0, max=0) (estimated) 3496 - output (full): 10-17 (cnt=8, max=17) (estimated) 3497 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 3498 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 3499 - shaderdb: 1 (ss), 0 (sy) 3500109d068c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 3501109d06ac: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 3502109d06cc: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 3503109d06ec: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 3504109d070c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 3505109d072c: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 3506109d074c: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 3507109d076c: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 3508109d078c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 3509109d07ac: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 3510109d07cc: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 3511109d07ec: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 3512109d080c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 3513109d082c: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 3514* 3515t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 3516 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 3517 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 3518 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x 3519 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x 3520 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x 3521 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x 3522 :0:0004:0004[03000000x_00000000x] end 3523 :0:0005:0005[00000000x_00000000x] nop 3524 :0:0006:0006[00000000x_00000000x] nop 3525 :0:0007:0007[00000000x_00000000x] nop 3526 :0:0008:0008[00000000x_00000000x] nop 3527 Register Stats: 3528 - used (half): (cnt=0, max=0) 3529 - used (full): 0 2-5 (cnt=5, max=5) 3530 - input (half): (cnt=0, max=0) 3531 - input (full): 0 (cnt=1, max=0) 3532 - max const: 0 3533 3534 - output (half): (cnt=0, max=0) (estimated) 3535 - output (full): 2-5 (cnt=4, max=5) (estimated) 3536 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full 3537 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 3538 - shaderdb: 0 (ss), 0 (sy) 3539109d0898: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 3540109d08b8: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 3541* 3542t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 3543109d0924: 0000: c0002600 00000000 3544t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 3545 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 3546 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 3547109d0938: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 3548109d0958: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 3549109d0978: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000 3550109d0998: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 3551109d09b8: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000 3552109d09d8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 3553109d0938: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 3554109d0958: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 3555109d0978: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3556109d0998: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3557109d09b8: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 3558109d09d8: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 3559109d092c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 3560109d094c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 3561109d096c: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3562109d098c: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 3563109d09ac: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 3564109d09cc: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 3565109d09ec: 00c0: 02020202 02020202 00000202 3566t0 write VFD_INDEX_OFFSET (2208) 3567 VFD_INDEX_OFFSET: 0 3568 UNKNOWN_2209: 0 3569109d09f8: 0000: 00012208 00000000 00000000 3570t0 write PC_RESTART_INDEX (21c6) 3571 PC_RESTART_INDEX: 0xffffffff 3572109d0a04: 0000: 000021c6 ffffffff 3573t0 write CP_SCRATCH[0x7].REG (057f) 3574 CP_SCRATCH[0x7].REG: 0x4a 3575 :0,73,115,74 3576109d0a0c: 0000: 0000057f 0000004a 3577t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 3578 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 3579 { NUM_INSTANCES = 1 } 3580 { NUM_INDICES = 60 } 3581 { FIRST_INDX = 0 } 3582 { INDX_BASE = 0x10bd0f00 } 3583 { INDX_SIZE = 120 } 3584 draw[12] register values 3585!+ 00000049 CP_SCRATCH[0x5].REG: 0x49 3586 :0,73,115,74 3587!+ 0000004a CP_SCRATCH[0x7].REG: 0x4a 3588 :0,73,115,74 3589 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 3590!+ 00000001 GRAS_CNTL: { IJ_PERSP } 3591 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 3592 + 00000010 GRAS_SU_POINT_SIZE: 1.000000 3593 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 3594 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 3595 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 3596 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 3597 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 3598 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 3599 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3600!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 3601 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 3602 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 3603 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 3604 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 3605 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 3606 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 3607!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 3608 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 3609 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 3610 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 3611 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 3612 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 3613 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 3614 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 3615 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 3616 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 3617 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 3618 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 3619 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 3620 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 3621 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 3622 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 3623 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 3624 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 3625 + ffffffff PC_RESTART_INDEX: 0xffffffff 3626 + 00000000 VFD_INDEX_OFFSET: 0 3627 + 00000000 UNKNOWN_2209: 0 3628 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 3629 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 3630 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 3631 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 3632 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 3633 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 3634 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 3635 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 3636 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 3637 + 00000004 SP_VS_LENGTH_REG: 4 3638!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 3639 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 3640 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3641!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 3642 + 00000001 SP_FS_LENGTH_REG: 1 3643 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 3644!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 3645!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 3646!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 3647!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 3648!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 3649!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 3650!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 3651!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 3652 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3653 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3654 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3655 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 3656 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 3657 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 3658!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 3659 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 3660 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 3661 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 3662 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3663 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3664 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3665 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 3666109d0a14: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0f00 00000078 3667t0 write CP_SCRATCH[0x7].REG (057f) 3668 CP_SCRATCH[0x7].REG: 0x4b 3669 :0,73,115,75 3670109d0a30: 0000: 0000057f 0000004b 3671t0 write CP_SCRATCH[0x5].REG (057d) 3672 CP_SCRATCH[0x5].REG: 0x4f 3673 :0,79,115,75 3674109d0a38: 0000: 0000057d 0000004f 3675t0 write RB_DEPTH_CONTROL (2101) 3676 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 3677109d0a40: 0000: 00002101 80000016 3678t0 write GRAS_ALPHA_CONTROL (2073) 3679 GRAS_ALPHA_CONTROL: { 0 } 3680109d0a48: 0000: 00002073 00000000 3681t0 write GRAS_SU_MODE_CONTROL (2078) 3682 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 3683109d0a50: 0000: 00002078 00100012 3684t0 write GRAS_SU_POINT_MINMAX (2070) 3685 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 3686 GRAS_SU_POINT_SIZE: 1.000000 3687109d0a58: 0000: 00012070 00100010 00000010 3688t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 3689 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 3690 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 3691 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 3692109d0a64: 0000: 00022074 00000000 00000000 00000000 3693t0 write GRAS_CL_CLIP_CNTL (2000) 3694 GRAS_CL_CLIP_CNTL: { 0x80000 } 3695109d0a74: 0000: 00002000 00080000 3696t0 write PC_PRIM_VTX_CNTL (21c4) 3697 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 3698 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 3699109d0a7c: 0000: 000121c4 02000001 00000012 3700t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 3701 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 3702 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 3703109d0a88: 0000: 0001209c 012b012b 00000000 3704t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 3705 RB_VPORT_Z_CLAMP[0].MIN: 0 3706 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 3707109d0a94: 0000: 00012120 00000000 00ffffff 3708t0 write HLSQ_UPDATE_CONTROL (23db) 3709 HLSQ_UPDATE_CONTROL: 0x3 3710109d0aa0: 0000: 000023db 00000003 3711t0 write HLSQ_CONTROL_0_REG (23c0) 3712 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 3713 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 3714 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 3715 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 3716 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 3717109d0aa8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 3718t0 write HLSQ_VS_CONTROL_REG (23c5) 3719 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 3720 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 3721 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3722 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3723 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 3724109d0ac0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 3725t0 write SP_SP_CTRL_REG (22c0) 3726 SP_SP_CTRL_REG: { 0x140010 } 3727109d0ad8: 0000: 000022c0 00140010 3728t0 write SP_INSTR_CACHE_CTRL (22c1) 3729 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 3730109d0ae0: 0000: 000022c1 000005ff 3731t0 write SP_VS_LENGTH_REG (22e5) 3732 SP_VS_LENGTH_REG: 4 3733109d0ae8: 0000: 000022e5 00000004 3734t0 write SP_VS_CTRL_REG0 (22c4) 3735 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 3736 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 3737 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 3738109d0af0: 0000: 000222c4 00201000 04000042 0010fc06 3739t0 write SP_VS_OUT[0].REG (22c7) 3740 SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 3741109d0b00: 0000: 000022c7 00001e0a 3742t0 write SP_VS_VPC_DST[0].REG (22d8) 3743 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 3744109d0b08: 0000: 000022d8 08080808 3745t0 write SP_VS_OBJ_OFFSET_REG (22e0) 3746 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 3747 SP_VS_OBJ_START: 0x10cd0000 3748109d0b10: 0000: 000122e0 00000000 10cd0000 3749t0 write SP_FS_LENGTH_REG (22ef) 3750 SP_FS_LENGTH_REG: 1 3751109d0b1c: 0000: 000022ef 00000001 3752t0 write SP_FS_CTRL_REG0 (22e8) 3753 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 3754 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 3755109d0b24: 0000: 000122e8 00340402 8010003e 3756t0 write SP_FS_OBJ_OFFSET_REG (22ea) 3757 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3758 SP_FS_OBJ_START: 0x10cd2000 3759109d0b30: 0000: 000122ea 7e420000 10cd2000 3760t0 write SP_HS_OBJ_OFFSET_REG (230d) 3761 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3762109d0b3c: 0000: 0000230d 7e420000 3763t0 write SP_DS_OBJ_OFFSET_REG (2334) 3764 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3765109d0b44: 0000: 00002334 7e420000 3766t0 write SP_GS_OBJ_OFFSET_REG (235b) 3767 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 3768109d0b4c: 0000: 0000235b 7e420000 3769t0 write GRAS_CNTL (2003) 3770 GRAS_CNTL: { 0 } 3771109d0b54: 0000: 00002003 00000000 3772t0 write RB_RENDER_CONTROL2 (20a3) 3773 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 3774109d0b5c: 0000: 000020a3 00000000 3775t0 write RB_FS_OUTPUT_REG (2100) 3776 RB_FS_OUTPUT_REG: { MRT = 1 } 3777109d0b64: 0000: 00002100 00000001 3778t0 write SP_FS_OUTPUT_REG (22f0) 3779 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 3780109d0b6c: 0000: 000022f0 0000fc01 3781t0 write SP_FS_MRT[0].REG (22f1) 3782 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 3783 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 3784 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 3785 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 3786 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 3787 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 3788 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 3789 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 3790109d0b74: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 3791* 3792t0 write VPC_ATTR (2140) 3793 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 3794 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 3795109d0b98: 0000: 00012140 42001004 00040400 3796t0 write VPC_VARYING_INTERP[0].MODE (2142) 3797 VPC_VARYING_INTERP[0].MODE: 0x55 3798 VPC_VARYING_INTERP[0x1].MODE: 0 3799 VPC_VARYING_INTERP[0x2].MODE: 0 3800 VPC_VARYING_INTERP[0x3].MODE: 0 3801 VPC_VARYING_INTERP[0x4].MODE: 0 3802 VPC_VARYING_INTERP[0x5].MODE: 0 3803 VPC_VARYING_INTERP[0x6].MODE: 0 3804 VPC_VARYING_INTERP[0x7].MODE: 0 3805109d0ba4: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 3806* 3807t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 3808 VPC_VARYING_PS_REPL[0].MODE: 0 3809 VPC_VARYING_PS_REPL[0x1].MODE: 0 3810 VPC_VARYING_PS_REPL[0x2].MODE: 0 3811 VPC_VARYING_PS_REPL[0x3].MODE: 0 3812 VPC_VARYING_PS_REPL[0x4].MODE: 0 3813 VPC_VARYING_PS_REPL[0x5].MODE: 0 3814 VPC_VARYING_PS_REPL[0x6].MODE: 0 3815 VPC_VARYING_PS_REPL[0x7].MODE: 0 3816109d0bc8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3817* 3818t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 3819 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 3820 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 3821 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 3822 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 3823 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 3824 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 3825 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 3826 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 3827 :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x 3828 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 3829 :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y 3830 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 3831 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 3832 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 3833 :0:0012:0012[00000000x_00000000x] nop 3834 :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x 3835 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 3836 :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y 3837 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 3838 :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z 3839 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 3840 :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w 3841 :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x 3842 :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y 3843 :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z 3844 :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x 3845 :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w 3846 :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x 3847 :0:0026:0026[00000000x_00000000x] nop 3848 :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x 3849 :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z 3850 :0:0029:0029[00000200x_00000000x] (rpt2)nop 3851 :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x 3852 :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x 3853 :0:0032:0034[00000200x_00000000x] (rpt2)nop 3854 :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y 3855 :0:0034:0038[00000000x_00000000x] nop 3856 :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x 3857 :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x 3858 :0:0037:0041[00000200x_00000000x] (rpt2)nop 3859 :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y 3860 :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x 3861 :0:0040:0046[00000200x_00000000x] (rpt2)nop 3862 :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x 3863 :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x 3864 :0:0043:0051[00000200x_00000000x] (rpt2)nop 3865 :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x 3866 :0:0045:0055[00000200x_00000000x] (rpt2)nop 3867 :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 3868 :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x 3869 :0:0048:0060[00000100x_00000000x] (rpt1)nop 3870 :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 3871 :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y 3872 :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z 3873 :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w 3874 :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y 3875 :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z 3876 :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x 3877 :0:0056:0069[03000000x_00000000x] end 3878 :0:0057:0070[00000000x_00000000x] nop 3879 :0:0058:0071[00000000x_00000000x] nop 3880 :0:0059:0072[00000000x_00000000x] nop 3881 :0:0060:0073[00000000x_00000000x] nop 3882 Register Stats: 3883 - used (half): (cnt=0, max=0) 3884 - used (full): 0-13 (cnt=14, max=13) 3885 - input (half): (cnt=0, max=0) 3886 - input (full): 2-5 (cnt=4, max=5) 3887 - max const: 52 3888 3889 - output (half): (cnt=0, max=0) (estimated) 3890 - output (full): 6-13 (cnt=8, max=13) (estimated) 3891 - shaderdb: 74 instructions, 27 nops, 47 non-nops, (61 instlen), 0 last-baryf, 0 half, 4 full 3892 - shaderdb: 28 cat0, 8 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 3893 - shaderdb: 1 (ss), 0 (sy) 3894109d0bec: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 3895109d0c0c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 3896109d0c2c: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 3897109d0c4c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 3898109d0c6c: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a 3899109d0c8c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 3900109d0cac: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 3901109d0ccc: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 3902109d0cec: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 3903109d0d0c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 3904109d0d2c: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 3905109d0d4c: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 3906109d0d6c: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 3907109d0d8c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 3908109d0dac: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 3909* 3910t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 3911 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 3912 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 3913 :0:0000:0000[00000000x_00000000x] nop 3914 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 3915 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 3916 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 3917 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 3918 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 3919 :0:0006:0006[03000000x_00000000x] end 3920 :0:0007:0007[00000000x_00000000x] nop 3921 :0:0008:0008[00000000x_00000000x] nop 3922 :0:0009:0009[00000000x_00000000x] nop 3923 :0:0010:0010[00000000x_00000000x] nop 3924 Register Stats: 3925 - used (half): (cnt=0, max=0) 3926 - used (full): 0-3 (cnt=4, max=3) 3927 - input (half): (cnt=0, max=0) 3928 - input (full): 0-3 (cnt=4, max=3) 3929 - max const: 0 3930 3931 - output (half): (cnt=0, max=0) (estimated) 3932 - output (full): (cnt=0, max=0) (estimated) 3933 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 3934 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 3935 - shaderdb: 1 (ss), 0 (sy) 3936109d0df8: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 3937109d0e18: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 3938109d0e38: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3939* 3940t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 3941109d0e84: 0000: c0002600 00000000 3942t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 3943 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 3944 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 3945109d0e98: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 3946109d0eb8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 3947109d0ed8: 0.000000 0.000000 1.000000 1.000000 0.040000 0.040000 0.200000 1.000000 3948109d0ef8: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 3949109d0f18: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000 3950109d0f38: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 3951109d0e98: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc 3952109d0eb8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f 3953109d0ed8: 0040: 00000000 00000000 3f800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000 3954109d0ef8: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 3955109d0f18: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 3956109d0f38: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 3957109d0e8c: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 3958109d0eac: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 3959109d0ecc: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 3f800000 3f800000 3d23d70b 3960109d0eec: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 3961109d0f0c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd 3962109d0f2c: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000 3963109d0f4c: 00c0: 00000000 00000000 3f800000 3964t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 3965 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 3966 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 3967109d0f64: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 3968109d0f64: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 3969109d0f58: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 3970t0 write VFD_FETCH[0].INSTR_0 (220a) 3971 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 3972 VFD_FETCH[0].INSTR_1: 0x107cb000 3973 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 3974 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 3975109d0f74: 0000: 0003220a 0000060b 107cb000 00100000 00000001 3976t0 write VFD_DECODE[0].INSTR (228a) 3977 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 3978109d0f88: 0000: 0000228a 2c0020df 3979t0 write VFD_CONTROL_0 (2200) 3980 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 3981 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 3982 VFD_CONTROL_2: 0 3983 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 3984 VFD_CONTROL_4: 0 3985109d0f90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 3986t0 write UCHE_INVALIDATE0 (0e8a) 3987 UCHE_INVALIDATE0: 0 3988 UCHE_INVALIDATE1: 0x12 3989109d0fa8: 0000: 00010e8a 00000000 00000012 3990t0 write VFD_INDEX_OFFSET (2208) 3991 VFD_INDEX_OFFSET: 0 3992 UNKNOWN_2209: 0 3993109d0fb4: 0000: 00012208 00000000 00000000 3994t0 write PC_RESTART_INDEX (21c6) 3995 PC_RESTART_INDEX: 0xffffffff 3996109d0fc0: 0000: 000021c6 ffffffff 3997t0 write CP_SCRATCH[0x7].REG (057f) 3998 CP_SCRATCH[0x7].REG: 0x50 3999 :0,79,115,80 4000109d0fc8: 0000: 0000057f 00000050 4001t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4002 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4003 { NUM_INSTANCES = 1 } 4004 { NUM_INDICES = 120 } 4005 { FIRST_INDX = 0 } 4006 { INDX_BASE = 0x10bd0f78 } 4007 { INDX_SIZE = 240 } 4008 draw[13] register values 4009!+ 0000004f CP_SCRATCH[0x5].REG: 0x4f 4010 :0,79,115,80 4011!+ 00000050 CP_SCRATCH[0x7].REG: 0x50 4012 :0,79,115,80 4013 + 00000000 UCHE_INVALIDATE0: 0 4014 + 00000012 UCHE_INVALIDATE1: 0x12 4015 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 4016!+ 00000000 GRAS_CNTL: { 0 } 4017 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 4018 + 00000010 GRAS_SU_POINT_SIZE: 1.000000 4019 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 4020 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 4021 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 4022 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 4023 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 4024 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 4025 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4026!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 4027 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 4028 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 4029 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 4030 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 4031 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 4032 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 4033!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 4034 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 4035 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 4036 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 4037 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 4038 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 4039 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 4040 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 4041 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 4042 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 4043 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 4044 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 4045 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 4046 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 4047 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 4048 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 4049 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4050 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4051 + ffffffff PC_RESTART_INDEX: 0xffffffff 4052!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 4053 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 4054 + 00000000 VFD_CONTROL_2: 0 4055 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 4056 + 00000000 VFD_CONTROL_4: 0 4057 + 00000000 VFD_INDEX_OFFSET: 0 4058 + 00000000 UNKNOWN_2209: 0 4059!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 4060 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 4061 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 4062 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 4063!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 4064 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 4065 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 4066!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 4067!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 4068!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 4069!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 4070 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 4071 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 4072!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 4073 + 00000004 SP_VS_LENGTH_REG: 4 4074!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 4075 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 4076 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4077!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 4078 + 00000001 SP_FS_LENGTH_REG: 1 4079 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 4080!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 4081!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 4082!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 4083!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 4084!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 4085!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 4086!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 4087!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 4088 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4089 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4090 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4091 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 4092 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 4093 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 4094!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 4095 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 4096 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 4097 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 4098 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4099 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4100 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4101 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 4102109d0fd0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0f78 000000f0 4103t0 write CP_SCRATCH[0x7].REG (057f) 4104 CP_SCRATCH[0x7].REG: 0x51 4105 :0,79,115,81 4106109d0fec: 0000: 0000057f 00000051 4107t0 write CP_SCRATCH[0x5].REG (057d) 4108 CP_SCRATCH[0x5].REG: 0x55 4109 :0,85,115,81 4110109d0ff4: 0000: 0000057d 00000055 4111t0 write PC_PRIM_VTX_CNTL (21c4) 4112 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4113 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4114109d0ffc: 0000: 000121c4 02000001 00000012 4115t0 write VFD_INDEX_OFFSET (2208) 4116 VFD_INDEX_OFFSET: 0 4117 UNKNOWN_2209: 0 4118109d1008: 0000: 00012208 00000000 00000000 4119t0 write PC_RESTART_INDEX (21c6) 4120 PC_RESTART_INDEX: 0xffffffff 4121109d1014: 0000: 000021c6 ffffffff 4122t0 write CP_SCRATCH[0x7].REG (057f) 4123 CP_SCRATCH[0x7].REG: 0x56 4124 :0,85,115,86 4125109d101c: 0000: 0000057f 00000056 4126t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4127 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4128 { NUM_INSTANCES = 1 } 4129 { NUM_INDICES = 60 } 4130 { FIRST_INDX = 0 } 4131 { INDX_BASE = 0x10bd1068 } 4132 { INDX_SIZE = 120 } 4133 draw[14] register values 4134!+ 00000055 CP_SCRATCH[0x5].REG: 0x55 4135 :0,85,115,86 4136!+ 00000056 CP_SCRATCH[0x7].REG: 0x56 4137 :0,85,115,86 4138 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4139 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4140 + ffffffff PC_RESTART_INDEX: 0xffffffff 4141 + 00000000 VFD_INDEX_OFFSET: 0 4142 + 00000000 UNKNOWN_2209: 0 4143109d1024: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1068 00000078 4144t0 write CP_SCRATCH[0x7].REG (057f) 4145 CP_SCRATCH[0x7].REG: 0x57 4146 :0,85,115,87 4147109d1040: 0000: 0000057f 00000057 4148t0 write CP_SCRATCH[0x5].REG (057d) 4149 CP_SCRATCH[0x5].REG: 0x5b 4150 :0,91,115,87 4151109d1048: 0000: 0000057d 0000005b 4152t0 write PC_PRIM_VTX_CNTL (21c4) 4153 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4154 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4155109d1050: 0000: 000121c4 02000001 00000012 4156t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 4157109d105c: 0000: c0002600 00000000 4158t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 4159 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 4160 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 4161109d1070: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 4162109d1090: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 4163109d10b0: 0.000000 0.000000 -1.000000 1.000000 0.040000 0.040000 0.200000 1.000000 4164109d10d0: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 4165109d10f0: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000 4166109d1110: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 4167109d1070: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc 4168109d1090: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f 4169109d10b0: 0040: 00000000 00000000 bf800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000 4170109d10d0: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 4171109d10f0: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 4172109d1110: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 4173109d1064: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4174109d1084: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4175109d10a4: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 bf800000 3f800000 3d23d70b 4176109d10c4: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 4177109d10e4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd 4178109d1104: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000 4179109d1124: 00c0: 00000000 00000000 3f800000 4180t0 write VFD_INDEX_OFFSET (2208) 4181 VFD_INDEX_OFFSET: 0 4182 UNKNOWN_2209: 0 4183109d1130: 0000: 00012208 00000000 00000000 4184t0 write PC_RESTART_INDEX (21c6) 4185 PC_RESTART_INDEX: 0xffffffff 4186109d113c: 0000: 000021c6 ffffffff 4187t0 write CP_SCRATCH[0x7].REG (057f) 4188 CP_SCRATCH[0x7].REG: 0x5c 4189 :0,91,115,92 4190109d1144: 0000: 0000057f 0000005c 4191t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4192 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4193 { NUM_INSTANCES = 1 } 4194 { NUM_INDICES = 120 } 4195 { FIRST_INDX = 0 } 4196 { INDX_BASE = 0x10bd10e0 } 4197 { INDX_SIZE = 240 } 4198 draw[15] register values 4199!+ 0000005b CP_SCRATCH[0x5].REG: 0x5b 4200 :0,91,115,92 4201!+ 0000005c CP_SCRATCH[0x7].REG: 0x5c 4202 :0,91,115,92 4203 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4204 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4205 + ffffffff PC_RESTART_INDEX: 0xffffffff 4206 + 00000000 VFD_INDEX_OFFSET: 0 4207 + 00000000 UNKNOWN_2209: 0 4208109d114c: 0000: c0053800 00000404 00000001 00000078 00000000 10bd10e0 000000f0 4209t0 write CP_SCRATCH[0x7].REG (057f) 4210 CP_SCRATCH[0x7].REG: 0x5d 4211 :0,91,115,93 4212109d1168: 0000: 0000057f 0000005d 4213t0 write CP_SCRATCH[0x5].REG (057d) 4214 CP_SCRATCH[0x5].REG: 0x61 4215 :0,97,115,93 4216109d1170: 0000: 0000057d 00000061 4217t0 write PC_PRIM_VTX_CNTL (21c4) 4218 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4219 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4220109d1178: 0000: 000121c4 02000001 00000012 4221t0 write VFD_INDEX_OFFSET (2208) 4222 VFD_INDEX_OFFSET: 0 4223 UNKNOWN_2209: 0 4224109d1184: 0000: 00012208 00000000 00000000 4225t0 write PC_RESTART_INDEX (21c6) 4226 PC_RESTART_INDEX: 0xffffffff 4227109d1190: 0000: 000021c6 ffffffff 4228t0 write CP_SCRATCH[0x7].REG (057f) 4229 CP_SCRATCH[0x7].REG: 0x62 4230 :0,97,115,98 4231109d1198: 0000: 0000057f 00000062 4232t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4233 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4234 { NUM_INSTANCES = 1 } 4235 { NUM_INDICES = 60 } 4236 { FIRST_INDX = 0 } 4237 { INDX_BASE = 0x10bd11d0 } 4238 { INDX_SIZE = 120 } 4239 draw[16] register values 4240!+ 00000061 CP_SCRATCH[0x5].REG: 0x61 4241 :0,97,115,98 4242!+ 00000062 CP_SCRATCH[0x7].REG: 0x62 4243 :0,97,115,98 4244 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4245 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4246 + ffffffff PC_RESTART_INDEX: 0xffffffff 4247 + 00000000 VFD_INDEX_OFFSET: 0 4248 + 00000000 UNKNOWN_2209: 0 4249109d11a0: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd11d0 00000078 4250t0 write CP_SCRATCH[0x7].REG (057f) 4251 CP_SCRATCH[0x7].REG: 0x63 4252 :0,97,115,99 4253109d11bc: 0000: 0000057f 00000063 4254t0 write CP_SCRATCH[0x5].REG (057d) 4255 CP_SCRATCH[0x5].REG: 0x67 4256 :0,103,115,99 4257109d11c4: 0000: 0000057d 00000067 4258t0 write RB_DEPTH_CONTROL (2101) 4259 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 4260109d11cc: 0000: 00002101 80000016 4261t0 write GRAS_ALPHA_CONTROL (2073) 4262 GRAS_ALPHA_CONTROL: { 0 } 4263109d11d4: 0000: 00002073 00000000 4264t0 write PC_PRIM_VTX_CNTL (21c4) 4265 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4266 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4267109d11dc: 0000: 000121c4 02000001 00000012 4268t0 write HLSQ_UPDATE_CONTROL (23db) 4269 HLSQ_UPDATE_CONTROL: 0x3 4270109d11e8: 0000: 000023db 00000003 4271t0 write HLSQ_CONTROL_0_REG (23c0) 4272 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 4273 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 4274 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 4275 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 4276 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 4277109d11f0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 4278t0 write HLSQ_VS_CONTROL_REG (23c5) 4279 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 4280 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 4281 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4282 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4283 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4284109d1208: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 4285t0 write SP_SP_CTRL_REG (22c0) 4286 SP_SP_CTRL_REG: { 0x140010 } 4287109d1220: 0000: 000022c0 00140010 4288t0 write SP_INSTR_CACHE_CTRL (22c1) 4289 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 4290109d1228: 0000: 000022c1 000005ff 4291t0 write SP_VS_LENGTH_REG (22e5) 4292 SP_VS_LENGTH_REG: 4 4293109d1230: 0000: 000022e5 00000004 4294t0 write SP_VS_CTRL_REG0 (22c4) 4295 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 4296 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 4297 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 4298109d1238: 0000: 000222c4 00201400 08000042 0010fc0a 4299t0 write SP_VS_OUT[0].REG (22c7) 4300 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 4301109d1248: 0000: 000022c7 00001e0e 4302t0 write SP_VS_VPC_DST[0].REG (22d8) 4303 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 4304109d1250: 0000: 000022d8 08080808 4305t0 write SP_VS_OBJ_OFFSET_REG (22e0) 4306 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 4307 SP_VS_OBJ_START: 0x10cd5000 4308109d1258: 0000: 000122e0 00000000 10cd5000 4309t0 write SP_FS_LENGTH_REG (22ef) 4310 SP_FS_LENGTH_REG: 1 4311109d1264: 0000: 000022ef 00000001 4312t0 write SP_FS_CTRL_REG0 (22e8) 4313 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 4314 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 4315109d126c: 0000: 000122e8 00340402 8010003e 4316t0 write SP_FS_OBJ_OFFSET_REG (22ea) 4317 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4318 SP_FS_OBJ_START: 0x10cd2000 4319109d1278: 0000: 000122ea 7e420000 10cd2000 4320t0 write SP_HS_OBJ_OFFSET_REG (230d) 4321 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4322109d1284: 0000: 0000230d 7e420000 4323t0 write SP_DS_OBJ_OFFSET_REG (2334) 4324 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4325109d128c: 0000: 00002334 7e420000 4326t0 write SP_GS_OBJ_OFFSET_REG (235b) 4327 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4328109d1294: 0000: 0000235b 7e420000 4329t0 write GRAS_CNTL (2003) 4330 GRAS_CNTL: { 0 } 4331109d129c: 0000: 00002003 00000000 4332t0 write RB_RENDER_CONTROL2 (20a3) 4333 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 4334109d12a4: 0000: 000020a3 00000000 4335t0 write RB_FS_OUTPUT_REG (2100) 4336 RB_FS_OUTPUT_REG: { MRT = 1 } 4337109d12ac: 0000: 00002100 00000001 4338t0 write SP_FS_OUTPUT_REG (22f0) 4339 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 4340109d12b4: 0000: 000022f0 0000fc01 4341t0 write SP_FS_MRT[0].REG (22f1) 4342 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 4343 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 4344 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 4345 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 4346 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 4347 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 4348 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 4349 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 4350109d12bc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 4351* 4352t0 write VPC_ATTR (2140) 4353 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 4354 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 4355109d12e0: 0000: 00012140 42001004 00040400 4356t0 write VPC_VARYING_INTERP[0].MODE (2142) 4357 VPC_VARYING_INTERP[0].MODE: 0x55 4358 VPC_VARYING_INTERP[0x1].MODE: 0 4359 VPC_VARYING_INTERP[0x2].MODE: 0 4360 VPC_VARYING_INTERP[0x3].MODE: 0 4361 VPC_VARYING_INTERP[0x4].MODE: 0 4362 VPC_VARYING_INTERP[0x5].MODE: 0 4363 VPC_VARYING_INTERP[0x6].MODE: 0 4364 VPC_VARYING_INTERP[0x7].MODE: 0 4365109d12ec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 4366* 4367t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 4368 VPC_VARYING_PS_REPL[0].MODE: 0 4369 VPC_VARYING_PS_REPL[0x1].MODE: 0 4370 VPC_VARYING_PS_REPL[0x2].MODE: 0 4371 VPC_VARYING_PS_REPL[0x3].MODE: 0 4372 VPC_VARYING_PS_REPL[0x4].MODE: 0 4373 VPC_VARYING_PS_REPL[0x5].MODE: 0 4374 VPC_VARYING_PS_REPL[0x6].MODE: 0 4375 VPC_VARYING_PS_REPL[0x7].MODE: 0 4376109d1310: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4377* 4378t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 4379 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 4380 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 4381 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 4382 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 4383 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 4384 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 4385 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 4386 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 4387 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 4388 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 4389 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 4390 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 4391 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 4392 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 4393 :0:0012:0012[00000000x_00000000x] nop 4394 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 4395 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 4396 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 4397 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 4398 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 4399 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 4400 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 4401 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 4402 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 4403 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 4404 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 4405 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 4406 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 4407 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 4408 :0:0027:0027[00000200x_00000000x] (rpt2)nop 4409 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 4410 :0:0029:0031[00000000x_00000000x] nop 4411 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 4412 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 4413 :0:0032:0034[00000200x_00000000x] (rpt2)nop 4414 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 4415 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 4416 :0:0035:0039[00000200x_00000000x] (rpt2)nop 4417 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 4418 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 4419 :0:0038:0044[00000200x_00000000x] (rpt2)nop 4420 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 4421 :0:0040:0048[00000200x_00000000x] (rpt2)nop 4422 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 4423 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 4424 :0:0043:0053[00000100x_00000000x] (rpt1)nop 4425 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 4426 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 4427 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 4428 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 4429 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 4430 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 4431 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 4432 :0:0051:0062[03000000x_00000000x] end 4433 :0:0052:0063[00000000x_00000000x] nop 4434 :0:0053:0064[00000000x_00000000x] nop 4435 :0:0054:0065[00000000x_00000000x] nop 4436 :0:0055:0066[00000000x_00000000x] nop 4437 Register Stats: 4438 - used (half): (cnt=0, max=0) 4439 - used (full): 0-8 10-17 (cnt=17, max=17) 4440 - input (half): (cnt=0, max=0) 4441 - input (full): 2-8 (cnt=7, max=8) 4442 - max const: 52 4443 4444 - output (half): (cnt=0, max=0) (estimated) 4445 - output (full): 10-17 (cnt=8, max=17) (estimated) 4446 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 4447 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 4448 - shaderdb: 1 (ss), 0 (sy) 4449109d1334: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 4450109d1354: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 4451109d1374: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 4452109d1394: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 4453109d13b4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 4454109d13d4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 4455109d13f4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 4456109d1414: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 4457109d1434: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 4458109d1454: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 4459109d1474: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 4460109d1494: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 4461109d14b4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 4462109d14d4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 4463* 4464t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 4465 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 4466 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 4467 :0:0000:0000[00000000x_00000000x] nop 4468 :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 4469 :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 4470 :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 4471 :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 4472 :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x 4473 :0:0006:0006[03000000x_00000000x] end 4474 :0:0007:0007[00000000x_00000000x] nop 4475 :0:0008:0008[00000000x_00000000x] nop 4476 :0:0009:0009[00000000x_00000000x] nop 4477 :0:0010:0010[00000000x_00000000x] nop 4478 Register Stats: 4479 - used (half): (cnt=0, max=0) 4480 - used (full): 0-3 (cnt=4, max=3) 4481 - input (half): (cnt=0, max=0) 4482 - input (full): 0-3 (cnt=4, max=3) 4483 - max const: 0 4484 4485 - output (half): (cnt=0, max=0) (estimated) 4486 - output (full): (cnt=0, max=0) (estimated) 4487 - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 5 last-baryf, 0 half, 1 full 4488 - shaderdb: 6 cat0, 0 cat1, 1 cat2, 0 cat3, 0 cat4, 0 cat5, 4 cat6, 0 cat7 4489 - shaderdb: 1 (ss), 0 (sy) 4490109d1540: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 4491109d1560: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 4492109d1580: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4493* 4494t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 4495109d15cc: 0000: c0002600 00000000 4496t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 4497 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 4498 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 4499109d15e0: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 4500109d1600: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 4501109d1620: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000 4502109d1640: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 4503109d1660: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000 4504109d1680: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 4505109d15e0: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc 4506109d1600: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f 4507109d1620: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 4508109d1640: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 4509109d1660: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 4510109d1680: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 4511109d15d4: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4512109d15f4: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4513109d1614: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 4514109d1634: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 4515109d1654: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 4516109d1674: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 4517109d1694: 00c0: 02020202 02020202 00000202 4518t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) 4519 { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 4520 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 4521109d16ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 4522109d16ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 4523109d16a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 4524t0 write VFD_FETCH[0].INSTR_0 (220a) 4525 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 4526 VFD_FETCH[0].INSTR_1: 0x107cb000 4527 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 4528 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 4529109d16bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 4530t0 write VFD_DECODE[0].INSTR (228a) 4531 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 4532109d16d0: 0000: 0000228a 6c0020df 4533t0 write VFD_FETCH[0x1].INSTR_0 (220e) 4534 VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 4535 VFD_FETCH[0x1].INSTR_1: 0x107cb00c 4536 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 4537 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 4538109d16d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 4539t0 write VFD_DECODE[0x1].INSTR (228b) 4540 VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 4541109d16ec: 0000: 0000228b 2c0060df 4542t0 write VFD_CONTROL_0 (2200) 4543 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 4544 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 4545 VFD_CONTROL_2: 0 4546 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 4547 VFD_CONTROL_4: 0 4548109d16f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 4549t0 write UCHE_INVALIDATE0 (0e8a) 4550 UCHE_INVALIDATE0: 0 4551 UCHE_INVALIDATE1: 0x12 4552109d170c: 0000: 00010e8a 00000000 00000012 4553t0 write VFD_INDEX_OFFSET (2208) 4554 VFD_INDEX_OFFSET: 0 4555 UNKNOWN_2209: 0 4556109d1718: 0000: 00012208 00000000 00000000 4557t0 write PC_RESTART_INDEX (21c6) 4558 PC_RESTART_INDEX: 0xffffffff 4559109d1724: 0000: 000021c6 ffffffff 4560t0 write CP_SCRATCH[0x7].REG (057f) 4561 CP_SCRATCH[0x7].REG: 0x68 4562 :0,103,115,104 4563109d172c: 0000: 0000057f 00000068 4564t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4565 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4566 { NUM_INSTANCES = 1 } 4567 { NUM_INDICES = 240 } 4568 { FIRST_INDX = 0 } 4569 { INDX_BASE = 0x10bd1248 } 4570 { INDX_SIZE = 480 } 4571 draw[17] register values 4572!+ 00000067 CP_SCRATCH[0x5].REG: 0x67 4573 :0,103,115,104 4574!+ 00000068 CP_SCRATCH[0x7].REG: 0x68 4575 :0,103,115,104 4576 + 00000000 UCHE_INVALIDATE0: 0 4577 + 00000012 UCHE_INVALIDATE1: 0x12 4578 + 00000000 GRAS_CNTL: { 0 } 4579 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 4580 + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 4581 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 4582 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 4583 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 4584 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 4585 + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 4586 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 4587 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 4588 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 4589 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 4590 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 4591 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 4592 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 4593 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 4594 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 4595 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 4596 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 4597 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 4598 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 4599 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 4600 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 4601 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4602 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4603 + ffffffff PC_RESTART_INDEX: 0xffffffff 4604!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } 4605 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 4606 + 00000000 VFD_CONTROL_2: 0 4607 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 4608 + 00000000 VFD_CONTROL_4: 0 4609 + 00000000 VFD_INDEX_OFFSET: 0 4610 + 00000000 UNKNOWN_2209: 0 4611!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } 4612 + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 4613 + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } 4614 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 4615 + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } 4616 + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c 4617 + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } 4618 + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } 4619!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } 4620 + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 4621 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 4622 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 4623!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 4624!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 4625!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 4626!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 4627 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 4628 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 4629!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 4630 + 00000004 SP_VS_LENGTH_REG: 4 4631 + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 4632 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 4633 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4634 + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 4635 + 00000001 SP_FS_LENGTH_REG: 1 4636 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 4637 + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } 4638 + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 4639 + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 4640 + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 4641 + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 4642 + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 4643 + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 4644 + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 4645 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4646 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4647 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4648 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 4649 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 4650 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 4651 + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 4652 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 4653 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 4654 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 4655 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4656 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4657 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4658 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 4659109d1734: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd1248 000001e0 4660t0 write CP_SCRATCH[0x7].REG (057f) 4661 CP_SCRATCH[0x7].REG: 0x69 4662 :0,103,115,105 4663109d1750: 0000: 0000057f 00000069 4664t0 write CP_SCRATCH[0x5].REG (057d) 4665 CP_SCRATCH[0x5].REG: 0x6d 4666 :0,109,115,105 4667109d1758: 0000: 0000057d 0000006d 4668t0 write RB_DEPTH_CONTROL (2101) 4669 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 4670109d1760: 0000: 00002101 80000016 4671t0 write GRAS_ALPHA_CONTROL (2073) 4672 GRAS_ALPHA_CONTROL: { 0 } 4673109d1768: 0000: 00002073 00000000 4674t0 write GRAS_SU_MODE_CONTROL (2078) 4675 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 4676109d1770: 0000: 00002078 00100012 4677t0 write GRAS_SU_POINT_MINMAX (2070) 4678 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 4679 GRAS_SU_POINT_SIZE: 1.000000 4680109d1778: 0000: 00012070 00100010 00000010 4681t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) 4682 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 4683 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 4684 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 4685109d1784: 0000: 00022074 00000000 00000000 00000000 4686t0 write GRAS_CL_CLIP_CNTL (2000) 4687 GRAS_CL_CLIP_CNTL: { 0x80000 } 4688109d1794: 0000: 00002000 00080000 4689t0 write PC_PRIM_VTX_CNTL (21c4) 4690 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 4691 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 4692109d179c: 0000: 000121c4 02000001 00000012 4693t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 4694 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 4695 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4696109d17a8: 0000: 0001209c 012b012b 00000000 4697t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) 4698 RB_VPORT_Z_CLAMP[0].MIN: 0 4699 RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 4700109d17b4: 0000: 00012120 00000000 00ffffff 4701t0 write HLSQ_UPDATE_CONTROL (23db) 4702 HLSQ_UPDATE_CONTROL: 0x3 4703109d17c0: 0000: 000023db 00000003 4704t0 write HLSQ_CONTROL_0_REG (23c0) 4705 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 4706 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 4707 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 4708 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 4709 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 4710109d17c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc 4711t0 write HLSQ_VS_CONTROL_REG (23c5) 4712 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 4713 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 4714 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4715 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4716 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 4717109d17e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 4718t0 write SP_SP_CTRL_REG (22c0) 4719 SP_SP_CTRL_REG: { 0x140010 } 4720109d17f8: 0000: 000022c0 00140010 4721t0 write SP_INSTR_CACHE_CTRL (22c1) 4722 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 4723109d1800: 0000: 000022c1 000005ff 4724t0 write SP_VS_LENGTH_REG (22e5) 4725 SP_VS_LENGTH_REG: 4 4726109d1808: 0000: 000022e5 00000004 4727t0 write SP_VS_CTRL_REG0 (22c4) 4728 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 4729 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 4730 SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 4731109d1810: 0000: 000222c4 00201400 08000042 0010fc0a 4732t0 write SP_VS_OUT[0].REG (22c7) 4733 SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 4734109d1820: 0000: 000022c7 00001e0e 4735t0 write SP_VS_VPC_DST[0].REG (22d8) 4736 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 4737109d1828: 0000: 000022d8 08080808 4738t0 write SP_VS_OBJ_OFFSET_REG (22e0) 4739 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 4740 SP_VS_OBJ_START: 0x10cd5000 4741109d1830: 0000: 000122e0 00000000 10cd5000 4742t0 write SP_FS_LENGTH_REG (22ef) 4743 SP_FS_LENGTH_REG: 1 4744109d183c: 0000: 000022ef 00000001 4745t0 write SP_FS_CTRL_REG0 (22e8) 4746 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 4747 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 4748109d1844: 0000: 000122e8 00340802 8010003e 4749t0 write SP_FS_OBJ_OFFSET_REG (22ea) 4750 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4751 SP_FS_OBJ_START: 0x108cb000 4752109d1850: 0000: 000122ea 7e420000 108cb000 4753t0 write SP_HS_OBJ_OFFSET_REG (230d) 4754 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4755109d185c: 0000: 0000230d 7e420000 4756t0 write SP_DS_OBJ_OFFSET_REG (2334) 4757 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4758109d1864: 0000: 00002334 7e420000 4759t0 write SP_GS_OBJ_OFFSET_REG (235b) 4760 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 4761109d186c: 0000: 0000235b 7e420000 4762t0 write GRAS_CNTL (2003) 4763 GRAS_CNTL: { IJ_PERSP } 4764109d1874: 0000: 00002003 00000001 4765t0 write RB_RENDER_CONTROL2 (20a3) 4766 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 4767109d187c: 0000: 000020a3 00001000 4768t0 write RB_FS_OUTPUT_REG (2100) 4769 RB_FS_OUTPUT_REG: { MRT = 1 } 4770109d1884: 0000: 00002100 00000001 4771t0 write SP_FS_OUTPUT_REG (22f0) 4772 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 4773109d188c: 0000: 000022f0 0000fc01 4774t0 write SP_FS_MRT[0].REG (22f1) 4775 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 4776 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 4777 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 4778 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 4779 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 4780 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 4781 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 4782 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 4783109d1894: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 4784109d18b4: 0020: 00000002 4785t0 write VPC_ATTR (2140) 4786 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 4787 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 4788109d18b8: 0000: 00012140 42001004 00040400 4789t0 write VPC_VARYING_INTERP[0].MODE (2142) 4790 VPC_VARYING_INTERP[0].MODE: 0 4791 VPC_VARYING_INTERP[0x1].MODE: 0 4792 VPC_VARYING_INTERP[0x2].MODE: 0 4793 VPC_VARYING_INTERP[0x3].MODE: 0 4794 VPC_VARYING_INTERP[0x4].MODE: 0 4795 VPC_VARYING_INTERP[0x5].MODE: 0 4796 VPC_VARYING_INTERP[0x6].MODE: 0 4797 VPC_VARYING_INTERP[0x7].MODE: 0 4798109d18c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4799* 4800t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 4801 VPC_VARYING_PS_REPL[0].MODE: 0 4802 VPC_VARYING_PS_REPL[0x1].MODE: 0 4803 VPC_VARYING_PS_REPL[0x2].MODE: 0 4804 VPC_VARYING_PS_REPL[0x3].MODE: 0 4805 VPC_VARYING_PS_REPL[0x4].MODE: 0 4806 VPC_VARYING_PS_REPL[0x5].MODE: 0 4807 VPC_VARYING_PS_REPL[0x6].MODE: 0 4808 VPC_VARYING_PS_REPL[0x7].MODE: 0 4809109d18e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4810* 4811t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) 4812 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 4813 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 4814 :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x 4815 :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w 4816 :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x 4817 :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y 4818 :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x 4819 :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y 4820 :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x 4821 :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y 4822 :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y 4823 :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x 4824 :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x 4825 :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x 4826 :0:0012:0012[00000000x_00000000x] nop 4827 :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x 4828 :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z 4829 :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y 4830 :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x 4831 :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y 4832 :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x 4833 :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w 4834 :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x 4835 :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w 4836 :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z 4837 :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x 4838 :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x 4839 :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x 4840 :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z 4841 :0:0027:0027[00000200x_00000000x] (rpt2)nop 4842 :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w 4843 :0:0029:0031[00000000x_00000000x] nop 4844 :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x 4845 :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x 4846 :0:0032:0034[00000200x_00000000x] (rpt2)nop 4847 :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y 4848 :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x 4849 :0:0035:0039[00000200x_00000000x] (rpt2)nop 4850 :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x 4851 :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x 4852 :0:0038:0044[00000200x_00000000x] (rpt2)nop 4853 :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x 4854 :0:0040:0048[00000200x_00000000x] (rpt2)nop 4855 :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x 4856 :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x 4857 :0:0043:0053[00000100x_00000000x] (rpt1)nop 4858 :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x 4859 :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y 4860 :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z 4861 :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w 4862 :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y 4863 :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z 4864 :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x 4865 :0:0051:0062[03000000x_00000000x] end 4866 :0:0052:0063[00000000x_00000000x] nop 4867 :0:0053:0064[00000000x_00000000x] nop 4868 :0:0054:0065[00000000x_00000000x] nop 4869 :0:0055:0066[00000000x_00000000x] nop 4870 Register Stats: 4871 - used (half): (cnt=0, max=0) 4872 - used (full): 0-8 10-17 (cnt=17, max=17) 4873 - input (half): (cnt=0, max=0) 4874 - input (full): 2-8 (cnt=7, max=8) 4875 - max const: 52 4876 4877 - output (half): (cnt=0, max=0) (estimated) 4878 - output (full): 10-17 (cnt=8, max=17) (estimated) 4879 - shaderdb: 67 instructions, 23 nops, 44 non-nops, (56 instlen), 0 last-baryf, 0 half, 5 full 4880 - shaderdb: 24 cat0, 5 cat1, 15 cat2, 22 cat3, 1 cat4, 0 cat5, 0 cat6, 0 cat7 4881 - shaderdb: 1 (ss), 0 (sy) 4882109d190c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 4883109d192c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c 4884109d194c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 4885109d196c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 4886109d198c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a 4887109d19ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d 4888109d19cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 4889109d19ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 4890109d1a0c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 4891109d1a2c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 4892109d1a4c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 4893109d1a6c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 4894109d1a8c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 4895109d1aac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 4896* 4897t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 4898 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 4899 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 4900 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x 4901 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x 4902 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x 4903 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x 4904 :0:0004:0004[03000000x_00000000x] end 4905 :0:0005:0005[00000000x_00000000x] nop 4906 :0:0006:0006[00000000x_00000000x] nop 4907 :0:0007:0007[00000000x_00000000x] nop 4908 :0:0008:0008[00000000x_00000000x] nop 4909 Register Stats: 4910 - used (half): (cnt=0, max=0) 4911 - used (full): 0 2-5 (cnt=5, max=5) 4912 - input (half): (cnt=0, max=0) 4913 - input (full): 0 (cnt=1, max=0) 4914 - max const: 0 4915 4916 - output (half): (cnt=0, max=0) (estimated) 4917 - output (full): 2-5 (cnt=4, max=5) (estimated) 4918 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full 4919 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 4920 - shaderdb: 0 (ss), 0 (sy) 4921109d1b18: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 4922109d1b38: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 4923* 4924t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 4925109d1ba4: 0000: c0002600 00000000 4926t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) 4927 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } 4928 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } 4929109d1bb8: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 4930109d1bd8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 4931109d1bf8: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000 4932109d1c18: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 4933109d1c38: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000 4934109d1c58: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 4935109d1bb8: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc 4936109d1bd8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f 4937109d1bf8: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 4938109d1c18: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 4939109d1c38: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 4940109d1c58: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 4941109d1bac: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4942109d1bcc: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4943109d1bec: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 4944109d1c0c: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 4945109d1c2c: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 4946109d1c4c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 4947109d1c6c: 00c0: 02020202 02020202 00000202 4948t0 write VFD_INDEX_OFFSET (2208) 4949 VFD_INDEX_OFFSET: 0 4950 UNKNOWN_2209: 0 4951109d1c78: 0000: 00012208 00000000 00000000 4952t0 write PC_RESTART_INDEX (21c6) 4953 PC_RESTART_INDEX: 0xffffffff 4954109d1c84: 0000: 000021c6 ffffffff 4955t0 write CP_SCRATCH[0x7].REG (057f) 4956 CP_SCRATCH[0x7].REG: 0x6e 4957 :0,109,115,110 4958109d1c8c: 0000: 0000057f 0000006e 4959t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) 4960 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } 4961 { NUM_INSTANCES = 1 } 4962 { NUM_INDICES = 60 } 4963 { FIRST_INDX = 0 } 4964 { INDX_BASE = 0x10bd1428 } 4965 { INDX_SIZE = 120 } 4966 draw[18] register values 4967!+ 0000006d CP_SCRATCH[0x5].REG: 0x6d 4968 :0,109,115,110 4969!+ 0000006e CP_SCRATCH[0x7].REG: 0x6e 4970 :0,109,115,110 4971 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 4972!+ 00000001 GRAS_CNTL: { IJ_PERSP } 4973 + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } 4974 + 00000010 GRAS_SU_POINT_SIZE: 1.000000 4975 + 00000000 GRAS_ALPHA_CONTROL: { 0 } 4976 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 4977 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 4978 + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 4979 + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } 4980 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 4981 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 4982!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } 4983 + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } 4984 + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } 4985 + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 4986 + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff 4987 + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } 4988 + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } 4989!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 4990 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 4991 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 4992 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 4993 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 4994 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 4995 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 4996 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 4997 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 4998 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 4999 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 5000 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 5001 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 5002 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 5003 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 5004 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 5005 + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } 5006 + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } 5007 + ffffffff PC_RESTART_INDEX: 0xffffffff 5008 + 00000000 VFD_INDEX_OFFSET: 0 5009 + 00000000 UNKNOWN_2209: 0 5010 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 5011 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 5012 + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 5013 + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } 5014 + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } 5015 + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } 5016 + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } 5017 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 5018 + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 5019 + 00000004 SP_VS_LENGTH_REG: 4 5020!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 5021 + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } 5022 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5023!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 5024 + 00000001 SP_FS_LENGTH_REG: 1 5025 + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 5026!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } 5027!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } 5028!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } 5029!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } 5030!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } 5031!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } 5032!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } 5033!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } 5034 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5035 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5036 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5037 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 5038 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 5039 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 5040!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 5041 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 5042 + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } 5043 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 5044 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5045 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5046 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5047 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 5048109d1c94: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1428 00000078 5049t0 write CP_SCRATCH[0x7].REG (057f) 5050 CP_SCRATCH[0x7].REG: 0x6f 5051 :0,109,115,111 5052109d1cb0: 0000: 0000057f 0000006f 5053108ce2d0: 0000: c0013f00 109ce000 00000f2e 5054t2 nop 5055t0 write RB_DEPTH_CONTROL (2101) 5056 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 5057108ce2e8: 0000: 00002101 00000000 5058t0 write RB_STENCIL_CONTROL (2106) 5059 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 5060 RB_STENCIL_CONTROL2: { 0 } 5061108ce2f0: 0000: 00012106 00000000 00000000 5062t0 write RB_STENCILREFMASK (210b) 5063 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 5064 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 5065108ce2fc: 0000: 0001210b ffff0000 ffff0000 5066t0 write GRAS_SU_MODE_CONTROL (2078) 5067 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 5068108ce308: 0000: 00002078 00000000 5069t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) 5070108ce310: 0000: c0002600 00000000 5071t0 write GRAS_CL_CLIP_CNTL (2000) 5072 GRAS_CL_CLIP_CNTL: { 0x80000 } 5073108ce318: 0000: 00002000 00080000 5074t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) 5075 GRAS_CL_VPORT_XOFFSET_0: 150.000000 5076 GRAS_CL_VPORT_XSCALE_0: 150.000000 5077 GRAS_CL_VPORT_YOFFSET_0: 150.000000 5078 GRAS_CL_VPORT_YSCALE_0: -150.000000 5079 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 5080 GRAS_CL_VPORT_ZSCALE_0: 1.000000 5081108ce320: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000 5082t0 write RB_RENDER_CONTROL (20a1) 5083 RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa } 5084108ce33c: 0000: 000020a1 0000002a 5085t0 write GRAS_SC_CONTROL (207b) 5086 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 } 5087108ce344: 0000: 0000207b 00001808 5088t0 write PC_PRIM_VTX_CNTL (21c4) 5089 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 5090108ce34c: 0000: 000021c4 02000000 5091t0 write GRAS_ALPHA_CONTROL (2073) 5092 GRAS_ALPHA_CONTROL: { 0x2 } 5093108ce354: 0000: 00002073 00000002 5094t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) 5095 GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 5096 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5097108ce35c: 0000: 0001209c 012b012b 00000000 5098t0 write VFD_INDEX_OFFSET (2208) 5099 VFD_INDEX_OFFSET: 0 5100 UNKNOWN_2209: 0 5101108ce368: 0000: 00012208 00000000 00000000 5102t0 write HLSQ_UPDATE_CONTROL (23db) 5103 HLSQ_UPDATE_CONTROL: 0x3 5104108ce374: 0000: 000023db 00000003 5105t0 write HLSQ_CONTROL_0_REG (23c0) 5106 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 5107 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 5108 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 5109 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 5110 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 5111108ce37c: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc 5112t0 write HLSQ_VS_CONTROL_REG (23c5) 5113 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 5114 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 5115 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5116 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5117 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5118108ce394: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200 5119t0 write SP_SP_CTRL_REG (22c0) 5120 SP_SP_CTRL_REG: { 0x140010 } 5121108ce3ac: 0000: 000022c0 00140010 5122t0 write SP_INSTR_CACHE_CTRL (22c1) 5123 SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 5124108ce3b4: 0000: 000022c1 000005ff 5125t0 write SP_VS_LENGTH_REG (22e5) 5126 SP_VS_LENGTH_REG: 1 5127108ce3bc: 0000: 000022e5 00000001 5128t0 write SP_VS_CTRL_REG0 (22c4) 5129 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 5130 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 5131 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } 5132108ce3c4: 0000: 000222c4 00200400 04000042 0000fc00 5133t0 write SP_VS_OBJ_OFFSET_REG (22e0) 5134 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 5135 SP_VS_OBJ_START: 0x1073c000 5136108ce3d4: 0000: 000122e0 00000000 1073c000 5137t0 write SP_FS_LENGTH_REG (22ef) 5138 SP_FS_LENGTH_REG: 1 5139108ce3e0: 0000: 000022ef 00000001 5140t0 write SP_FS_CTRL_REG0 (22e8) 5141 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 5142 SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } 5143108ce3e8: 0000: 000122e8 00340400 8000003e 5144t0 write SP_FS_OBJ_OFFSET_REG (22ea) 5145 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5146 SP_FS_OBJ_START: 0x1073b000 5147108ce3f4: 0000: 000122ea 7e420000 1073b000 5148t0 write SP_HS_OBJ_OFFSET_REG (230d) 5149 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5150108ce400: 0000: 0000230d 7e420000 5151t0 write SP_DS_OBJ_OFFSET_REG (2334) 5152 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5153108ce408: 0000: 00002334 7e420000 5154t0 write SP_GS_OBJ_OFFSET_REG (235b) 5155 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5156108ce410: 0000: 0000235b 7e420000 5157t0 write GRAS_CNTL (2003) 5158 GRAS_CNTL: { 0 } 5159108ce418: 0000: 00002003 00000000 5160t0 write RB_RENDER_CONTROL2 (20a3) 5161 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 5162108ce420: 0000: 000020a3 00000000 5163t0 write RB_FS_OUTPUT_REG (2100) 5164 RB_FS_OUTPUT_REG: { MRT = 0 } 5165108ce428: 0000: 00002100 00000000 5166t0 write SP_FS_OUTPUT_REG (22f0) 5167 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 5168108ce430: 0000: 000022f0 0000fc00 5169t0 write SP_FS_MRT[0].REG (22f1) 5170 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 } 5171 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 5172 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 5173 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 5174 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 5175 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 5176 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 5177 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 5178108ce438: 0000: 000722f1 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5179* 5180t0 write VPC_ATTR (2140) 5181 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 5182 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 5183108ce45c: 0000: 00012140 40001000 00000000 5184t0 write VPC_VARYING_INTERP[0].MODE (2142) 5185 VPC_VARYING_INTERP[0].MODE: 0 5186 VPC_VARYING_INTERP[0x1].MODE: 0 5187 VPC_VARYING_INTERP[0x2].MODE: 0 5188 VPC_VARYING_INTERP[0x3].MODE: 0 5189 VPC_VARYING_INTERP[0x4].MODE: 0 5190 VPC_VARYING_INTERP[0x5].MODE: 0 5191 VPC_VARYING_INTERP[0x6].MODE: 0 5192 VPC_VARYING_INTERP[0x7].MODE: 0 5193108ce468: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5194* 5195t0 write VPC_VARYING_PS_REPL[0].MODE (214a) 5196 VPC_VARYING_PS_REPL[0].MODE: 0 5197 VPC_VARYING_PS_REPL[0x1].MODE: 0 5198 VPC_VARYING_PS_REPL[0x2].MODE: 0 5199 VPC_VARYING_PS_REPL[0x3].MODE: 0 5200 VPC_VARYING_PS_REPL[0x4].MODE: 0 5201 VPC_VARYING_PS_REPL[0x5].MODE: 0 5202 VPC_VARYING_PS_REPL[0x6].MODE: 0 5203 VPC_VARYING_PS_REPL[0x7].MODE: 0 5204108ce48c: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5205* 5206t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 5207 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } 5208 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 5209 :0:0000:0000[03000000x_00000000x] end 5210 :0:0001:0001[00000000x_00000000x] nop 5211 :0:0002:0002[00000000x_00000000x] nop 5212 :0:0003:0003[00000000x_00000000x] nop 5213 :0:0004:0004[00000000x_00000000x] nop 5214 Register Stats: 5215 - used (half): (cnt=0, max=0) 5216 - used (full): (cnt=0, max=0) 5217 - input (half): (cnt=0, max=0) 5218 - input (full): (cnt=0, max=0) 5219 - max const: 0 5220 5221 - output (half): (cnt=0, max=0) (estimated) 5222 - output (full): (cnt=0, max=0) (estimated) 5223 - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 last-baryf, 0 half, 0 full 5224 - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 5225 - shaderdb: 0 (ss), 0 (sy) 5226108ce4b0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000 5227* 5228t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) 5229 { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } 5230 { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } 5231 :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x 5232 :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y 5233 :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z 5234 :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w 5235 :0:0004:0004[03000000x_00000000x] end 5236 :0:0005:0005[00000000x_00000000x] nop 5237 :0:0006:0006[00000000x_00000000x] nop 5238 :0:0007:0007[00000000x_00000000x] nop 5239 :0:0008:0008[00000000x_00000000x] nop 5240 Register Stats: 5241 - used (half): (cnt=0, max=0) 5242 - used (full): 0-3 (cnt=4, max=3) 5243 - input (half): (cnt=0, max=0) 5244 - input (full): (cnt=0, max=0) 5245 - max const: 3 5246 5247 - output (half): (cnt=0, max=0) (estimated) 5248 - output (full): 0-3 (cnt=4, max=3) (estimated) 5249 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 last-baryf, 0 half, 1 full 5250 - shaderdb: 5 cat0, 4 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 5251 - shaderdb: 0 (ss), 0 (sy) 5252108ce53c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002 5253108ce55c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000 5254* 5255t0 write VFD_FETCH[0].INSTR_0 (220a) 5256 VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 5257 VFD_FETCH[0].INSTR_1: 0x1074a000 5258 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } 5259 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 5260108ce5c8: 0000: 0003220a 0000060b 1074a000 00001000 00000001 5261t0 write VFD_DECODE[0].INSTR (228a) 5262 VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 5263108ce5dc: 0000: 0000228a 2c0000df 5264t0 write VFD_CONTROL_0 (2200) 5265 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 5266 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 5267 VFD_CONTROL_2: 0 5268 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 5269 VFD_CONTROL_4: 0 5270108ce5e4: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 5271t0 write UCHE_INVALIDATE0 (0e8a) 5272 UCHE_INVALIDATE0: 0 5273 UCHE_INVALIDATE1: 0x12 5274108ce5fc: 0000: 00010e8a 00000000 00000012 5275t0 write RB_COPY_CONTROL (20fc) 5276 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 } 5277 RB_COPY_DEST_BASE: { BASE = 0x10edc000 } 5278 RB_COPY_DEST_PITCH: { PITCH = 1280 } 5279 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } 5280108ce608: 0000: 000320fc 00064010 10edc000 00000028 0003c068 5281t0 write CP_SCRATCH[0x7].REG (057f) 5282 CP_SCRATCH[0x7].REG: 0x75 5283 :0,109,115,117 5284108ce61c: 0000: 0000057f 00000075 5285t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) 5286 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } 5287 { NUM_INSTANCES = 1 } 5288 { NUM_INDICES = 2 } 5289 draw[19] register values 5290!+ 00000075 CP_SCRATCH[0x7].REG: 0x75 5291 :0,109,115,117 5292 + 00000000 UCHE_INVALIDATE0: 0 5293 + 00000012 UCHE_INVALIDATE1: 0x12 5294 + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } 5295!+ 00000000 GRAS_CNTL: { 0 } 5296 + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 5297 + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 5298 + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 5299 + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 5300!+ 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 5301!+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000 5302!+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } 5303!+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } 5304!+ 00001808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 } 5305 + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } 5306 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } 5307!+ 0000002a RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa } 5308!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } 5309!+ 00064010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 } 5310!+ 10edc000 RB_COPY_DEST_BASE: { BASE = 0x10edc000 } 5311!+ 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } 5312!+ 0003c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } 5313!+ 00000000 RB_FS_OUTPUT_REG: { MRT = 0 } 5314!+ 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } 5315 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } 5316 + 00000000 RB_STENCIL_CONTROL2: { 0 } 5317!+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 5318!+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } 5319!+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } 5320!+ 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } 5321 + 00000000 VPC_VARYING_INTERP[0].MODE: 0 5322 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 5323 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 5324 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 5325 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 5326 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 5327 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 5328 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 5329 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 5330 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 5331 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 5332 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 5333 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 5334 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 5335 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 5336 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 5337!+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } 5338!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } 5339 + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } 5340 + 00000000 VFD_CONTROL_2: 0 5341 + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } 5342 + 00000000 VFD_CONTROL_4: 0 5343 + 00000000 VFD_INDEX_OFFSET: 0 5344 + 00000000 UNKNOWN_2209: 0 5345!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } 5346!+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000 5347!+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } 5348 + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } 5349!+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } 5350 + 00140010 SP_SP_CTRL_REG: { 0x140010 } 5351 + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } 5352!+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } 5353!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } 5354!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } 5355 + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } 5356!+ 1073c000 SP_VS_OBJ_START: 0x1073c000 5357!+ 00000001 SP_VS_LENGTH_REG: 1 5358!+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } 5359!+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } 5360 + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5361!+ 1073b000 SP_FS_OBJ_START: 0x1073b000 5362 + 00000001 SP_FS_LENGTH_REG: 1 5363!+ 0000fc00 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } 5364!+ 00000000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 } 5365!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } 5366!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } 5367!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } 5368!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } 5369!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } 5370!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } 5371!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } 5372 + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5373 + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5374 + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } 5375 + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } 5376 + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } 5377 + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } 5378!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } 5379 + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } 5380!+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } 5381 + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } 5382 + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5383 + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5384 + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } 5385 + 00000003 HLSQ_UPDATE_CONTROL: 0x3 5386108ce624: 0000: c0023800 00000088 00000001 00000002 5387t0 write CP_SCRATCH[0x7].REG (057f) 5388 CP_SCRATCH[0x7].REG: 0x76 5389 :0,109,115,118 5390108ce634: 0000: 0000057f 00000076 5391t0 write RB_COPY_CONTROL (20fc) 5392 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } 5393 RB_COPY_DEST_BASE: { BASE = 0x10f3c000 } 5394 RB_COPY_DEST_PITCH: { PITCH = 1280 } 5395 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } 5396108ce63c: 0000: 000320fc 00000010 10f3c000 00000028 0003c168 5397t0 write CP_SCRATCH[0x7].REG (057f) 5398 CP_SCRATCH[0x7].REG: 0x77 5399 :0,109,115,119 5400108ce650: 0000: 0000057f 00000077 5401t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) 5402 { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } 5403 { NUM_INSTANCES = 1 } 5404 { NUM_INDICES = 2 } 5405 draw[20] register values 5406!+ 00000077 CP_SCRATCH[0x7].REG: 0x77 5407 :0,109,115,119 5408!+ 00000010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } 5409!+ 10f3c000 RB_COPY_DEST_BASE: { BASE = 0x10f3c000 } 5410 + 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } 5411!+ 0003c168 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } 5412108ce658: 0000: c0023800 00000088 00000001 00000002 5413t0 write CP_SCRATCH[0x7].REG (057f) 5414 CP_SCRATCH[0x7].REG: 0x78 5415 :0,109,115,120 5416108ce668: 0000: 0000057f 00000078 5417t0 write GRAS_SC_CONTROL (207b) 5418 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } 5419108ce670: 0000: 0000207b 00000800 5420############################################################ 5421vertices: 0 5422cmd: glxgears/23375: fence=1029605 5423cmd: glxgears/23375: fence=1029606 5424cmd: glxgears/23375: fence=1029607 5425cmd: glxgears/23375: fence=1029608 5426cmd: glxgears/23375: fence=1029609 5427cmd: glxgears/23375: fence=1029610 5428cmd: glxgears/23375: fence=1029611 5429cmd: glxgears/23375: fence=1029612 5430cmd: glxgears/23375: fence=1029613 5431cmd: glxgears/23375: fence=1029614 5432cmd: glxgears/23375: fence=1029615 5433cmd: glxgears/23375: fence=1029616 5434cmd: glxgears/23375: fence=1029617 5435cmd: glxgears/23375: fence=1029618 5436cmd: glxgears/23375: fence=1029619 5437cmd: glxgears/23375: fence=1029620 5438cmd: glxgears/23375: fence=1029621 5439cmd: glxgears/23375: fence=1029622 5440cmd: glxgears/23375: fence=1029623 5441cmd: glxgears/23375: fence=1029624 5442cmd: glxgears/23375: fence=1029625 5443cmd: glxgears/23375: fence=1029626 5444cmd: glxgears/23375: fence=1029627 5445cmd: glxgears/23375: fence=1029628 5446cmd: glxgears/23375: fence=1029629 5447cmd: glxgears/23375: fence=1029630 5448cmd: glxgears/23375: fence=1029631 5449cmd: glxgears/23375: fence=1029632 5450cmd: glxgears/23375: fence=1029633 5451cmd: glxgears/23375: fence=1029634 5452cmd: glxgears/23375: fence=1029635 5453cmd: glxgears/23375: fence=1029636 5454cmd: glxgears/23375: fence=1029637 5455cmd: glxgears/23375: fence=1029638 5456cmd: glxgears/23375: fence=1029639 5457cmd: glxgears/23375: fence=1029640 5458cmd: glxgears/23375: fence=1029641 5459cmd: glxgears/23375: fence=1029642 5460cmd: glxgears/23375: fence=1029643 5461cmd: glxgears/23375: fence=1029644 5462cmd: glxgears/23375: fence=1029645 5463cmd: glxgears/23375: fence=1029646 5464cmd: glxgears/23375: fence=1029647 5465cmd: glxgears/23375: fence=1029648 5466cmd: glxgears/23375: fence=1029649 5467cmd: glxgears/23375: fence=1029650 5468cmd: glxgears/23375: fence=1029651 5469cmd: glxgears/23375: fence=1029652 5470cmd: glxgears/23375: fence=1029653 5471cmd: glxgears/23375: fence=1029654 5472cmd: glxgears/23375: fence=1029655 5473cmd: glxgears/23375: fence=1029656 5474cmd: glxgears/23375: fence=1029657 5475cmd: glxgears/23375: fence=1029658 5476cmd: glxgears/23375: fence=1029659 5477cmd: glxgears/23375: fence=1029660 5478cmd: glxgears/23375: fence=1029661 5479cmd: glxgears/23375: fence=1029662 5480cmd: glxgears/23375: fence=1029663 5481cmd: glxgears/23375: fence=1029664 5482cmd: glxgears/23375: fence=1029665 5483cmd: glxgears/23375: fence=1029666 5484cmd: glxgears/23375: fence=1029667 5485cmd: glxgears/23375: fence=1029668 5486cmd: glxgears/23375: fence=1029669 5487cmd: glxgears/23375: fence=1029670 5488cmd: glxgears/23375: fence=1029671 5489cmd: glxgears/23375: fence=1029672 5490cmd: glxgears/23375: fence=1029673 5491cmd: glxgears/23375: fence=1029674 5492cmd: glxgears/23375: fence=1029675 5493cmd: glxgears/23375: fence=1029676 5494cmd: glxgears/23375: fence=1029677 5495cmd: glxgears/23375: fence=1029678 5496cmd: glxgears/23375: fence=1029679 5497cmd: glxgears/23375: fence=1029680 5498cmd: glxgears/23375: fence=1029681 5499cmd: glxgears/23375: fence=1029682 5500cmd: glxgears/23375: fence=1029683 5501cmd: glxgears/23375: fence=1029684 5502cmd: glxgears/23375: fence=1029685 5503cmd: glxgears/23375: fence=1029686 5504cmd: glxgears/23375: fence=1029687 5505cmd: glxgears/23375: fence=1029688 5506cmd: glxgears/23375: fence=1029689 5507cmd: glxgears/23375: fence=1029690 5508cmd: glxgears/23375: fence=1029691 5509cmd: glxgears/23375: fence=1029692 5510cmd: glxgears/23375: fence=1029693 5511cmd: glxgears/23375: fence=1029694 5512cmd: glxgears/23375: fence=1029695 5513cmd: glxgears/23375: fence=1029696 5514cmd: glxgears/23375: fence=1029697 5515cmd: glxgears/23375: fence=1029698 5516cmd: glxgears/23375: fence=1029699 5517cmd: glxgears/23375: fence=1029700 5518cmd: glxgears/23375: fence=1029701 5519cmd: glxgears/23375: fence=1029702 5520cmd: glxgears/23375: fence=1029703 5521cmd: glxgears/23375: fence=1029704 5522cmd: glxgears/23375: fence=1029705 5523cmd: glxgears/23375: fence=1029706 5524cmd: glxgears/23375: fence=1029707 5525cmd: glxgears/23375: fence=1029708 5526cmd: glxgears/23375: fence=1029709 5527cmd: glxgears/23375: fence=1029710 5528cmd: glxgears/23375: fence=1029711 5529cmd: glxgears/23375: fence=1029712 5530cmd: glxgears/23375: fence=1029713 5531cmd: glxgears/23375: fence=1029714 5532cmd: glxgears/23375: fence=1029715 5533cmd: glxgears/23375: fence=1029716 5534cmd: glxgears/23375: fence=1029717 5535cmd: glxgears/23375: fence=1029718 5536cmd: glxgears/23375: fence=1029719 5537cmd: glxgears/23375: fence=1029720 5538cmd: glxgears/23375: fence=1029721 5539cmd: glxgears/23375: fence=1029722 5540cmd: glxgears/23375: fence=1029723 5541cmd: glxgears/23375: fence=1029724 5542cmd: glxgears/23375: fence=1029725 5543cmd: glxgears/23375: fence=1029726 5544cmd: glxgears/23375: fence=1029727 5545cmd: glxgears/23375: fence=1029728 5546cmd: glxgears/23375: fence=1029729 5547cmd: glxgears/23375: fence=1029730 5548cmd: glxgears/23375: fence=1029731 5549cmd: glxgears/23375: fence=1029732 5550cmd: glxgears/23375: fence=1029733 5551cmd: glxgears/23375: fence=1029734 5552cmd: glxgears/23375: fence=1029735 5553cmd: glxgears/23375: fence=1029736 5554cmd: glxgears/23375: fence=1029737 5555cmd: glxgears/23375: fence=1029738 5556cmd: glxgears/23375: fence=1029739 5557cmd: glxgears/23375: fence=1029740 5558cmd: glxgears/23375: fence=1029741 5559cmd: glxgears/23375: fence=1029742 5560cmd: glxgears/23375: fence=1029743 5561cmd: glxgears/23375: fence=1029744 5562cmd: glxgears/23375: fence=1029745 5563cmd: glxgears/23375: fence=1029746 5564cmd: glxgears/23375: fence=1029747 5565cmd: glxgears/23375: fence=1029748 5566cmd: glxgears/23375: fence=1029749 5567cmd: glxgears/23375: fence=1029750 5568cmd: glxgears/23375: fence=1029751 5569cmd: glxgears/23375: fence=1029752 5570cmd: glxgears/23375: fence=1029753 5571cmd: glxgears/23375: fence=1029754 5572cmd: glxgears/23375: fence=1029755 5573cmd: glxgears/23375: fence=1029756 5574cmd: glxgears/23375: fence=1029757 5575cmd: glxgears/23375: fence=1029758 5576cmd: glxgears/23375: fence=1029759 5577cmd: glxgears/23375: fence=1029760 5578cmd: glxgears/23375: fence=1029761 5579cmd: glxgears/23375: fence=1029762 5580cmd: glxgears/23375: fence=1029763 5581cmd: glxgears/23375: fence=1029764 5582cmd: glxgears/23375: fence=1029765 5583cmd: glxgears/23375: fence=1029766 5584cmd: glxgears/23375: fence=1029767 5585cmd: glxgears/23375: fence=1029768 5586cmd: glxgears/23375: fence=1029769 5587cmd: glxgears/23375: fence=1029770 5588cmd: glxgears/23375: fence=1029771 5589cmd: glxgears/23375: fence=1029772 5590cmd: glxgears/23375: fence=1029773 5591cmd: glxgears/23375: fence=1029774 5592cmd: glxgears/23375: fence=1029775 5593cmd: glxgears/23375: fence=1029776 5594cmd: glxgears/23375: fence=1029777 5595cmd: glxgears/23375: fence=1029778 5596cmd: glxgears/23375: fence=1029779 5597cmd: glxgears/23375: fence=1029780 5598cmd: glxgears/23375: fence=1029781 5599cmd: glxgears/23375: fence=1029782 5600cmd: glxgears/23375: fence=1029783 5601cmd: glxgears/23375: fence=1029784 5602cmd: glxgears/23375: fence=1029785 5603cmd: glxgears/23375: fence=1029786 5604cmd: glxgears/23375: fence=1029787 5605cmd: glxgears/23375: fence=1029788 5606cmd: glxgears/23375: fence=1029789 5607cmd: glxgears/23375: fence=1029790 5608cmd: glxgears/23375: fence=1029791 5609cmd: glxgears/23375: fence=1029792 5610cmd: glxgears/23375: fence=1029793 5611cmd: glxgears/23375: fence=1029794 5612cmd: glxgears/23375: fence=1029795 5613cmd: glxgears/23375: fence=1029796 5614cmd: glxgears/23375: fence=1029797 5615cmd: glxgears/23375: fence=1029798 5616cmd: glxgears/23375: fence=1029799 5617cmd: glxgears/23375: fence=1029800 5618cmd: glxgears/23375: fence=1029801 5619cmd: glxgears/23375: fence=1029802 5620cmd: glxgears/23375: fence=1029803 5621cmd: glxgears/23375: fence=1029804 5622cmd: glxgears/23375: fence=1029805 5623cmd: glxgears/23375: fence=1029806 5624cmd: glxgears/23375: fence=1029807 5625cmd: glxgears/23375: fence=1029808 5626cmd: glxgears/23375: fence=1029809 5627cmd: glxgears/23375: fence=1029810 5628cmd: glxgears/23375: fence=1029811 5629cmd: glxgears/23375: fence=1029812 5630cmd: glxgears/23375: fence=1029813 5631cmd: glxgears/23375: fence=1029814 5632cmd: glxgears/23375: fence=1029815 5633cmd: glxgears/23375: fence=1029816 5634cmd: glxgears/23375: fence=1029817 5635cmd: glxgears/23375: fence=1029818 5636cmd: glxgears/23375: fence=1029819 5637cmd: glxgears/23375: fence=1029820 5638cmd: glxgears/23375: fence=1029821 5639cmd: glxgears/23375: fence=1029822 5640cmd: glxgears/23375: fence=1029823 5641cmd: glxgears/23375: fence=1029824 5642cmd: glxgears/23375: fence=1029825 5643cmd: glxgears/23375: fence=1029826 5644cmd: glxgears/23375: fence=1029827 5645cmd: glxgears/23375: fence=1029828 5646cmd: X/23360: fence=1029829 5647cmd: glxgears/23375: fence=1029830 5648cmd: glxgears/23375: fence=1029831 5649cmd: X/23360: fence=1029832 5650cmd: glxgears/23375: fence=1029833 5651cmd: glxgears/23375: fence=1029834 5652cmd: X/23360: fence=1029835 5653cmd: glxgears/23375: fence=1029836 5654cmd: glxgears/23375: fence=1029837 5655cmd: X/23360: fence=1029838 5656cmd: glxgears/23375: fence=1029839 5657cmd: glxgears/23375: fence=1029840 5658cmd: X/23360: fence=1029841 5659cmd: glxgears/23375: fence=1029842 5660cmd: glxgears/23375: fence=1029843 5661cmd: X/23360: fence=1029844 5662cmd: glxgears/23375: fence=1029845 5663cmd: glxgears/23375: fence=1029846 5664cmd: X/23360: fence=1029847 5665