1 // Copyright 2022 The Pigweed Authors
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not
4 // use this file except in compliance with the License. You may obtain a copy of
5 // the License at
6 //
7 // https://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
12 // License for the specific language governing permissions and limitations under
13 // the License.
14
15 #include "pw_boot/boot.h"
16
17 #include <array>
18
19 #include "FreeRTOS.h"
20 #include "config/sf2_mss_hal_conf.h"
21 #include "m2sxxx.h"
22 #include "pw_boot_cortex_m/boot.h"
23 #include "pw_malloc/malloc.h"
24 #include "pw_preprocessor/compiler.h"
25 #include "pw_string/util.h"
26 #include "pw_sys_io_emcraft_sf2/init.h"
27 #include "pw_system/init.h"
28 #include "system_m2sxxx.h"
29 #include "task.h"
30
31 #include liberosoc_CONFIG_FILE
32
33 namespace {
34
35 std::array<StackType_t, configMINIMAL_STACK_SIZE> freertos_idle_stack;
36 StaticTask_t freertos_idle_tcb;
37
38 std::array<StackType_t, configTIMER_TASK_STACK_DEPTH> freertos_timer_stack;
39 StaticTask_t freertos_timer_tcb;
40
41 std::array<char, configMAX_TASK_NAME_LEN> temp_thread_name_buffer;
42
43 } // namespace
44
45 // Functions needed when configGENERATE_RUN_TIME_STATS is on.
configureTimerForRunTimeStats(void)46 extern "C" void configureTimerForRunTimeStats(void) {}
getRunTimeCounterValue(void)47 extern "C" unsigned long getRunTimeCounterValue(void) { return 10 /* FIXME */; }
48 // uwTick is an uint32_t incremented each Systick interrupt 1ms. uwTick is used
49 // to execute HAL_Delay function.
50
51 // Required for configCHECK_FOR_STACK_OVERFLOW.
vApplicationStackOverflowHook(TaskHandle_t,char * pcTaskName)52 extern "C" void vApplicationStackOverflowHook(TaskHandle_t, char* pcTaskName) {
53 pw::string::Copy(pcTaskName, temp_thread_name_buffer);
54 PW_CRASH("Stack OVF for task %s", temp_thread_name_buffer.data());
55 }
56
57 // Required for configUSE_TIMERS.
vApplicationGetTimerTaskMemory(StaticTask_t ** ppxIdleTaskTCBBuffer,StackType_t ** ppxIdleTaskStackBuffer,uint32_t * pulIdleTaskStackSize)58 extern "C" void vApplicationGetTimerTaskMemory(
59 StaticTask_t** ppxIdleTaskTCBBuffer,
60 StackType_t** ppxIdleTaskStackBuffer,
61 uint32_t* pulIdleTaskStackSize) {
62 *ppxIdleTaskTCBBuffer = &freertos_idle_tcb;
63 *ppxIdleTaskStackBuffer = freertos_idle_stack.data();
64 *pulIdleTaskStackSize = freertos_idle_stack.size();
65 }
66
vApplicationGetIdleTaskMemory(StaticTask_t ** ppxIdleTaskTCBBuffer,StackType_t ** ppxIdleTaskStackBuffer,uint32_t * pulIdleTaskStackSize)67 extern "C" void vApplicationGetIdleTaskMemory(
68 StaticTask_t** ppxIdleTaskTCBBuffer,
69 StackType_t** ppxIdleTaskStackBuffer,
70 uint32_t* pulIdleTaskStackSize) {
71 *ppxIdleTaskTCBBuffer = &freertos_timer_tcb;
72 *ppxIdleTaskStackBuffer = freertos_timer_stack.data();
73 *pulIdleTaskStackSize = freertos_timer_stack.size();
74 }
75
pw_boot_PreStaticMemoryInit()76 extern "C" void pw_boot_PreStaticMemoryInit() {
77 #if SF2_MSS_NO_BOOTLOADER
78 SystemInit();
79 // Initialize DDR
80 // inclusive-language: disable
81 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x0000;
82 MDDR->core.ddrc.DYN_REFRESH_1_CR = 0x27de;
83 MDDR->core.ddrc.DYN_REFRESH_2_CR = 0x030f;
84 MDDR->core.ddrc.DYN_POWERDOWN_CR = 0x0002;
85 MDDR->core.ddrc.DYN_DEBUG_CR = 0x0000;
86 MDDR->core.ddrc.MODE_CR = 0x00C1;
87 MDDR->core.ddrc.ADDR_MAP_BANK_CR = 0x099f;
88 MDDR->core.ddrc.ECC_DATA_MASK_CR = 0x0000;
89 MDDR->core.ddrc.ADDR_MAP_COL_1_CR = 0x3333;
90 MDDR->core.ddrc.ADDR_MAP_COL_2_CR = 0xffff;
91 MDDR->core.ddrc.ADDR_MAP_ROW_1_CR = 0x7777;
92 MDDR->core.ddrc.ADDR_MAP_ROW_2_CR = 0x0fff;
93 MDDR->core.ddrc.INIT_1_CR = 0x0001;
94 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[0] = 0x4242;
95 MDDR->core.ddrc.CKE_RSTN_CYCLES_CR[1] = 0x0008;
96 MDDR->core.ddrc.INIT_MR_CR = 0x0033;
97 MDDR->core.ddrc.INIT_EMR_CR = 0x0020;
98 MDDR->core.ddrc.INIT_EMR2_CR = 0x0000;
99 MDDR->core.ddrc.INIT_EMR3_CR = 0x0000;
100 MDDR->core.ddrc.DRAM_BANK_TIMING_PARAM_CR = 0x00c0;
101 MDDR->core.ddrc.DRAM_RD_WR_LATENCY_CR = 0x0023;
102 MDDR->core.ddrc.DRAM_RD_WR_PRE_CR = 0x0235;
103 MDDR->core.ddrc.DRAM_MR_TIMING_PARAM_CR = 0x0064;
104 MDDR->core.ddrc.DRAM_RAS_TIMING_CR = 0x0108;
105 MDDR->core.ddrc.DRAM_RD_WR_TRNARND_TIME_CR = 0x0178;
106 MDDR->core.ddrc.DRAM_T_PD_CR = 0x0033;
107 MDDR->core.ddrc.DRAM_BANK_ACT_TIMING_CR = 0x1947;
108 MDDR->core.ddrc.ODT_PARAM_1_CR = 0x0010;
109 MDDR->core.ddrc.ODT_PARAM_2_CR = 0x0000;
110 MDDR->core.ddrc.ADDR_MAP_COL_3_CR = 0x3300;
111 MDDR->core.ddrc.MODE_REG_RD_WR_CR = 0x0000;
112 MDDR->core.ddrc.MODE_REG_DATA_CR = 0x0000;
113 MDDR->core.ddrc.PWR_SAVE_1_CR = 0x0514;
114 MDDR->core.ddrc.PWR_SAVE_2_CR = 0x0000;
115 MDDR->core.ddrc.ZQ_LONG_TIME_CR = 0x0200;
116 MDDR->core.ddrc.ZQ_SHORT_TIME_CR = 0x0040;
117 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[0] = 0x0012;
118 MDDR->core.ddrc.ZQ_SHORT_INT_REFRESH_MARGIN_CR[1] = 0x0002;
119 MDDR->core.ddrc.PERF_PARAM_1_CR = 0x4000;
120 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[0] = 0x80f8;
121 MDDR->core.ddrc.HPR_QUEUE_PARAM_CR[1] = 0x0007;
122 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[0] = 0x80f8;
123 MDDR->core.ddrc.LPR_QUEUE_PARAM_CR[1] = 0x0007;
124 MDDR->core.ddrc.WR_QUEUE_PARAM_CR = 0x0200;
125 MDDR->core.ddrc.PERF_PARAM_2_CR = 0x0001;
126 MDDR->core.ddrc.PERF_PARAM_3_CR = 0x0000;
127 MDDR->core.ddrc.DFI_RDDATA_EN_CR = 0x0003;
128 MDDR->core.ddrc.DFI_MIN_CTRLUPD_TIMING_CR = 0x0003;
129 MDDR->core.ddrc.DFI_MAX_CTRLUPD_TIMING_CR = 0x0040;
130 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[0] = 0x0000;
131 MDDR->core.ddrc.DFI_WR_LVL_CONTROL_CR[1] = 0x0000;
132 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[0] = 0x0000;
133 MDDR->core.ddrc.DFI_RD_LVL_CONTROL_CR[1] = 0x0000;
134 MDDR->core.ddrc.DFI_CTRLUPD_TIME_INTERVAL_CR = 0x0309;
135 MDDR->core.ddrc.AXI_FABRIC_PRI_ID_CR = 0x0000;
136 MDDR->core.ddrc.ECC_INT_CLR_REG = 0x0000;
137
138 MDDR->core.phy.LOOPBACK_TEST_CR = 0x0000;
139 MDDR->core.phy.CTRL_SLAVE_RATIO_CR = 0x0080;
140 MDDR->core.phy.DATA_SLICE_IN_USE_CR = 0x0003;
141 MDDR->core.phy.DQ_OFFSET_CR[0] = 0x00000000;
142 MDDR->core.phy.DQ_OFFSET_CR[2] = 0x0000;
143 MDDR->core.phy.DLL_LOCK_DIFF_CR = 0x000B;
144 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[0] = 0x0040;
145 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[1] = 0x0401;
146 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[2] = 0x4010;
147 MDDR->core.phy.FIFO_WE_SLAVE_RATIO_CR[3] = 0x0000;
148 MDDR->core.phy.LOCAL_ODT_CR = 0x0001;
149 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[0] = 0x0040;
150 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[1] = 0x0401;
151 MDDR->core.phy.RD_DQS_SLAVE_RATIO_CR[2] = 0x4010;
152 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[0] = 0x0040;
153 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[1] = 0x0401;
154 MDDR->core.phy.WR_DATA_SLAVE_RATIO_CR[2] = 0x4010;
155 MDDR->core.phy.WR_RD_RL_CR = 0x0021;
156 MDDR->core.phy.RDC_WE_TO_RE_DELAY_CR = 0x0003;
157 MDDR->core.phy.USE_FIXED_RE_CR = 0x0001;
158 MDDR->core.phy.USE_RANK0_DELAYS_CR = 0x0001;
159 MDDR->core.phy.CONFIG_CR = 0x0009;
160 MDDR->core.phy.DYN_RESET_CR = 0x01;
161 MDDR->core.ddrc.DYN_SOFT_RESET_CR = 0x01;
162 // inclusive-language: enable
163 // Wait for config
164 while ((MDDR->core.ddrc.DDRC_SR) == 0x0000) {
165 }
166 #endif
167 }
168
pw_boot_PreStaticConstructorInit()169 extern "C" void pw_boot_PreStaticConstructorInit() {
170 // TODO(skeys) add "#if no_bootLoader" and the functions needed for init.
171
172 #if PW_MALLOC_ACTIVE
173 pw_MallocInit(&pw_boot_heap_low_addr, &pw_boot_heap_high_addr);
174 #endif // PW_MALLOC_ACTIVE
175 pw_sys_io_Init();
176 }
177
178 // TODO(amontanez): pw_boot_PreMainInit() should get renamed to
179 // pw_boot_FinalizeBoot or similar when main() is removed.
pw_boot_PreMainInit()180 extern "C" void pw_boot_PreMainInit() {
181 pw::system::Init();
182 vTaskStartScheduler();
183 PW_UNREACHABLE;
184 }
185
186 // This `main()` stub prevents another main function from being linked since
187 // this target deliberately doesn't run `main()`.
main()188 extern "C" int main() {}
189
pw_boot_PostMain()190 extern "C" PW_NO_RETURN void pw_boot_PostMain() {
191 // In case main() returns, just sit here until the device is reset.
192 while (true) {
193 }
194 PW_UNREACHABLE;
195 }
196